JPS61184345U - - Google Patents

Info

Publication number
JPS61184345U
JPS61184345U JP6831185U JP6831185U JPS61184345U JP S61184345 U JPS61184345 U JP S61184345U JP 6831185 U JP6831185 U JP 6831185U JP 6831185 U JP6831185 U JP 6831185U JP S61184345 U JPS61184345 U JP S61184345U
Authority
JP
Japan
Prior art keywords
clock
bit
frame
phase modulation
receiving circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6831185U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6831185U priority Critical patent/JPS61184345U/ja
Publication of JPS61184345U publication Critical patent/JPS61184345U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
JP6831185U 1985-05-09 1985-05-09 Pending JPS61184345U (enrdf_load_stackoverflow)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6831185U JPS61184345U (enrdf_load_stackoverflow) 1985-05-09 1985-05-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6831185U JPS61184345U (enrdf_load_stackoverflow) 1985-05-09 1985-05-09

Publications (1)

Publication Number Publication Date
JPS61184345U true JPS61184345U (enrdf_load_stackoverflow) 1986-11-17

Family

ID=30602946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6831185U Pending JPS61184345U (enrdf_load_stackoverflow) 1985-05-09 1985-05-09

Country Status (1)

Country Link
JP (1) JPS61184345U (enrdf_load_stackoverflow)

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