JPS61182908U - - Google Patents
Info
- Publication number
- JPS61182908U JPS61182908U JP6659885U JP6659885U JPS61182908U JP S61182908 U JPS61182908 U JP S61182908U JP 6659885 U JP6659885 U JP 6659885U JP 6659885 U JP6659885 U JP 6659885U JP S61182908 U JPS61182908 U JP S61182908U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- head
- gain
- limiter
- disk
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Digital Magnetic Recording (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
第１図はこの考案の一実施例による開ループ式
ＡＧＣ回路を用いたヘツドアンプの機能ブロツク
図、第２図はこの考案の他の実施例の機能ブロツ
ク図、第３図は閉ループ式ＡＧＣ回路を用いた従
来のヘツドアンプの機能ブロツク図である。
なお、図中、１はデイスクヘツド、２Ａと２Ｂ
はヘツドアンプ、２１はバツフアアンプリフアイ
ア、２２はゲインコントロール可能なアンプリフ
アイア、２３Ａはゲイン制御信号を作るためのコ
ントロール回路、２４はリミツタ、２４Ａはリミ
ツタのためのゲインコントロール回路である。な
お、図中、同一符号は同一、又は相当部分を示す
。
Figure 1 is a functional block diagram of a head amplifier using an open-loop AGC circuit according to one embodiment of this invention, Figure 2 is a functional block diagram of another embodiment of this invention, and Figure 3 is a closed-loop AGC circuit. FIG. 2 is a functional block diagram of the conventional head amplifier used. In addition, in the figure, 1 is the disk head, 2A and 2B
2 is a head amplifier, 21 is a buffer amplifier, 22 is a gain controllable amplifier, 23A is a control circuit for generating a gain control signal, 24 is a limiter, and 24A is a gain control circuit for the limiter. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
とするヘツドアンプ。 (2) 開ループ式ＡＧＣ回路は、デイスクヘツド
からの信号電圧が入力されるアンプリフアイアと
、このアンプリフアイアの制御信号入力端子へ接
続され前記デイスクヘツドからのデイスクのトラ
ツクを決定するシーク信号を、前記アンプリフア
イアのゲインを制御する制御信号に変換するコン
トロール回路とから成る実用新案登録請求の範囲
第１項記載のヘツドアンプ。 (3) アンプリフアイアの出力端子にリミツタを
接続した実用新案登録請求の範囲第２項記載のヘ
ツドアンプ。 (4) リミツタが受動的回路である実用新案登録
請求の範囲第３項記載のヘツドアンプ。 (5) リミツタがそのフイードバツクループにゲ
インコントロール回路を持つた可変ゲインアンプ
リフアイアである実用新案登録請求の範囲第３項
記載のヘツドアンプ。[Claims for Utility Model Registration] (1) A head amplifier characterized by using an open-loop AGC circuit. (2) The open-loop AGC circuit includes an amplifier that receives a signal voltage from the disk head, and a seek signal that is connected to the control signal input terminal of the amplifier and determines the track of the disk from the disk head. The head amplifier according to claim 1, comprising a control circuit for converting the gain of the amplifier into a control signal for controlling the gain of the amplifier. (3) The head amplifier according to claim 2 of the utility model registration, wherein a limiter is connected to the output terminal of the amplifier fire. (4) The head amplifier according to claim 3, wherein the limiter is a passive circuit. (5) The head amplifier according to claim 3, wherein the limiter is a variable gain amplifier amplifier having a gain control circuit in its feedback loop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6659885U JPS61182908U (en) | 1985-05-07 | 1985-05-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6659885U JPS61182908U (en) | 1985-05-07 | 1985-05-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61182908U true JPS61182908U (en) | 1986-11-14 |
Family
ID=30599661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6659885U Pending JPS61182908U (en) | 1985-05-07 | 1985-05-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61182908U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006527545A (en) * | 2003-06-06 | 2006-11-30 | サイエンティフィック−アトランタ， インコーポレイテッド | Optical receiver with open loop automatic gain control circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5236551A (en) * | 1975-09-19 | 1977-03-19 | Kohan Sendan Kikai Kk | Apparatus for flat correction |
-
1985
- 1985-05-07 JP JP6659885U patent/JPS61182908U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5236551A (en) * | 1975-09-19 | 1977-03-19 | Kohan Sendan Kikai Kk | Apparatus for flat correction |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006527545A (en) * | 2003-06-06 | 2006-11-30 | サイエンティフィック−アトランタ， インコーポレイテッド | Optical receiver with open loop automatic gain control circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61182908U (en) | ||
| EP0251530A3 (en) | Improvements relating to amplifier gain control circuit arrangements | |
| JPS61176820U (en) | ||
| JPS6355244U (en) | ||
| JPS60116718U (en) | Feedback control type output stabilization device | |
| JPS6190311U (en) | ||
| JPS58104013U (en) | AGC device | |
| JPH0178418U (en) | ||
| JPH01115378U (en) | ||
| JPS61103918U (en) | ||
| JPH01102902U (en) | ||
| JPS62121884U (en) | ||
| JPS6022017U (en) | automatic power control circuit | |
| JPS61168746U (en) | ||
| JPS62198711U (en) | ||
| JPS61174020U (en) | ||
| JPS58177823U (en) | linearizer | |
| JPS60149288U (en) | AGC circuit | |
| JPS63147077U (en) | ||
| JPS60184316U (en) | automatic attenuator control circuit | |
| JPH03117931U (en) | ||
| JPS62124658U (en) | ||
| JPH03113987U (en) | ||
| JPH0262822U (en) | ||
| JPH02141149U (en) |