JPS6117829U

JPS6117829U - Abnormal voltage detection relay

Info

Publication number: JPS6117829U
Application number: JP10301584U
Authority: JP
Inventors: 辰三佐藤
Original assignee: 日新電機株式会社
Priority date: 1984-07-06
Filing date: 1984-07-06
Publication date: 1986-02-01

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例の回路を示すブロック図、
第２図は雷サージ電圧発生時の各部の波形図、第３図は
しゃ断器開閉時の各部の波形図、第４図Ａ−Ｆは並行回
線の事故発生時の動作説明図、第５図はその場合の各部
の波形図である。１・・・母線、２・・・しゃ断器、３・・・変成器、４
・・・サージ電圧レベル検出回路、５・・・商用電圧レ
ベル検出回路、６・・・第１の遅延回路、７・・・第１
のアンドゲート、８・・・サージ信号保持回路、９・・
・第２の遅延回路、１０・・・第２のアンドゲー・ト、
１１・・・第３の遅延回路、１２・・・出力リレー。FIG. 1 is a block diagram showing a circuit of an embodiment of this invention.
Figure 2 is a waveform diagram of each part when a lightning surge voltage occurs, Figure 3 is a waveform diagram of various parts when a circuit breaker opens and closes, Figures 4 A-F are diagrams explaining the operation when a fault occurs in a parallel line, and Figure 5 is a waveform diagram of each part in that case. 1... bus bar, 2... breaker, 3... transformer, 4
... surge voltage level detection circuit, 5 ... commercial voltage level detection circuit, 6 ... first delay circuit, 7 ... first
AND gate, 8... Surge signal holding circuit, 9...
- Second delay circuit, 10... second AND gate,
11...Third delay circuit, 12...Output relay.

Claims

[Scope of utility model registration request]

A surge voltage level detection circuit and a commercial voltage level detection circuit connected to a portion on the load side of the breaker connected to the bus line via a transformer, and a first delay circuit connected to the output end of the commercial voltage level detection circuit. , a first ant gate which receives the output of the first delay circuit and the output of the surge voltage level detection circuit, a surge signal holding circuit connected to the output terminal of the first AND gate, and a surge signal holding circuit connected to the output terminal of the first AND gate; a second delay circuit connected to the output terminal of the signal holding circuit; a second AND gate whose inputs are the output of the second delay circuit and the output of the first delay circuit; An abnormal voltage detection relay comprising a third delay circuit connected to the output end of the gate and an output relay connected to the output end of the third delay circuit.