JPS61176207A - Signal voltage detecting circuit - Google Patents

Abstract

PURPOSE:To shorten the working time by reflecting the potential difference between the 1st and 2nd nodes to the potential difference to be detected and charging or discharging the 1st and 2nd capacity charges via the 2nd MOS transistor. CONSTITUTION:The electric charge stored in the capacity of a lower potential level between the capacity C1 produced between an identification output node N1 and the earth and the capacity C2 produced between an identification output node N2 and the earth is discharged positively via MOS transistors (TR)Q1 and Q3 or Q2 and Q3 respectively. Thus the potential difference between both nodes N1 and N2 is increased. Here said discharge of the electric charge is carried out while both MOSTRs Q8 and Q9 are kept off. Therefore the electric charges stored in both capacities C1 and C2 formed between the nodes N1 and N2 and the earth respectively are never discharged through the TRs Q8 or Q9. This can decrease the working time during which the potential difference between both nodes N1 and N2 is increased and delivered as an identification output signal.

Description

[Detailed Description of the Invention] [Summary] Two voltages having a potential difference are applied to the first and second capacitors connected to the first and second identification output nodes, respectively. the first and second M
In a signal voltage detection circuit that obtains an identification output signal with an expanded potential difference between both identification output nodes by discharging (or charging) through an OS transistor, the first and second identification output nodes are connected to the first and second identification output nodes. MOS transistor and third and fourth MOS of different conductivity type
The first and second MOS transistors are connected to the source (or drain) of the transistor, and the gates of the third and fourth MOS transistors are used as the first and second input nodes, respectively, and the potential difference is detected by applying two input signals. Since a voltage having a potential difference is generated at the identification output node of the 1st node, there is no need for a clock to separate the input node and the identification output node. The operating time required to obtain an expanded identification output signal is reduced.

[Industrial application field]

The present invention relates to a signal voltage detection circuit in which an input node to which an input signal is applied and an identification output node to which an identification output signal is output are separated.

[Conventional technology]

Conventionally, a signal voltage detection circuit in which an input node and an identification output node are separated has been configured as shown in FIG. 4, for example. In the same figure, Ql-Ql is a MOS transistor, N
l-N6 are the first to sixth nodes, C1 to C5 are capacitances formed between the nodes and the ground, and 1 to 3 generate clock signals φ1 to φB for driving this signal voltage detection circuit. 4 is a positive power supply of voltage VDD.

It is assumed that the capacitors C1 and C2 and C4 and C5 have the same capacitance value. It is assumed that the clock signal takes two states: 1L level and 1H level. Since it is necessary to turn off the n-ch MO8 transistor, 'L level is assumed to be at ground potential. Furthermore, since the highest potential transmitted through the MOS transistor is the common node N6 potential VDD connected to the positive power supply 4, the threshold voltage of the n-ch MO8 transistor is set as vth (n-ah), and 1H
The level is defined as a constant potential that satisfies the following equation.

°H゛shield≧ ■DD+vth (n-8h) In the initial state, the clock signal φ1 of the signal voltage detection circuit shown in FIG. φ2 is in the lH level state, and φ8 is in the 1L level state, and the capacitances 01 to C5 formed between each node and the ground are photoelectrically connected to the power source 4 via the MOS transistors Ql, Q2, and Q4 to Q7, and are connected to the node N1. N2, N4 and N
5 is assumed to be set at equal potential.

First, the clock signal φ2 is set to 'L' level, and the power supply 4
are separated from the identification output nodes Nl and N2. Thereafter, an input signal whose potential difference is to be detected is applied to the input nodes N4 and N5 via a gate circuit or the like. Accordingly, the capacitances C4, C5 of the input nodes and the capacitances C1, C of the identification output nodes
2 charging and discharging is performed, and the identification output node Nl.

N2 respectively have input nodes N4. A potential equal to N5 appears.

For example, using the circuit of FIG. 4, - n-ahMO8
FIG. 5 shows an example of detecting information of a memory cell composed of a transistor and one capacitor. Here, TI, T
2 is an n-ch MO8 transistor, El is a memory cell capacity, E2 is a dummy cell capacity, E3. E4 is a capacitor formed between the bit line and ground, and W is a selection signal generating circuit that generates a selection signal φ7 for selecting a set of memory cells and dummy cells. φ7 takes 1L level when the memory cell is not selected. It is assumed that the memory cell capacitance has a capacitance value C8 and has two states: DD potential and ground potential. In addition, in order to detect the information of the memory cell, the capacitance value C
A dummy cell is prepared which has a dummy cell capacitance of B/2 and which takes only one state, that is, ground potential, and a gate of an n-ChMOS transistor.

Many memory cell capacities and one dummy cell capacity ii, n
-eh They are each connected to a common line called a bit line through a gate circuit made of MOS transistors, and the terminal end of the bit line is connected to the input node (N4 or N5) shown in Figure 4 or Figure 5. There is. The bit lines form a pair of bit lines connected to input nodes N4 and N5, respectively, and when one memory cell on the bit line connected to a certain input node is selected, it is connected to the remaining input nodes. It is assumed that a dummy cell is selected for the selected bit line. In the example of FIG. 5, the memory cell capacitance E1 on the bit line connected to the input node N4 side and the dummy cell capacitance E2 on the bit line connected to the input node N5 side are selected. Also, the capacitance E formed between the bit line and ground
3. It is assumed that both E4 have a capacitance value CBo. C
The capacitance value obtained by adding the capacitance value of the input node on one side and the capacitance value of the identification output node on the other side to BO is set as CB, and this is called the bit line capacitance.

It is assumed that the pair of bit lines are set to the initial potential VDD like the input node. - When a set of memory cells and dummy cells is selected, the selection signal φ7 becomes the lH level;
Paths from the memory cell capacitor and dummy cell capacitor to each bit line are opened.

When the memory cell capacitance has the VDD potential in the initial state, there is no movement of charge between the bit line capacitance and the memory cell capacitance, so the potential v4 of the input node remains at VDD. Furthermore, if the memory cell capacitor has a ground potential in the initial state, charge transfer occurs from the bit line capacitor to the memory cell capacitor. Input node N when charge transfer is completed
4's potential ■ 4 is expressed by the following formula % formula % On the other hand, the dummy cell capacitor has the ground potential in the initial state and has a capacitance value of K of the memory cell, so when the path from the dummy cell to the bit line is opened, the bit line A movement of charge from the dummy cell −\ occurs from the line, and the potential v5 of the input node N5 is given by the following equation.

B V5-'VnDc, , C,/2'1VDn Vsi
gThis approximation holds true when CB>CB, and takes approximately the intermediate value of the output potential of the memory cell. Memory cell information (VDD potential or ground potential) is identified by detecting the potential difference between the output potential of the memory cell read onto the bit line and the output potential of the dummy cell read onto the paired bit line. .

After a potential difference reflecting the potential difference between the input nodes N4 and N5 appears between the identification output nodes N1 and N2, the clock signal φ1 from the clock signal generation circuit 1 is set to 1L level and the input nodes N4. By disconnecting N5 from the identification output nodes Nl and N2, respectively, and then setting the clock signal φ8 from the clock signal generation circuit 3 to the IHl level, the charges in the capacitors C1 to C3 are transferred to the MOS transistors Q1 to Q3. is discharged through. The signal on the pit line connected to the memory cell and the signal on the bit line connected to the dummy cell are respectively input to the input node N4. When applied to N5, the potential of input node N4 is set to V4, and the identification output node N
If the potential of 1 is vl, the potential of input node N5 is 5, and the potential of identification output node N2 is v2, then, for example, V4=V1-v
DD, ■5=■z=VDD−V8ig.

Now, when the relationship of V[>V2 is established between the potentials Vl and V2 of the nodes Nl and N2, although slightly, the capacitance is larger than C1 due to the difference in the source-gate voltage of the MOS transistors Ql and Q2. Capacitor C2 is discharged faster and MOS
The transistor Q1 is turned off (υ), and the discharge of the capacitor C1 is stopped. With this, the potential of the output node N1 stops decreasing, but the potential of the output node N1 is n -ch MO
S Maintains a potential higher than the threshold voltage Vth (n-ah) of the transistor. Therefore, the MOS transistor Q2 continues to be in the on state, and all the charges stored in the capacitor C2 connected between the output node N2 and the ground are discharged.

As a result, the potential of the output node N2 drops to the ground potential, so the potential difference between the identification output nodes Nl and N2 is expanded. By the way, before the MOS transistor Q3 turns on, the input node N4. Since N5 is separated from the discrimination output nodes N1 and N2, it continues to maintain the potential of the initial input signal.

[Problem that the invention seeks to solve]

In the conventional signal voltage detection circuit, input node N4. N
After the input signal is applied to 5, a clock is required to turn off the transistor inserted between the input node and the identification output node in order to separate the input node N4゜N5 from the identification output node Nl, N2. Therefore, after the input signal is applied to the input nodes N4 and N5, the identification output node Nl
, N2 cannot perform the operations at high speed until the identification output signal is output.

[Failure to solve the problem]

In order to solve the problems of the prior art, the signal voltage detection circuit of the present invention connects the drain (or source) of the first MOS transistor and the gate of the second MOS transistor of the same conductivity type as the first transistor. A first capacitor is connected between the connected first node and ground, and a first capacitor is connected between the drain (or source) of the first MOS transistor and the source (or drain) of a third MOS transistor of a conductivity type different from that of the first MOS transistor. )
A second capacitor is connected between the ground and a second node connecting the gate of the first MOS transistor and the drain (or source) of the second MOS transistor, and the drain (or source) of the second MOS transistor is The fourth MOS transistor has a configuration in which the source (or drain) of a fourth MOS transistor of a conductivity type different from that of the second MOS transistor is connected to the second MOS transistor, and the first and second capacitances are charged or discharged. After setting the and second nodes to the same potential, two input signals whose potential difference is to be detected are applied to the gates of the third and fourth MOS transistors to convert the potential difference between the first and second nodes into the detected potential difference. , and then discharging or charging the charges of the first and second capacitors through the first and second MOS transistors, respectively, thereby creating an enlarged discrimination of the potential difference between the first node and the second node. It is designed to obtain an output signal.

[For production]

In the signal voltage detection circuit of the present invention, after charging and discharging the first capacitor C1 and the second capacitor C2 to bring the first node N1 and the second node N2 to the same potential,
Third MOS transistor Q8 and fourth MOS
When two input signals whose potential difference is to be detected are applied to the gate of the transistor Q9, the potential difference between the first node N1 and the second node N2 is reflected in the detected potential difference, and then the MO
When the S transistor Q3 is turned on and the charges in the first capacitor C1 and the second capacitor C2 are discharged or charged via the first MOS transistor Q1 and the second MOS transistor Q2, respectively, the first node N1 and the second node Node N of 2
2, an identification output signal with an expanded potential difference is obtained.

〔Example〕

FIG. 1 is a circuit diagram of an embodiment of the present invention, in which Q1 to Q3
．． QIO is an n-ch MO8 transistor Q4. Qr,
Q&.

Q9 is a p-ch MO8 transistor, N1 to N7 are nodes, 01 to C6 are capacitors formed between the nodes and ground, respectively, 2.3.5 is a clock signal generation circuit, φ2. φB.

φ5 is a clock signal, and 4' is a positive power supply. It is assumed that capacitors C1 and C2 and C4 and C5 have equal capacitance values.

Input node N4. The initial setting potential of N5 is VDD, p
The threshold voltage of the chMOS transistor is set to 1Vth (p-a
h) If l, the positive power supply 4' is VDD+1Vth
(p-8h) Suppose that it has a voltage of 1 or more. It is assumed that the clock signal has two states: 1L+ level and 1H level. 'L level Id,, In order to turn off the n-ch MO8 transistor and turn on the p-ah MOS transistor, the lowest ground potential is taken. Further, the 1H level is assumed to have the same potential as the highest potential power source 4' in order to turn off the p-ch MOs transistor and turn on the n-ch MOs transistor.

Also, in FIG. 2, the clock signal φ2. φ8. An example of the time chart of φ5, FIG. 3 shows input node N4. An example of potential waveforms of N5 and identification output nodes Nl and N2 is shown.

In the initial state, the input nodes N4 and N5 are set equal to the potential VDD via a gate circuit etc., and the identification output node Nl
, the capacitance C1°C2 formed between N2 and ground, respectively.
and common node N3. Capacitors C3 and C6 formed between N7 and ground are MOS transistors Q4,
C5.

Ql, through C2 and C8, Q9, is charged by the charge supplied from the power supply 4' and identified at the output node Nl.
, N2 are equally set to the potential of the power supply 4', and each clock signal φ2 . It is assumed that φB and φ5 are all 1L lebel.

First, the clock signal φ2 from the clock signal generation circuit 2
'&'H' level to identify the power supply 4' to the output node Nl
, disconnect from N2. After that, the clock signal φg from the clock signal generation circuit 5 is set to 'H' level and the MOS
Turn on the transistor QIQ and connect the common node N7.
Opens a path from to earth. p -Ch MO8 transistor Q8 has a source-gate voltage of p -ch
MOS transistor threshold voltage jvth (p-oh
) The charge stored in the capacitor C1 formed between the node N1 and the ground is M
OS transistor Q8. Discharged via QIO'i.

This discharge causes the potential of the identification output node N1 to drop to a potential higher than the potential VDD of the input node N4 by p p -ah MOS transistor threshold voltage IVth(p-eh) l, that is, VDD+1vth(,-8h)1. Then, it automatically stops and the MOS transistor Q8 is turned off. The same applies to identification output node N2 and MOS transistor Q9. In the initial state, the input nodes N4 and N5 are set to the same VDD potential, so the identification output nodes N1 and N5 are set to the same potential. N21ri etc. L < VDD
+1Vth(p-ah)l potential is automatically set.

Next, input node N4. A signal for detecting a potential difference is applied to N5 via a gate circuit or the like. For example, as used in the explanation of FIG. 4 above, the signal on the bit line connected to the memory cell is applied to the input node N4, and the signal on the bit line connected to the dummy cell is applied to the input node N5.

The potentials of input nodes N4 and N5 after the input signal is applied are assumed to be VDD + VDD-V and ig, respectively. input node N
As the potential of 5 decreased by ■, ig, j5, MOS
The source-gate voltage of transistor Q9 is p −a
h MOS transistor threshold voltage 1Vth (p-0
h) l Since the voltage exceeds the total Vsig, the MOS transistor Q9 is not turned on, and the charge of the capacitor C2 formed between the identification output node N2 and the ground is transferred to the MOS transistor Q9. QIO'i is discharged, and the potential of the identification output node N2 is lowered to a potential higher than the potential of the input node N5 by the threshold voltage of the p-ch MOS transistor IVth(p-8h)l. That is, when the potential decreases by the amount of ■, ig, it becomes the off state again. As a result, the potential difference v81g between the input nodes N4 and N5 becomes the identified output node Nl.
, reflected as the potential difference between N2 v8ig.

The potential of input nodes N4 and N5 is set to V4. V5, identification output node Nl.

N2 chime level 6vt, v2, p -ah MOS transistor threshold voltage IVth (p-8h) 1,
In an equilibrium state, the following equation holds true between ■+ and Vi, and between V5 and VZ.

vI:V” 1vth(p-ah)l, VZ=V
5+ 1vth(p-ah)1 Using the above example, V
4=VDD, VF-VnDVsigtearnote,v
l"'Vnn+l"th(p-ah)l, V
Z = vI)I)” I■th(p-ah)l V
sig, the potential v1 of the identification output node N1 is higher than the potential v2 of the identification output node N2 by an amount of sig.

There is an input node N4 between the identification output nodes Nl and N2. When the clock signal φs' of the clock signal generation circuit 3 is set to 'H' level with the potential difference Vsig between N5 sufficiently reflected to open a path from the common node N3 to the ground, the common node N3
drops to ground potential. At this time, the same type of n-
chMO8 transistor Q1. Q2 is the respective source-gate voltage, that is, the identification output node N2, Nl
When the potential of the n −Ch MOS transistor exceeds the threshold voltage of the transistor, the transistor is turned on. Here, since the purpose is to expand the potential difference between the identification output nodes, the input nodes N4 and MOS transistors in the initial state are set so that at least one of the MOS transistors Ql and Q2 is always on.
It is assumed that the potential VDD of N5 is selected.

In the above example, when the clock signal φ8 is not at the 1H1 level and the potential of the common node N3 drops to the ground potential, each identification output node N1. The potential of N2 is both n-c
Assume that the threshold voltage of the hMO8 transistor is exceeded.

Both n-ch MOS transistors Ql and Q2 are in the on state, and the charge stored in the capacitor C1 formed between the identification output node N1 and the ground is discharged via the MOS transistors Ql and Q3, and the electric charge is discharged through the identification output node N1 and the ground. The charge stored in the capacitor C2 formed between N2 and ground is also transferred to the MOS transistor Q2. Q3 is discharged through k. Clock signal φ8 is +H level9, capacitance C1, C
If the potential of the identification output node N1 is higher than the potential of the identification output node N2 by Vs i g at the time when the discharge of MOS transistor Q2 starts, the source-gate voltage of the MOS transistor Q2 is higher than the potential of the identification output node N2. Since the voltage between the source and gate of the MOS transistor Q1 is higher, the discharge of the capacitor C2 is faster than the discharge of the capacitor C1, and the potential 2 of the discrimination output node N2 is higher than the potential V1 of the discrimination output node N1. Declines faster.

When the potential of the identification output node N2 drops to the threshold voltage of the n-ch MO8 transistor, the MOS transistor Q1
turns off and stops discharging the capacitor c1, so
The potential drop at the identification output node N1 stops. Identification output node N
1 stops at a potential sufficiently higher than the threshold voltage Vth (n=.h) of the n-ah MOS transistor, the MOS transistor Q2 remains on.

Therefore, the charge in the capacitor C2 is finally completely discharged, and the potential at the identification output node N2 drops to the ground potential.

With the above operations, the expansion of the potential difference between the identification output nodes Nl and N2 is completed.

As shown in the embodiment of FIG.
S transistor Q8. , the conductive type of iQ9 is MOS
Transistor Q1. It has the characteristic that it is different from the conductive type of Q2. As already explained, the identification output node N
Capacitance c1 formed between 1 and ground, identification output node N2
By actively discharging the charge stored in the capacitor with a lower potential among the capacitor c2 formed between Transistor Q8. It has the characteristic that Q9 is carried out in the off state. Therefore, when the potential difference between the identification output nodes Nl and N2 increases, the MOS transistor QIC) is turned on.

Regardless of the off state, the identification output node Nu,
Each capacitance C1°C2 formed between N2 and ground
The charge stored in MOS transistor Q8 or Q9
It is not discharged through k.

In addition, in the case of a conventional signal voltage detection circuit in which the input node and the identification output node are separated, the input node N
4. Although the clock signal φ1 is required to separate the identification output nodes Nu, N2"t" from the input nodes N4. Since there is no need for a clock signal to separate N5 from the identification output nodes Nu and N2, after the input signal is applied to the input nodes N4 and N5, the potential difference increases as an identification output to the identification output nodes Nl and N2. It is possible to shorten the time until the identified identification output signal is output.

MOS transistor Q4 used in FIG. Q5 is ne
It may be an hMOS transistor or a p-Ch MOS transistor. When using an n-ah MOS transistor, the clock signal φ2 has the opposite polarity ('I■1g
1L+) = Must be used. Furthermore, in order to boost the potentials of the identification output nodes Nl and N2 up to the potential of the power supply 4' in the initial state, the 'H level is set to the potential of the power supply 4' and at least the threshold voltage IVth (n -ah) It is necessary to have a higher level Kumquat.

MOS transistor QIO has capacitances C1, C2, C3o
MOS transistor Q4 during charging. Q5. Q8. Q9
'(i) This is to reduce power consumption by preventing the formation of a DC path from the power supply to the ground via i.
? The nodes N4 and N1.・N5
This can be omitted by setting the potential relationship between and N2.

In addition, as a circuit configuration complementary to this circuit, MOS transistors Q4 to Q3, QIO'e p-ch MOS
) ray register, Qg, Q? A circuit configured with n-ch MO8 transistors can be considered. If the latter configuration is adopted, a negative power supply is used as the circuit configuration and reverse polarity is used for the clock signal, but the operating principle is the same as that of the present circuit.

As an application of this circuit, an array configuration may be considered as a sense amplifier for a multi-level logic memory. The MOS transistors QIQ and QB can be shared, and the capacitance CI formed between the identification output nodes Nl and N2 and the ground
, C2'i Since there are many methods for charging and discharging to initialize the equipotential, the basic components of the sense amplifier are:
MOS transistors Ql and Q2 of the same conductivity type and MOS transistors Q8 of a conductivity type different from Qi and Q2. There are a total of 4 pieces, Q9.

[Effect of revelation]

The circuit of the present invention is characterized in that the input node and the identification output node are separated, and that MOS transistors of different conductivity types are used, such as the MOS transistors Ql, Q2 and Q8, Q9 in the embodiment of FIG. So,
MOS transistor Q8. When Q9 is in the OFF state, the potential difference between the identification output nodes Nl and N2 is expanded, and since there is no need for a clock signal to separate the input node and the identification output node, the input signal is applied to the input signal node. This has the advantage that the operating time from when the identification output node is outputted until the identification output signal is outputted by expanding the potential difference at the identification output node can be shortened.

This circuit is considered to be very effective if applied to a circuit that wants to preserve the potential level of an input signal, such as a sense amplifier of a multi-level logic memory.

[Brief explanation of drawings]

1 is a diagram showing an embodiment of the signal voltage detection circuit of the present invention, FIG. 2 is a diagram illustrating the signal voltage detection circuit of FIG. 1, and FIG. 4 is a diagram showing an example of the configuration of a conventional signal voltage detection circuit. FIG. 5 is a diagram showing an example of application of the circuit of FIG. 4 to a memory sense circuit. Q1 to QIO, TI, TZ...MOS transistors N1 to N7...nodes C1 to C6, El to E4-...capacitances 1 to 3.5...clock signal generation circuit W...selection signal generation Circuit φl~φB, φS... Clock signal φ... Selection signal

Claims (1)

[Claims] Drain (or source) of the first MOS transistor
A first capacitor is connected between the ground and a first node connecting the gate of a second MOS transistor of the same conductivity type as the first MOS transistor.
The source (or drain) of a third MOS transistor of a conductivity type different from that of the first transistor is connected to the drain (or source) of the transistor, and the first M
A second capacitor is connected between a second node connecting the gate of the OS transistor and the drain (or source) of the second MOS transistor and the ground, and the second M
The second layer is connected to the drain (or source) of the OS transistor.
MOS transistor and a fourth MO of a different conductivity type.
The source (or drain) of the S transistor is connected, and two input signals whose potential difference is to be detected are applied to the gates of the third and fourth MOS transistors, respectively, and then the first and second MOS transistors are connected to each other. A signal voltage detection circuit characterized by discharging or charging charges of a first capacitor and a second capacitor, respectively, via a transistor.