JPS61175841A - Fast multi-bus construction and data transfer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to an apparatus and method for transferring data between a source and a plurality of receiving data processing devices; The invention relates to transferring data along a bus between a plurality of data processing devices and a plurality of transmission devices.

[Prior Art] In the field of computers, for example, there are multiple data processing devices such as computers, multiple printers,
It is quite common to transfer data and instructions to and from multiple memories, etc. via a system or data bus. Data processing devices typically include a processor that executes instructions stored at addresses in memory. The data to be processed is transferred via buses that interconnect data processing equipment with other digital hardware.
Transferred to and from the system by input/output devices. A common constraint on the speed of data transfer between data processing devices coupled to a bus is that a necessary event must occur within a specified NFC time before any data is exchanged between the data processing devices. All protocols that require that the sequence occur are 1-handshaking constraints.

Many methods have been devised for communicating data between data processing devices and peripheral devices such as storage devices and second processors and disk drives. One of these utilizes direct memory transfer, which allows large amounts of information to be moved between processing unit storage and peripheral devices. However, one drawback of conventional direct memory transfers is that each direct memory transfer requires some processor activity. Various commands and other signals are required to start and stop the transfer, and generation of these signals requires an interrupt to the processing unit. In data processing systems utilizing multiple processors, direct memory transfers between the memory of a first processor and the memory of a second processor require complex system protocols and addressing and I need. For example, a transfer of data along a common bus between a first processor A's local resource memory and a second processor B's a-local resource memory requires a second memory address along the bus. Second
Typically, an interrupt to the functionality of the second processor is required to initiate the transfer of the second processor. Also, due to the smooth overlapping of memory addresses between the memory of the fourth processor and the memory of the second processor, there is no difference in the contents of each message in the same numbered pigeonhole. It is clear that proper allocation and access of system resources is important for high data transfer efficiency in order to avoid this problem.

〔overview〕

The present invention provides a data processing system that includes a multiple bus structure to optimize the transfer of data and messages between multiple processors and to orderly allocate system resources to all devices coupled to each bus. It provides architecture.

The bus structure of the present invention comprises a general-purpose parallel bus and a specialized bus interconnected via a system interface that defines communication and data transfer protocols.

A multiple bus system architecture and an improved data transfer method for transferring data between multiple data processing devices are disclosed by the present invention. The bus structure of the present invention is designed to enable high-speed data and message exchange using a minimum number of "handshakes J'" prior to data transfer. Collectively, “Agent J”
including parallel and serial buses that interconnect the The serial bus protocol is controlled by a message controller coupled to each communication agent. The local bus is coupled to processing agents within the system to allow full access to the local memory and second processing resources without significantly impacting data traffic performed over the parallel bus. Direct access from other bus agents to resources coupled to the agent's local bus is also under the control of the message controller.

Assuming that a requesting bus agent wishes to begin data exchange along the parallel bus, it asserts a bus request (BREQ) signal and receives a digital signal corresponding to its unique agent arbitration number. The code is coupled to all system agents.
, D, (by lR) Send to bus. Since the bus request agent's arbitration number has a predetermined highest priority, all parallel paths can be used by the bus request agent. The requesting agent then asserts the address of the responding agent along with its own address on the address/data bus, as well as asserting the commands to the responding agent on the full command bus. When you are ready to continue exchanging data,
The request agent is request agent ready (REQ).
RDY) signal.

Similarly, when the responsive agent is ready to continue data transfer, it asserts the responsive agent ready (REPLY RDY) signal. Data on the address/data bus is considered valid only when both ready signals are asserted. REQ RDY
A data transfer operation is terminated by the request agent asserting an end of cycle (EOC) signal in conjunction with the signal.

Using the serial bus of the present invention, a bus agent wishing to send a message to another agent wraps the data message, verifies that the first row bus is not in use, and then sends the data message. send. The message receiver then responds by sending an acknowledgment (ACK) signal during the interframe period following the serial message. When a conflict of requests along the bus is detected, the serial bus agent begins a collision retransmission arbitration cycle. In the collision retransmission arbitration cycle, serial bus usage rights are allocated in an appropriate manner.

Next to the first processor of the Ruru agent on the local bus of the present invention is a high speed, high bandwidth parallel bus to local memory and processing resources. The data is the first
(also a second) processor and local memory resources according to the a-carbus protocol. All events on the local bus are clocked according to the first processor's internal clock signal. Assuming that the responding agent is unable to perform the required data operation (e.g., a bladder expulsion or a gulp) at the speed determined by the bus clock, then the responding agent a, Assert a wait signal that requires state and information content to remain unchanged for a clock cycle of t.Using the wait signal introduces a delay while the wait signal is asserted. allows the response agent to operate at a slower speed than the first processor.

[Metal practice]

Hereinafter, the present invention will be described in detail with reference to the drawings.

Overall System The following describes a multiple bus system architecture and improved data transfer method for transferring data between multiple data processing devices. In the following explanation, we will use specific numbers,
Although specific bytes, specific registers, specific addresses, specific times, specific signals, etc. are described, it will be apparent to those skilled in the art that the present invention may be practiced without being bound to those specific embodiments. . In order not to obscure the present invention unnecessarily, well-known circuits and devices are shown in block diagrams.

Referring first to FIG.
0 (or other [1,), such as printers, disk drives, etc., containing the same sides tctil and t. For purposes of this discussion, all data processing devices and all peripheral devices coupled to the bus structure of the present invention will be collectively referred to as "agents". , processing device f!25 ,2
6 and the global storage f130fd are interconnected to each other by a parallel bus 35 and a serial bus 37 for data transfer. Each processing unit 25.26 includes a first processor 40.41t-respectively. The first processors are coupled to parallel bus 35 and serial bus 3T via respective bus interface devices e44f. I10 to bus interface device 44 as described in more detail below.
Logic 46 and message control logic 50 are included. As shown, each processing device 1llc has access to local data processing resources such as memory 54 via a local bus 56.
The pigeonhole of the processing device 25 is connected to a memory 54 as well as a second processor 5T via a local bus 56.
is also combined. The processors 40 and 41U are coupled to their respective local resources such as a telememo IJ 54 via a local bus interface circuit 51.

As will be explained below, the bus architecture of the present invention allows for high speed serial transfer of messages between all agents coupled to the bus and high speed parallel transfer between data 1fx-agents. Additionally, the architecture of the present invention minimizes the need for scarce processor interrupts to transfer data between bus agents, including accessing data stored in local memory 54, which constitutes local resource resources for each processing unit. become.

Mayo, as will be explained later, parallel bus 35, serial bus 3T, and local bus 56 are used so that only minimal handshake operations are required to perform a data transfer.
A data transfer protocol has been defined for Although only two processing devices are shown coupled to the bus in FIG. 1, the structure of the present invention allows for multiple processing devices and multiple peripheral devices such as memory, disk drives, printers, etc. It will be appreciated that fIfts can be interconnected using one or all of the bus structures described herein.

Refer now to FIG. Parallel bus 35 includes address/data lines 60. In the embodiment described here, this address/data line 60i has a total of 32 address/data lines (plus 4 parity lines), and addresses and data are sent alternately to these address/data lines. Provided multiplexed.

Additionally, the agent arbitration line 621 allows each agent coupled to the parallel bus 35 to use a unique agent arbitration line 621 to acquire the bus. -Including, high priority extension line 64
(This will be discussed later) allows each agent to obtain the right to use a parallel bus independently of the overall arbitration protocol. The right to use the bus can be maintained by fully asserting the bus lock signal on bus lock line 69, thereby effectively locking out other agents from acquiring the bus. In addition, the bus request line (BIQ) is used to enable the agent to make all parallel bus control requests.
) 66 is provided, and a command bus 68 is provided to enable the processing units 25, 26 to communicate commands to other bus agents. An exception line 70 is provided to indicate an error condition;
A system control line T2 is provided for proper synchronization and control.

Supports parallel bus 35H1381 type bus cycles. These cycles include the arbitration cycle, the transfer cycle, and the objection cycle, which are initiated at the request of an agent such as processing unit 125. For purposes of this discussion, an arbitration cycle is defined as a parallel bus cycle in which an agent attempts to exclusively control parallel bus 35. An arbitration cycle allows only one requesting agent to queue at a time. F data transfer cycle to Talybus 35'?
! : Enable execution. When the arbitration cycle closes,
Only one agent (e.g., processing unit 26)
Data can be exchanged with other agents using a parallel bus. Notice that a system error occurs while processing the data transfer. When a system dispute error occurs, a dispute cycle is initiated. A total of three parallel bus cycles are used to determine which agent will have the next right to use the parallel bus.Then, other agents can perform arbitration cycles during the currently active transfer cycle. They overlap and perform yc together.

In the structure shown in FIG. 2, the message control logic 50#-1r, the backup memory 8
2, a message controller 80 coupled to the bus controller 8
4, a MW memory access (DMA) interface 86, and a FIFO pointer 88. The message control logic 5°0 performs all of the serial and parallel bus protocols and accesses to the respective buses, and the DMA between other agents coupled to the parallel (and serial) buses and the memory 54. 9 handles data transfer and money via interface 86 and local bus 56.

Assume now that processing unit 25 is required to fetch data stored in global storage 30 using parallel bus 35 .

The processing unit 25, via its bus controller 84, must first access the parallel bus 35 by initiating an arbitration cycle. Figures 5a and 5
As best shown in the flowchart shown in Figure b, a bus controller 84 within processing unit gL25 issues a bus request (BREQ).
) line 66 is currently asserted. Assuming that processing unit 25 does not have a high priority request, processing unit flc25n, BRE
We must wait until the Q line 66 line table 6 is no longer present before entering the resolution phase of the arbitration cycle. Assuming that BREQ line 66 line table 6 is not done, processing unit 25
makes an assertion on BIQ line 66 and at the same time provides a digital code corresponding to its unique agent arbitration number on agent arbitration line 62 (see Figures 4 and 5a). The appropriate logic within bus controller 84 of each agent coupled to parallel bus 35 has the highest predetermined priority (high priority line) within a certain number of clock cycles after an arbitration cycle is initiated. (assuming that no assertion has been made in 64) Select all arbitration numbers of the requesting agent. Assuming that another agent, for example, the processing device 26, makes a full parallel bus acquisition request, another agent, for example, issues an arbitration number tV with a higher priority, then the processing device IL2
5 is the end of cycle (EOC) indicating the end of data conversion.
) signal or for the bus to become idle.

Similarly, the previous bus user agent Kabuslok line 69
All agents connected to the parallel bus wait for the assertion of the parallel bus to be released (released) before accessing the parallel bus, and then assert their own arbitration number on the all-agent arbitration line 62. In order to do so, repeated attempts to access the entire bus must be made.

1g explained here! In an embodiment, the priority among the agents coupled to the parallel node (slot 35) is determined by their respective arbitration numbers. is,
A dedicated rTI pin line is coupled to each slot location. When powered on, a central service module (C8M) (not shown) coupled to the bus is provided with an agent slot identification number and a unique arbitration number.

Central service module (C8M)? -! , give the agent slot identification number t to the agent arbitration line 62,
Drive the T pin line corresponding to the agent whose slot identification number must be fully associated to a low level.

By driving the T-bin line low, the by-slot it number is held in a register within that agent. Similarly, GSM provides a unique arbitration number to the agent arbitration line 62 and drives the T-pin pin low level corresponding to the arbitration number to which all agents are to be associated. The arbitration number is held by driving its T pin line high. In the actual case explained here, the arbitration line 6
The 201 state indicates whether the numbers asserted on the remaining lines of the arbitration line correspond to agent slot numbers or arbitration numbers. This operation is repeated until all agents are assigned their respective slot identification numbers and arbitration numbers. Processing device 25
．． It will be obvious to those skilled in the art that the priority hierarchy of the woodcutter can be summed up among 26 agents.

Assuming that processing device 25 obtains the right to use the bus (by having F priority rights to its arbitration number), processing device @2
514, becoming a bus usage rights agent, BREQ
As long as the signal remains deasserted, the full right to use the bus is retained even after the transfer is completed. When the IOC signal is detected and the bus is currently idle, the address of the responding agent (destination address) and possibly further processing equipment [25], since the data contains the message, are Digital code t1 processing device 25 corresponding to the address (source address)
is applied to the address/data bus.

At the same time, the processing unit 25 is connected to the response agent (in the embodiment described herein, the global storage 30).
) gives the command bus a digital code corresponding to the specific function to be performed.

As shown in FIG. 4, when a requesting agent, such as the processing unit filt 25, provides various address codes and various command codes to the fully parallel bus 35, the command bus lines are effectively split so that the requesting agent and the response Agent 9
Allows for frequent acknowledgment signals to be sent. Depending on the provision of the address and command by the requesting agent (processing device 25 in the embodiment described here),
The so-called "request stage" ends. In the embodiment described here, the actual request phase lasts only one clock cycle.

At the end of the request phase, the lines making up the command bus 68
Reallocated as shown in the figure. In particular, five lines are assigned to the requesting agent and five lines are assigned to the responding agent to complete the next required handshake that completes the transfer of data between the agents. In particular, the request agent (processor 25 in the embodiment described herein) asserts a request agent ready (REQ RDY) signal on the appropriate command lines (LF) when the request agent
Indicates to the responding agent that it is ready and able to receive data on data bus 60.

Similarly, the response agent (wtt
In the m example, the Qgo global storage 30) sends the response agent ready (REPLY RDY) signal i-assertion (
(see FIG. 7) indicates to the requesting agent that the data on the address data bus 60 is valid and can be accepted. Therefore, the data on the address/data bus 60 is added to the parallel bus 35's functionality. To be considered valid requires assertion of the response agent ready signal and the request agent ready signal. Subsequent deassertion and reassertion of the response agent ready signal and the request agent ready signal allows additional data packets to be sent between the request agent and the response agent via parallel bus 35. (Figure 4).As shown,
Assuming no further data transmission is to occur, the request agent (processor 25 in the embodiment described herein) asserts the end of cycle (IOC) signal simultaneously with the assertion of the REQ RDY signal. The generation and transmission of the EOC signal informs other agents coupled to parallel bus 35 of the end of the current transfer cycle and informs them of the possibility of transfer of ownership of the bus. As best shown in Figure 5b, once valid data has been sampled, the response agent (in the wm example described herein) receives the response agent ready signal. During the non-doshake portion of it, which is normally shown, an error in data transfer (rA conference) can be raised to the 11 agent. Detected during that period by the request agent (in the embodiment described here, processing unit 25) and by one of the next data transfer cycles, the I
Assertion of the OC signal interrupts further data transfers and grants use of the bus to any waiting agent that successfully completes the arbitration cycle.

Although the above description describes data transfer from a response agent coupled to parallel bus 35 to a request agent, it is important to note that the request agent (e.g., processing unit ff12)
It will be appreciated that the data transfer from 6) to the responding agent (eg, processing unit 25) follows substantially the same protocol as shown in FIG. However, the parallel bus protocol of the present invention uses the REQ RDY signal and the RFJP signal before releasing data from the fully parallel bus.
This is because it simply requests assertion of the LYRDY signal. Therefore, the present invention allows the operating speeds of the requesting agent and the responding agent to be different using the same transport protocol.

The message control logic 50 of the present invention allows for minimal interruption of the first processor in the processing unit between agents coupled to the parallel bus 35 (and the serial bus, as will be explained). , can perform numerous message transfers and data transfers. For example, the first
data t-40 without having to interrupt the processor 40 of
data can be transferred to or from the dedicated resource memory 54. As explained later,
Next, a message controller 80 within the message control logic 50 determines whether a particular agent't-message transfer operation should be included in the message transfer operation. Check the message address society. If a particular message controller is to be addressed, that message controller must be of the type (
Type) field and perform any necessary interrupts requested to the first processor. Assuming no interrupts are required, Meri writes the following information in order to make the resource memory 54 accessible to external request agents:
Appropriate information is transferred to a direct memory access (DMA) interface 86.

Reference is now made to FIG. 8, which illustrates a flowchart of message transfer operations using message control logic 50. First, assume that the first processor 41 in the processing unit 26 desires to transfer data to a memory that is directly accessible by the processing unit 25 . A request agent (processor 26) issues a "buffer request" to its message controller 80. That buffer request consists of a destination byte corresponding to the address of the destination responding agent, a command "type" byte corresponding to the specific operation requested (in this case a data write operation), and a requesting agent as shown. an identification byte corresponding to the unique identification number of , so it includes). Those message bytes are sent along local internal bus 29 to the requesting agent's message system a-thick 50. The message controller 80 of that particular requesting agent (processing unit 26 in this example) stores the local address and length information in the buffer memory 82 or DMAa 6 of the message control logic 50. Message controller 80 further adds a byte to the request packet that includes a unique communication forwarding number (ID/S) k that identifies the current request. Message controller 80 receives buffer request packet i, FIGS. 4, 5a, 5b, 6, and Wc7.
The data is sent to the responding agent (in this case the UM management device 25) via the bus controller 84 and the parallel bus using the data transfer protocol described above with reference to all figures. The response agent's message control logic 50 passes the request directly to the first processor 40 of the response processing unit [25].

Whether or not it is possible to allocate an appropriate memory buffer of sufficient length tV as determined by the length byte "length - 1" to the first processor 40 of the processing unit f125 that is missing the message. decide. first processor 4
If 0 is added to the requested memory space, a buffer grant message is generated. In the buffer grant message, the type byte corresponds to a unique code that identifies the buffer grant. The address location of the local response agent is also the address location of the allocated buffer length (f
length - 2''), and the fingers are added. The buffer length indicates the amount of memory that the responding agent has allocated to the smile. It can be seen that the allocated memory size ta is different from the memory size requested by the requesting agent. After R, the byte indicating the contact transfer identification number (ID/S) i is repeated. Individually identify all specific buffer requests that fill that byte. The buffer grant data packet is then transferred along local internal bus 29 to response agent message controller 8o.

Its response agent message controller is the alpha-cal address of the buffer and the contact forwarding number ID/S.

and the contact transfer requester number (ID/R)! , in addition to the buffer request bagut that is being generated. Request agent's message control logic 5 for buffer permission message.
Transferred to o. The message control logic 5o then etches the data to be transferred to the responding agent by using a DMA interface 86 and sends the data to the bus controller 84, as shown in FIGS. 4, 5, and 6. and 7 can be sent to the full response agent according to the protocol described above with reference to FIG. Data transfer can consist of one or more data packets, as shown in FIG.

Upon completion of the desired data transfer, the respective message controllers 80 for both agents issue a general completion message 9 to the requesting agent and responding agent's respective messages indicating that the transfer has been completed. 1
processor. Therefore, messages and data can be transferred between agents coupled to the bus structure of the invention with a total minimum of interruption to the operation of the first processor, and the data transfer is controlled by the message control logic 5o. may include direct memory access for It should be noted that the message transfer operations described above and shown in FIG. 8 are also utilized by serial bus 31.

Serial Bus As previously explained with full reference to FIG. 1, each agent in the bus structure of the present invention can be coupled by a serial bus 37, as well as, or instead of, the parallel bus described above. While the structure and operation of the parallel bus 35 is inherently configured to provide high speed transfer of large amounts of data between agents coupled to the parallel bus, the serial bus of the present invention provides high speed and high efficiency transfer between agents. constituted as a king for the transmission of messages. In the wm example described here, serial bus 3T has "SDA" and r SDB
A two-wire serial link is provided with a line t'' designated by the symbol J. As shown in FIG. Serial bus 37't
- both lines of the serial bus 3T, including a serial message controller 100 for transmitting messages via
Coupled to bus status detector 110. This bus state detector produces three basic signal outputs. Serial bus 3
Carrier sense (
detection) signal? It is sent to the decoder 115 along with a signal indicating the received data. As will be explained in detail later, the path state detector 11
It is also determined whether a collision has occurred between messages sent via the 0H1 serial bus 3γ. A collision detection line 117 is coupled from bus status detector 110 to serial message control logic 124. This serial message control logic 124Ia, as will be explained later, controls the collision retransmission arbitration cycle of the present invention. In order to enable messages to be sent by serial bus 37, serial transmitter 1
28 is coupled to serial message control logic 124 and each serial line SDA, SDR.

As shown, serial bus 37? Messages to be sent serially via internal message control lines (not shown) that are directly connected to the circuitry of other message controllers 80 within message control logic 50 shown in FIG.
Serial message control logic 124 is first provided.

In the embodiment described herein, the data sent on line bus 37 is driven 180 degrees out of phase on lines SDA and SDR. Official KXi
Column message control logic 124i encodes all messages to be sent using the well-known Manchester encoding technique in the embodiment described herein.

Referring now to FIG. 10a, bus state detector 110 generates an encoded data signal, a collision detection signal, and a carrier sense signal from the received serial messages. Optionally, bus state detector 110 may include a pair of f
'DJ-latch 131 (next to synchronization). To these D-latches, the illustrated device is coupled in series to a pair of similar D-latches 132. A third pair of rDJ-latches 133 are coupled to the respective output terminals of latches 132 and detector logic circuit 136. 1s
The output terminals of D-latte 132 for SDA and SDB are connected to input terminals A2. It is coupled to B2. Similarly, the output terminal of D-latch 133 is coupled to input terminals AI, Bl of detector logic circuit 136. By detector logic circuit 136 or external clock! l1 generated clock signal (its frequency is typically 20MH
z) all latches are clocked simultaneously. D-latch 131, 132°133? I- allows the comparison of sequential data bits received simultaneously on lines SDA and SDB.

The bus status detector 110 of the present invention provides a simple method for detecting encoded data sent serially along the serial bus 3T and for detecting collisions of messages along the serial bus 37. can get. Figures 10a and 10
As shown in Figure b, message collisions along the serial data bus can be easily detected by looking at the output ty4 of the collision detection (CD) port of the bus state detector 110. All inputs Al, A2 . Bl,B
2 is low level (logic O), both lines SD
A and SDB t- are pulled low to indicate a collision since both data lines are normally driven 180 degrees out of phase by each serial transmitter 12B in their respective agents. . Therefore, all inputs AI, A2 . B
The only landing platform that B2 can get at low level is the pigeon coop that crashes along the bus. The reason for this is that the design requires that there be a logic 0 on the line SDB even though there is a logic 1 on the line SDA. Similarly, the idle period N of the serial bus
JD, carrier sense of bus status detector 110 (C8)
Detected by examining the boat's output. As shown, the bus idle period consists of both lines SDA, SDR
It is indicated by VC. that VC is in a high level state. The carrier sense (C8) port of bus status detector 110 is set to idle by generating a logic O (low) signal. show. Although the operation of bus state detector 110 has been described for particular logic states, it will be appreciated that other combinations of logic states may equally be used.

Reference is now made to Figure 11a. Synchronization (rayncJ) required to perform Manchester encoding on all messages sent along WL column Babasu 3 Preface 20G
and the following byte 210.

Part-time job 2101-! Fully configure the address of the destination agent (eg, processing device 26). In addition, a source agent address 220 that identifies all senders of messages is sent.
is included. The "Kind Type" byte 225 identifies the character of the message sent between agents. Examples of type directives include buffer requests, buffer grants, and the like.

Following the type buffer 225 is an identification (ID) byte 23 corresponding to the 2% identification number of the particular sending agent.
0, followed by a data field 235.

ii In order to carry out an error-free transmission along the column bus 3T, the message is sent to the well-known ? I14 Kucheck CRCC1
6-bit CCITT) code 240. Each message sent along serial bus 37 between agents is followed by a message-free period called the "interframe space" (IFS). In the embodiment described here: The messageless transmission period constitutes approximately 4 byte hours. All messages sent over the serial bus 37Ka are sent by the receiving agent using the acknowledgment message format shown in Figure 11b. As shown in the figure, the synchronization preface 20 is added to the a acknowledgment signal.
0 followed by a simple acknowledgment field 260. The acknowledgment field is optional and contains a unique digital code representing the message acknowledgment signal.

In the system described herein, the acknowledgment field is not used and is instead indicated by a synchronization preamble 200 and a bus idle period within the interframe space time that it reads. Assuming that at least one of the synchronization preface 200 and the idle period is not detected within the IFS time,
It is assumed that mistakes will be made.

Referring now to FIG. 12a, a series of logical operations performed by message control logic 50 to send a message on serial bus 3T will now be described. first,
Assume that processing unit 25 must send messages to total processing capacity 26 using serial bus 37. The processing device 25 detects the carrier sense (C8) of the bus state detector 110.
) It is first determined whether the serial bus 37 is currently in use by examining the output. In the wm example described herein, the absence of data being sent along serial bus 37 causes both lines SDA and SDR to remain high (see Figure 10a).

#Detector logic circuit 136 for SDA and SDR
The NAND operation indicates a low level condition indicating that no carrier signal is present on the serial bus 37. Serial bus 3
When the sound processor 125 determines that 7 is not in use, the serial message control logic 124 of the processor 25
encapsulates the message using the message format shown in FIG. 11a and sends the message to serial transmitter 128 for assertion on lines SDA, SDB. Is the processing device 25 that message? [Line bus 3
7, during the interframe space following the message using the Homare style shown in FIG. 11b, the processing device 1
26 - Embedded fi
Wait for 125i. Assuming an acknowledgment is received within the interframe space (IFS), this will end the serial message cycle.

If processing unit 25 does not receive an acknowledgment message during the entire interframe space, and bus status detector 110 indicates that serial bus 3
If all collisions along T are not detected, the processing device 25
After setting the flag bit in the message type byte 225 to identify the second transmission as a duplicated packet, the data transmission git repeats. 1, and if the bus status detector 110 detects a collision, the processing device 25
(and other agents coupled to serial bus 37) initiates a serial bus retransmission arbitration cycle (second b).
Figures 12c and 13).

The nature of when data is sent along a serial bus, i.e. the phase of the data is reversed along lines SDA and SDR, then 1') collision messages between no more than t transmitting stations. The sum makes lines SDA and SDRe low. When the occurrence of a collision is detected, all agents connected to the serial bus 3T perform a "jam cycle Jt".
Start Maru.

The jam cycle begins with the lines SDA and SDR.
? "to jam the serial bus by driving it low for a predetermined bit time."

The agent then idles for a predetermined period of time, checking the state of the bus to allow for collisions, and waits for an additional period (equal to IFS) to ensure that a valid jam cycle occurs. At the end of the jam cycle, each transmitting station starts counting predetermined time slots 0 through N at the same time (FIG. 13).

Each agent coupled to the serial bus 3T is allocated a unique time period during which it will retransmit its messages. As shown in FIG. 13, each time slot can be divided into a plurality of sub-time slots (numbered from 0 to M). A valley time slot has associated with it a particular agent that is coupled to a serial bus. In that case, all stations start the jam cycle again when counting up to a time slot with its associated sub-time slot 't-
In the figure, the counting of the sub-time slots within the time slot 211) begins completely. As a result, the transmission arbitration of the present invention can be efficiently used with a large number of agents coupled to serial bus 37. Although Figure 13 shows the use of shrine time slots, in the embodiment described here, only one level is used so that only one agent can be assigned a particular slot. Ru.

Assume now that a collision occurs between messages sent by agents A and B along serial bus 37. After all collisions are detected, the serial bus 37
All agents coupled to the jam cycle last one time slot (in the example fabric described here, each time slot has approximately 8 bit times)
Start counting from time slot number 0. In the example described here, agent A is assigned time slot number 0. Therefore, all agents) H, agent A, which are coupled to the serial bus 3T
The count of time slots stops until it has retransmitted all of its messages. Once agent A has retransmitted all of its messages using the protocol shown in FIG. 12, all agents will again continue counting time slots starting with time slot number one. (If a sub-time slot is assigned, as in the case of time slot number 2 shown in Figure 13, agents assigned to special sub-time slots may send their Metsu 7-di ligation. (After the pause, the sub-time slot is counted down similarly by all agents.) Therefore, the collision retransmission arbitration protocol of the present invention provides , it decides to allocate a predetermined time slot in which to send the message. This method of determination simply requires all transmitting agents to wait a randomly weighted amount of time before retransmitting, such that one agent eventually has full bus access. Traditional CS MA/ like J.
'CD protocol (U.S. Pat. No. 4,063,220) is fundamentally different.

The local bus 56 of the present invention provides high-speed, wide-area parallel access to local memory and processing resources for any WCL processor in the processing unit shown in FIG. Give a bus. local bus 5
All information transfers performed in step 6 require a request agent and a response agent. For example, a typical request agent may have a first processor 40 or a second processor 57 coupled to the local bus 56 for use as a resource of the first processor 40 in performing data operations. Out. Similarly, typically responsive agents along local bus 56 have memory resources 54 available to them. Therefore, by Law Man Lebus 56,
Multiple dedicated data processing resources are provided by an agent, the first processor 40, and the second processor 57 (if it is coupled to the local bus 56). It's explained here! ! In an embodiment, up to two request agents (processors)
It can be coupled to the local bus 56 at t-1 degrees.

As shown in FIG. 14, the local bus 56 includes an address line 300, a command line 310, and a data line 315.
and a plurality of control lines 32θ for maintaining control of the system according to the protocol for local bus 56. A bus request line (BUS REQ) 325 is coupled between the second request agent 57 and the first request agent 40 (in the case of processing unit [25]) via a local bus interface 58 (FIG. 1). . Similarly, a bus acknowledgment (BUS ACK) line 330 provides a signal between the second request agent 5T and the first request agent 40 to indicate acknowledgment of bus rights. A bus clock line 335 is coupled to the first request agent for synchronization with the processor's internal clock on local bus 56tll. Therefore, all bus events are defined in integer multiples of the bus clock period, and the start and end of each event, the next in its validity duration, are defined in relation to the edges of the bus clock signal. I have yk.

Arbitration for all bus transfer operations
'' cycle, the ``transfer cycle,'' and the ``objection'' cycle.9 At any given time, an arbitration cycle has one and only one requesting agent. (1st
or a second processor),
It is provided to allow data transfers to be initiated along local bus 56. In the case described here, when there is no request by the second requesting agent 57, the first requesting agent 40 is given control of the a-carbus 56. Therefore, assuming that the second request agent 57 is coupled to the local bus, the first request agent 40 only if the a-calpas is currently in use under the control of the second request agent. (The processing unit fl126 shown in FIG. 1 requires a second processor, Kanakura, on its local bus) to enter into an arbitration cycle (the processing unit shown in FIG. Please note that the

Reference is now made to FIG. 15, where the local bus arbitration cycle of the present invention is illustrated. If the second request agent 57 requests a request for z on the local bus 56, it asserts a BUS REQ signal on the full bus request line 325. P1 responds to the bus request of the second requesting agent by generating an acknowledgment (BUS ACK) signal on the bus acknowledge line 330, thereby making the bus right available to the second requesting agent 57. be transferred.

Second request agent 57 then sends appropriate address and command signals to memory 54, etc., via address lines 300 and command lines 310, respectively, to initiate the particular bus operation being requested. Give to local bus resource. request agent (processor)
Indication of address and command information by the ``request phase''
is called and lasts at least two clock cycles in the example described here. From t'L, the response agent (for example, memory resource 54),
Assert the appropriate data (in the case of an "r read" operation) on all data lines 315. That data is received by the second request agent 57 using the protocol described below. At 9 o'clock after the requested action by the responding agent is completed, the bus request line 325
The above assertion release deassertion) is deceived and passed to the first requesting agent 40 based on the F-BUS usage right.

Reference is now made to FIG. 16, which illustrates the unique use of the WAIT signal of the present invention. A WAIT signal is available to all ``response'' agents coupled to local bus 56 to request that they extend the entire response phase by introducing a delayed clock cycle. When pipeline processing is delayed (if the request phase of the current bus operation overlaps with the response phase of a previous bus operation), the assertion of a wait signal by the response agent performing the previous bus operation causes the current It is possible to extend the request phase of the bus operation. As shown in Figure 16,
First processor 40U asserts a request (using address line 300 and command 11310t) to a response agent coupled to local bus 56. The wait signal is asserted during the first clock cycle of the request phase of a bus operation, indicating that the responding agent in service on a previous bus operation receives address and command information during the current bus clock cycle. Inform the first requesting agent that it was unable to do so.Assume that the addressed responding agent requests additional time to access the requested data and provide that data to the t-local bus. The responding agent must assert the WAIT signal in the last clock cycle of the request phase. The requesting agent must continue asserting the WAIT signal until the appropriate number of access delay cycles have been introduced. The use of a wait signal to effectively provide a delay cycle on the local bus 56 may be useful if the first processor 40 is operating at a faster rate than the access time of the local memory IJ 17 source 54, for example. In general, the local bus 56 clocks at the same speed as the WJl processor.

%16 As shown in the figure, the request phase of the first request agent continues for two additional clock cycles when the waiting signal is asserted in the first clock cycle of the request phase. The standby signal effectively interjects the state of the bus line, but does not change the standard protocol of the local bus. Every request in is asserted for a minimum of two clock periods, but a responding agent can respond to the request at any time after receiving it.In other words, the requesting agent (
Even if the first processor (or the second processor) is still asserting the request, the responding agent can respond no more than one clock cycle after asserting the request ('4
cycle delay).

Assertion of the wait signal after the first clock cycle of the request phase (i.e. during its second clock cycle)
You will notice that it has no effect on that particular request phase, but only affects the response phase by lengthening its entire response phase by introducing a delay. For example, as shown in Figure 16,! The request phase of the second bus operation of the @1 request agent begins during the rare clock cycle in which the response phase of the previous bus operation should have finished. If the wait signal or the response phase of the previous bus operation were to be delayed by one cycle or more clock cycles, the request phase of the second bus operation would be correspondingly extended. . Asserting the wait signal during the first clock cycle of the response phase (the last clock cycle of the request phase) results in the response agent's response being delayed until the wait signal is deasserted by the response agent. Become. In the implementation described here, the current response agent has the right to assert a wait signal during the response phase of a given bus operation.

FIG. 17 illustrates the use of a wait signal by a response agent during the response phase and the objection cycle of the present invention. As shown, a first request agent asserts the entire request (address and command information) on address line 300 and command line 310. Since the wait signal is not asserted during the first clock cycle of the first 70 setter request, the request phase lasts for a minimum of two clock cycles. Upon request, the response agent asserts the wait signal fully during the first clock cycle of the response phase (the last clock cycle of the request phase), thereby performing the requested bus operation until the wait signal is deasserted. t1 informs all bus agents that it will not be performed and that all other functions are delayed accordingly. In the embodiment described herein, in order to obtain all the data read by the first requesting agent, the responding agent delays access by only one cycle while simultaneously providing its response on the full data line 315. The standby signal is deasserted. By deasserting the wait signal during the response phase, the data read to the local bus can be validly sampled. t1 informs the requesting agent that the write operation is terminated by t1.

As shown in Figure 17, during the first data transfer period of the response phase, any errors related to the issued request phase must be notified to the requesting agent (processor) by the response agent. . In other words, in the wm example described herein, any objections to the request are signaled during the first data transfer period of the response phase. If the wait signal is not asserted during the last clock cycle of a request phase, then an objection to the request phase is signaled during this last clock cycle. As shown in FIG. 17, objections to data are signaled during the lock cycle immediately after data is added to data bus 315 710 .

Figures 18 and 21 illustrate requests, data objections and "continue" objection protocols according to the invention. As shown in FIG. 14, the control line 320 indicates an address error (AERR) m and a data error! 11 (DERR
) contains lines. Those iI? i! The halo is coupled to all agents on the local path 56. As previously mentioned, an objection to the request phase expressed by the request agent 40, for example the first processor, is signaled to the request agent during the first data transfer period of the response phase. Similarly, objections to data applied to data line 315 are signaled during the clock cycle immediately following the application of the data. In the present invention,
The continuation error signal line (AE
RR)'! Notification will be made via r.

The AERR signal indicates that the data presented on the data bus has not been driven to the expected response agent and that a continuation error (i.e., a physical boundary error) has occurred. Continuation-9 occurs in the case of a block transfer where the responding agent lists its data address after each operation and the data address exceeds the responding agent's address range. Kotokameru.On that occasion, Tsui I&wA
9 has occurred, the responding agent informs the requesting agent by asserting on the AERR line during the period that the requested data is valid. therefore,
Otherwise, all continuation errors will be signaled at the same time as the lock cycle if the data is valid. A continuation error may also be signaled by a responding agent that does not fully support block transfers when a block transfer request is made. If the wait signal were asserted, this period would be delayed accordingly.

Next, with full reference to FIG. 19, the local bus 5
The performance that can be controlled by the 6-string "pipeline" will be explained. In the implementation described here, a first 7'' processor 40 drives its WILL request stage onto the address and command lines. If the first bus operation is not a block transfer, its second bus operation can be started immediately after the current request phase has finished. It is noted that the request phase of the second bus operation cannot begin until the expected clock cycle of the data transfer period.

Figure 20 shows a case where the first request agent 40 is accessing the local bus 56 and the second request agent 57 is requesting bus access t-. As shown, the second processor 57 asserts on the BUS REQ line during the request phase of the first request agent. The first requesting agent is required not to relinquish use of the local bus to the second requesting agent earlier than the clock cycle following the end of its response phase. As shown, the request phase of second request agent 57 initiates a clock cycle following which a BUS ACK is asserted by first request agent 40 .

In FIG. 20, when the response phase of request agent 57 of WJl is completed, second request agent 57 responds to I! r
The timing for addressing the first request agent (processor) 40 is also shown. Figure 1 shows the work, @2
The first requesting agent can yield all bus rights to the first requesting agent on the earliest clock cycle that follows the last clock cycle of its response phase. This is accomplished by the second request agent 57 deasserting the BUS REQ signal. In subsequent clock cycles, the first request agent 40 must deassert the BUS ACK signal and can begin the request phase of a new bus operation.

In the example illustrated in FIG. 20, the wait signal is fully asserted to response agent 40 during the first clock cycle of the response phase of the second request agent, thereby causing the data to be asserted during the second clock cycle. delay. Does the dechaining of the wait (WAIT) signal in the next cycle mean that the data "read" on the data line is valid and must be accepted by the requesting agent? Instruct. The wait signal is also used to introduce l clock cycles into the response phase of the second request agent's bus operation.

In addition to the LOCK control signal, local bus 56 provides a LOCK
Other controls like myt include. These control lines are signal mechanisms through which mutually exclusive bus operations can be performed. The LOCK signal is received by all responding agents end-driven to the requesting agent and coupled to local bus 56. L
The OCK signal can be asserted by a requesting agent that has the right to use the bus at any given time.

All responding agents that are involved in the bus operation for which the LOCK signal is asserted must lock non-local bus ports and that the LOCK signal is asserted. Holds the lock until it is deasserted. The first requesting agent and the second requesting agent do not relinquish ownership of their bus until mutually exclusive bus operations associated with the agent are terminated and the LOCK signal is deasserted. , the responsibility of the first and second request agents. 22nd
As shown in the figure, the effect of the LOCK signal is to allow a given bus agent to
It is possible to find mutually exclusive states that allow a set of bus operations to be performed for all responsive agents. More specifically, assuming local bus 56 has a response agent with multiple ports, mutually exclusive functions require locking out all non-local passports.

Above, refer to all Figures 15 to 22 and take notes +71 J Noose 5
Although we have described the access and reception of data by a first agent or a second agent, such as from a memory resource 54, a processor 54, or another data processing device such as a memory resource 54, It will be appreciated that the same data transfer protocol can be conveniently used for write operations.
Buffers can be allocated to introduce pauses on the bus state so that data can be received and checked for errors.

A request agent driving data during a write operation must extend driving data until the next clock cycle if the wait signal is asserted in that clock cycle (Figure 21).

In view of the foregoing description, it will be apparent to those skilled in the art that the present invention provides a unique system data bus architecture and data transfer protocol heretofore unknown. The parallel bus 35 of the present invention allows large amounts of data to be transferred at high speed between agents coupled to the bus. This may include, for example, data transfer between a processing device and a comprehensive storage device or other data processing device. Similarly, the serial bus 37 of the present invention allows for the efficient transfer of messages between agents within the bus structure, while eliminating the need for subsequent messages to pass over the parallel bus 35'. Furthermore, the local bus 56 is ji! A high-speed, wide-bandwidth parallel bus is configured to fully transfer data between one processor and multiple local resources without impacting the available bandwidth of other system buses.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the ninth data processing device implementing the present invention, Fig. 2 is a block diagram of the main components that make up the entire message control logic of the present invention, and Fig. 3 is a block diagram of the main components of the entire message control logic of the present invention. FIG. 4 is a schematic diagram showing the structure of the various sub-buses that make up the system; FIG. 4 is a timing diagram showing the parallel system bus protocol for data transfer between agents coupled to serial buses; FIG. Figure 5b shows a series of actions f performed by request agents coupled to parallel buses in order to receive requests along the bus from response agents η1.
A flowchart showing the control path in the request stage and response stage is shown in Figure 6. Figure 7 is a flowchart showing the sequence of logical operations performed by a response agent coupled to a parallel bus in order to transfer data to a requesting agent; Next message transfer requested along the bus? Figure 10a is a block diagram of the main components of the serial message controller for sending messages along the serial bus of the present invention, and Figure 10a is a block diagram of the bus status detection circuit of the serial message controller. Schematic diagram,
Fig. 10b is an explanatory diagram of the operation of the detector Mr embedded circuit, Fig. 11a
11b is a diagram illustrating the data-wrapping structure of the present invention for sending messages between agents coupled to the bus structure of the present invention; FIG. A diagram illustrating the acknowledgment message structure used in the bus, FIG. 12a, is a series of logical operations performed by a sending agent along the serial bus of the present invention. The flow diagram shown in FIG.
Figure 2c is a flowchart showing the sequence of logical operations performed simultaneously by agents along the serial bus to detect and receive messages; Figure 14 is a diagram showing the cycle of collision retransmission arbitration; Figure 14 is a schematic diagram of seven various sub-bus structures connected to the local bus of the present invention; Figure 15 is a diagram of the arbitration for accessing the local bus of the present invention; Figure 16 is a timing diagram showing the use of a local bus in standby mode, Figure 17 is a timing diagram showing successive local bus accesses in standby state and object state, and Figure 18 is a local bus block diagram. FIG. 19 is a timing diagram showing transfer and continuation v4 notification; FIG. 19 is a timing diagram showing bus arbitration, pipeline processing 2, and standby fees where the local bus functions under the control of the first request agent; FIG. 20 is a timing diagram showing the local bus Timing diagram illustrating local bus arbitration and waiting initially under the control of the first request agent, 21st
FIG. 22 is a timing diagram showing the local bus mutually exclusive operation under the control of the LOCK signal. 25.26--processing unit, 30--comprehensive memory am, 3s--parallel bus, 3T...0. series bus,
40, 41. --- Male processor, 44... Interface device, 46, Red... 110 logic, 5
0...Message control logic, 54...Memory, 56e--a-carbus, 57...Second processor, 60...Address/data line, 6211
...Agent arbitration line, 64.φ...High priority line,
66◆...bus request line, 68.false...command bus, [i
9**ea bus lock line, 70---different line, 72・
--- System control line, 80 --- Message controller, 82, φam buffer memo IJ, 84 @ --- Bus controller, 86 --- a direct memory access (DMAJ interface, 88 --- FIFO pointer, io
o---” serial message system (fl[,110...
・Bus status detector, 115 ・Φ...Decoder, 11T
...Fist/collision detection line, 124...Serial message control logic, 12B--Fist/serial transmitter, 131. 132.133 ・11-・D-Latch, 136 ・
・・Conflict detector logic circuit, 300 −φ・・Address line,
310・Pot・・Command line, 315・・・・Data line, 32
0... Control line, 325... Bus request line, 330
...Bus confirmation response line, 335...Bus clock line.

Claims (1)

[Scope of Claims] (1) A high-speed multiple bus structure for transferring data between a plurality of data processing devices (agents), wherein at least one of said agents has at least one bus along a local parallel bus. the first coupled to the responding agent
in a high-speed multiplex bus structure for transferring data between a plurality of data processing devices including processors, comprising: an address line coupled to the first processor and the response agent for transmitting address information; and command information. a command line coupled to the first processor and the response agent for sending data; a data line coupled to the first processor and the response agent for sending data; and deassertion of a wait signal. a wait signal generator coupled to the responding agent for generating the wait signal and transmitting the wait signal to agents coupled to the local bus so that subsequent bus operations are delayed until the local bus is activated; and transferring data between a plurality of data processing devices, characterized in that the data can be transferred along the local bus regardless of the difference in operating speed between the response agent and the first processor. High-speed multiplexed bus structure for (2) A bus structure according to claim 1, comprising:
such that all events on the local bus are clocked at an integer multiple of the operating speed of the first processor;
A bus structure wherein the local bus includes a clock line coupled to the first processor and the response agent. (3) In the bus structure according to claim 2,
Assertion of the wait signal during a first clock cycle of the first processor providing address and data information (request) causes the address and data information (request) to be asserted until the wait signal is deasserted. A multiple bus structure characterized by a request to continue the drive. (4) In the bus structure according to claim 3,
As a result of assertion of the wait signal after the first clock cycle of the first processor's request, the first
A multiple bus structure characterized in that all subsequent bus operations except for the termination of a processor's request are delayed. (5) In the bus structure according to claim 4,
A multiplexed bus structure, characterized in that deassertion of the wait signal by the response agent allows subsequent bus operations to occur starting during the clock cycle of the deassertion. (6) In the bus structure according to claim 5,
The first processor request is driven on the respective address line and the command line for a minimum of two clock cycles with no assertion of a wait signal during the first clock cycle of the request. multiplexed bus structure. (7) In the bus structure according to claim 5,
a second processor coupled to the local bus, the second processor coupled to the first processor and the second processor; a bus request signal generator for asserting a bus request line on the BU
Assertion of the S_REQ signal indicates a request by the second processor to access the local bus, and the first processor sends a bus acknowledgment signal (BUS ACK) to the second processor to the first processor. and a bus acknowledge signal generator for asserting on a bus acknowledge line coupled to the processor and the second processor, the assertion of the BUS ACK signal by the first processor to the second processor. A multiple bus structure characterized by indicating permission for bus access. (8) In the bus structure according to claim 7,
The assertion of the BUS REQ and BUS ACK signals and the absence of a wait signal enable the second processor to assert address information and command information (requests) on the address lines and the command lines, respectively. A multiple bus structure characterized by: (9) In the bus structure according to claim 8,
A multiple bus structure, characterized in that said response agent terminates bus operations after the first clock cycle of a request. 10. The bus structure of claim 9, wherein the response agent includes a dissent signal generator for providing a dissent signal on request during a first clock cycle during which the response agent is capable of responding to the request. A multiple bus structure characterized by: (11) The bus structure of claim 10, wherein the response agent is a continuation objection signal generator that generates a continuation objection signal in response to a request by a processor during a clock cycle in which valid data is to be applied to the data line. A bus structure comprising: (12) The bus structure according to claim 11, wherein the first processor and the second processor include a LOCK signal generator that provides a LOCK signal to at least one response agent; A multiplexed bus structure wherein assertion requires all responding agents to accept requests only from the requesting processor until the LOCK signal is deasserted. (13) A method for transferring data between a plurality of data processing devices (agents) by a bus structure, wherein at least one said agent is coupled to at least one responding agent along a local parallel bus. A method for transferring data by a bus structure between a plurality of data processing devices (agents) including processors of the local bus, comprising the steps of: generating and sending a digital code representing a command to the responding agent indicating a desired action on a command line coupled between the agents of the local bus; monitoring a standby line coupled between said agents for a standby signal; and placing a signal on a data line coupled between all agents of said local bus in accordance with the operation identified by said command signal. between a plurality of data processing devices (agents), wherein upon detection of the standby signal, subsequent bus operations are delayed until the standby signal is deasserted. Data transfer method using bus structure. (14) In the method according to claim 13,
generating a clock signal in synchronization with an internal clock operation of the first processor; providing the clock signal to a clock line coupled to each agent above. (15) In the method according to claim 14,
Asserting the wait signal during a first clock cycle of the first processor providing (requesting) address and data information may cause the first processor to assert the wait signal during a first clock cycle of providing (requesting) address and data information (requesting) until the wait signal is deasserted. ) requesting that the drive continue. (16) In the method according to claim 15,
Assertion of the wait signal after the first clock cycle of the first processor's request causes all subsequent bus operations except termination of the first processor's request to be delayed. Method. (17) In the method according to claim 16,
The method characterized in that deassertion of the wait signal by the response agent allows subsequent bus operations to occur starting during the clock cycle of the deassertion. (18) In the method according to claim 17,
The first processor request is driven on the respective address line and the command line for a minimum of two clock cycles with no assertion of a wait signal during the first clock cycle of the request. how to. (20) In the method according to claim 19,
The method of claim 1, wherein the response agent generates a dissent signal indicating an error in a request by a processor during a first clock cycle during which the response agent can respond to the request. (21) In the method according to claim 20,
a second processor coupled to the local bus, the second processor coupled to the first processor and the second processor; a bus request signal generator for asserting a bus request line on the BU
Assertion of the S_REQ signal indicates a request by the second processor to access the local bus, and the first processor sends a bus acknowledgment signal (BUS ACK) to the second processor to the first processor. and a bus acknowledge signal generator for asserting on a bus acknowledge line coupled to the processor and the second processor, the assertion of the BUS ACK signal by the first processor to the second processor. A method comprising: indicating permission for bus access. (22) In the method according to claim 21,
The assertion of the BUS REQ and BUS ACK signals and the absence of a wait signal enable the second processor to assert address information and command information (requests) on the address lines and the command lines, respectively. A method characterized by: (23) In the method according to claim 22,
A method comprising: generating a continuation objection signal in response to a request by a processor to the response agent during a clock cycle in which valid data is to be provided on the data line, indicating an error in an address. (24) In the method according to claim 23,
The processor is capable of generating a LOCK signal and its L
sending an OCK signal to at least one responding agent;
The method of claim 1, wherein the response agent only requests requests from the request processor until the LOCK signal is deasserted.