JPS61174819A - Subtracting circuit - Google Patents

Abstract

PURPOSE:To constitute a subtracting circuit suitable for a multilevel system by providing a floating switch, which is turned on when the result obtained by subtracting a subtrahend from a minuend is smaller than a prescribed value, and the first and the second nodes where (a radix)+ (the minuend)-(the subtrahend) is operated when the floating switch is turned on. CONSTITUTION:A minuend (x) distributed by a two-output current mirror 83 and a radix (r) led out through a floating switch 81 are supplied to the first node 89. Said minuend (x) and a subtrahend (y) distributed by a two-output current mirror 84 are supplied to the third node 85. The floating switch 81 is turned on to supply the radix (r) to the first node 89 when (x-y) is smaller than -0.5 at the second node 85. Consequently, (x+r) is operated at the node 89, and the result is supplied to the second node 90. Since the second drain of the current mirror 84 is connected to the node 90, (x+r-y) is operated at the node 90.

Description

DETAILED DESCRIPTION OF THE INVENTION SUMMARY OF THE INVENTION A subtraction circuit includes a counter cycling circuit and a full subtraction circuit. The counter cycling circuit outputs the result of subtracting the subtrahend y from the minuend X if the result (x-y) is positive, and if it is negative, it outputs the value (x -y+r). A full subtractor circuit is constructed by adding a circuit for a borrower output to a counter cycling circuit. These circuits operate in current mode.

Table of contents (1) Background of the invention (i, i) Technical field (1, 2) Prior art (2) Overview of the invention (2, 1) Purpose of the invention (2, 2) Structure and effects of the invention (3) Implementation Example explanation (3,1) Grandito switch and floating switch
Switch (3, 2) Floating threshold switching circuit (3, 3) Subtraction circuit (3, 3, 1) Counter cycling circuit (3, 3,
2) Full subtraction circuit (1) Background of the invention (1, 1) Technical field The present invention relates to a subtraction circuit that is a basic circuit in multi-value logic circuit systems, analog circuit systems, and the like.

(1, 2) Prior art] Research into multi+i logic and its arithmetic circuits has been active as a way to supplement or overcome some of the limitations of binary logic, which is the basis of many digital circuit systems including computers. It is being done. Binary logic is O and 1
, and the signals used in binary logic circuit systems take two levels corresponding to these two values, whereas multi-value logic handles three or more values, and the signals used in binary logic circuit systems take two levels corresponding to these two values. The signals used in the system take on three or more levels.

Multivalued logic (circuit system) is binary logic (circuit system)
It is said to have the following advantages compared to

1) It is possible to describe an uncertain state between 0 and 1 (for example, in the case of three values).

2) The wiring area and the number of bins on the IC board can be reduced, and the effective degree of integration can be increased. For example, in the case of 64 values, a wiring area of 1/6 of that of a binary logic circuit is sufficient.

3) Since the realization of a 10-value machine makes it possible to use the same logic as humans, the encoder and decoder required for a binary machine are no longer necessary.

By the way, apart from the perspective of binary and multi-value, from the perspective of circuit modes used in information processing systems,
Conventional circuit systems can be classified into two categories. One is a voltage mode circuit system, where information is represented by the magnitude and polarity of a signal voltage. Most of the conventional 261 digital circuits are of this voltage mode, and some voltage mode multi-value logic circuits have also been reported. The other is a current mode circuit system, where information is represented by the magnitude and direction of a signal current.

For example, the 121 circuit belongs to this category of current mode circuits and has features such as low supply voltage, small delay time/power product, high density integration, and suitability for VLSt. Applications of 12L circuits to multivalued logic systems have also been reported. For example, T,Tich Dao,
”Threshold12L and Its
Application to Binary
Symmetric Functions and H
IEEE
Journal of 5solid-3tate C1
rcuits.

vol, 5C-12, No. 5, 463-4
72 (October 1977): ■.

Tich Dao, Edward J, HacClus
key and Lewis K.

Ru5sell, ”Hultivalued
Integrated Injection Log
ic”, IEEE Trans, Comput,,
vol, C-26, No. 12. pp, 123
3-1241 (December 1977).

However, since the 121 circuit is constructed with bipolar transistors, it is inevitable that the multiple output current mirrors used in this circuit will produce errors.
This error is particularly significant when one or more collectors of this multi-output current mirror become saturated. Therefore, although there is no particular problem when applying the I21 circuit to a binary logic circuit system, it is extremely difficult to use the R1 circuit in a multi-value logic circuit system, especially a multi-value logic circuit system with 10 or more values.

Furthermore, the switching circuit used in the I21 circuit that has already been reported includes a grounded switch, which consumes power regardless of whether the switch is on or off. The disadvantage is that a diode is required to prevent backflow when connected.

(2) Summary of the Invention (2,1) Purpose of the Invention The present invention is intended to enable the realization of a multi-value logic circuit system with 10 or more values without error even when used for a multi-value logic circuit system. In addition, the present invention provides a subtraction circuit that is a basic circuit for realizing a multivalued logic circuit system or an analog circuit system that overcomes the drawbacks of a grounded switch by using a floating switch.

(2,2) Structure and Effect of the Invention The subtraction circuit includes a counter cycling circuit and a full subtraction circuit.

The first invention relates to a counter cycling circuit, which includes: a current source generating a current representing a radix r; a first node for adding a current representing the radix r to a current representing the minuend X; point, a floating switch consisting of a MOS FET connected between the current source and the first node;
a current comparison circuit that outputs a control signal to turn on the floating switch when a current representing a value (x-V) subtracted from the current value is smaller than a current representing a predetermined value;
It is characterized by comprising a second node for subtracting a current representing the subtraction y from the output current of the node.

The counter cycling circuit subtracts the subtrahend y from the subtractive X, and if the result (x-y) is positive, it outputs a current representing the subtraction result, and if it is negative, it adds the radix r to this subtraction result. It outputs the value (x-y+r),
The counter cycling circuit described above accomplishes this function. A current representing the result of this calculation is output from the second node.

The above predetermined value is O or a noise value of logical value 1 or less.
A value representing the margin is set.

In the latter case, a flow prevention diode is provided on the output side of the second node. As a result, a counter cycling circuit for multi-value logic and taking noise margin into consideration can be realized.

The second invention relates to a full subtraction circuit, and this full subtraction path is, briefly, realized by adding a circuit for borrowing and output to the above-mentioned counter cycling circuit.

That is, the full subtraction circuit includes a first current source that generates a current representing the radix r, a first node for adding the current representing the radix r to a current representing the minuend X, and the first current source and the first current source. A first floating switch consisting of a MOS FET connected between the node of a current comparison circuit that outputs a control signal to turn on the first floating switch;
a second node for subtracting the current representing the subtrahend y from the output current of the first node, subtracting the borrow input terminal from the current representing the minuend X or adding the borrow input terminal to the current representing the subtrahend y; a second current source generating a current representing a logical value y);
A MOS connected between the current source and the borrow output terminal, and turned on and off by the output control signal of the current comparator circuit.
The device is characterized in that it includes a second floating switch made of an FET.

Noise margin can also be considered in this full subtraction circuit.

The subtraction circuit according to the present invention has advantages such as low power consumption because it uses a floating switch1, and no need for a diode to prevent current flow in parallel connection. Furthermore, since it is constructed using MOS FETs, there are almost no errors, and it is possible to easily create even a multivalued logic circuit with 10 or more values. Furthermore, since the subtraction circuit according to the present invention operates in current mode,
Like the first, second, and third nodes described above, addition and subtraction can be achieved by simply connecting the lines through which the currents to be added and subtracted flow, resulting in a simple configuration. Since the floating switches are controlled by voltage signals, the output signal of the current comparator circuit can be used in the full subtraction circuit to control the two floating switches simultaneously, which also simplifies the circuit configuration.

It goes without saying that the subtraction circuit according to the present invention can be applied not only to multivalued logic operations but also to circuit systems for analog operations.

(3) Description of the embodiment (3,1) Grandito switch and floating switch
In circuit systems that operate in either switch current mode or voltage mode, the switches used in these circuit systems can be divided into two types depending on their connection form. They are the grandito switch and the floating switch. A grounded switch and a floating switch in a current mode circuit system are shown in FIGS. 1A and 1B, respectively.

In Fig. 1 (A>), a node (5) is provided on the line connecting the current source (2) of current J and the output terminal (4), and this node (5) connects to the ground (or power terminal). A switch (1G) is connected between the ground switch and the ground switch.

The switch (1G) is turned on and off by a control signal output from the control signal generation circuit (3). Switch (1G
) is on, the current J output from the current source (2) flows to ground through the switch (1G) as shown by the chain line, so the output current I at the output terminal (4).

becomes O. When the switch (1G) is turned off, the current m
Since the output current of (2) appears as it is at the output terminal (4), the output current I. becomes J.

In FIG. 1(B), the switch (1F) is a current source (
2) and the output terminal (4). This switch (1F) is called a floating switch because it is floating from ground. When the switch (1F) is on, the output current J of the current source (2) is this switch (1F).
The output current I appears at the output terminal (4) through F)
. becomes J. When the switch (1F) is turned off, the output current of the current source (2) is cut off by this switch (1F), so the output type IIo becomes O.

Compared to a circuit using a floating switch,
Circuits using grounded switches have two major drawbacks.

One drawback is that circuits containing grounded switches
Power is always consumed regardless of whether the switch is on or off. In FIG. 1(A), the switch (
1G) is on, the current J is this switch (1G)
When the current is off, the current J is the output current ■. bawl. On the other hand, in the circuit including the floating switch shown in FIG. 1(B), the switch (1F
) is on, the current J is the output current ■. However, when the switch (1F) is off, the current does not flow anywhere and no power is consumed.

Another disadvantage of circuits containing grounded switches is most apparent when such circuits are connected in parallel. In FIG. 2, the circuit shown in FIG.
(shown as (gl) and (g2) in FIG. 2) are connected in parallel, and their output terminals are connected at a node (6) and connected to an output terminal (7). One circuit (gl) is provided with a grandito switch (1G), and the other circuit (g2) is provided with a grandito switch (2G).

Switch (1G) of circuit (gl) is off, circuit (g2)
Consider the state where the switch (2G) is on. In this case, the output current 101 of the circuit (gl) is J, and the output current I of the circuit (g2). 2 is O. circuit (gl)
The output current I. 1 does not flow from the node (6) to the output terminal (7), and most of it is shown by the chain line I. As shown in , the switch (2G
) and flows to ground.

Therefore, the output current ■0 flowing out from the terminal (7) is
is not equal to <lo1+Io2). I.

In order to set = (Io1+Io2), add a chain line (
As shown in 8), it is necessary to provide a backflow prevention diode on the output side of each circuit (gl)l+2).

On the other hand, even if two circuits including floating switches as shown in Figure 1 (B) are connected in parallel, the above-mentioned problem will not occur, and there will be no backflow prevention on the output side. There is no need to connect a diode.

The circuit containing the floating switch is grounded.
A floating switch is employed in the present invention because it has the above-mentioned advantages over a circuit including a switch.

The floating switch can be constructed by a bipolar transistor or a MO8 FET (field effect transistor).

While a certain amount of power is required to control bipolar transistors on and off, MO
Controlling the SFET requires almost no power. From this point of view, it can be said that MOSFETs are better as floating switches.

(32) Floating Threshold Switching Circuit FIG. 3 shows an example of a floating threshold switching circuit. The floating switch (1F) is an N-channel MO8 type FET (N-M
The train is connected to the current source (2), the source is connected to the output terminal (4), and the substrate is grounded. Also this MO
A control voltage output from a control signal generation circuit (3) is applied to the gate of the SFET.

The control signal generation circuit (3) is a current comparison circuit, and is composed of a current mirror (11) made of a P-channel MO8 type FET (P-MOS FET) and a current mirror (12) made of an N-MOS FET. . The current mirror illustrated here consists of two MOS FETs,
It is equivalent to a current mirror configured by connecting the gates of these FETs to each other and connecting the gates to the drain of one FET. Of course, two FETs can be easily integrated and fabricated on one substrate with a common source and gate. Current mirror (1
1), when a discharge current (current in the flowing direction) 11 is applied to its gate by the input terminal (13), it functions to discharge the same value of current (■y) from the output side drain. When the current mirror (12) is given a sinking current (current in the flowing direction) I2 to its gate by the input terminal (14), it acts to sink the same value of current I2 to its output drain.

The source of the current mirror (11) is connected to the positive power supply VD, and the source of the current mirror (12) is grounded. The output side drains of these two current mirrors (11) and (12) are connected to each other by a node (15), and this node (15) is connected to the gate of the MOS FET constituting the floating switch (1F). ing.

Now, when the current 11 is larger than the current I2, the current mirror (11) is turned on, and the current mirror (12) sinks and generates an output current 12. Therefore, node (15)
The potential of is high level (approximately equal to power supply voltage +VD)
become. This high-level voltage is applied to the gate of the N-MOS FET constituting the floating switch (1F), so this FET is turned on. Therefore, the current if! The current J in (2) is the output current I. It flows out from the terminal (4).

Conversely, when the current I is smaller than the current I2, the current mirror (12) is turned on, and the current mirror (11) generates a source output current 1y).

Therefore, the potential at the node (15) becomes low level (mostly ○V), so the floating switch (1F
) remains off. Output current [. is O.

When the current I2 is fixed as a constant value and the current 1y) is varied, if the current ■1 exceeds the current ■2, the floating switch (1F) turns on and the output current I becomes J
The value is . When the current 11 becomes smaller than the current 12, the floating switch (1F) is turned off and the output current I. becomes O. In the circuit shown in Fig. 3, the output current I0 changes to J depending on the value of the current ■1 with the current ■2 as the threshold value.
It is converted into two levels: and O. Furthermore, a floating switch is used in the circuit of FIG. Therefore,
This type of circuit is called a “flooding threshold”.
It is called a switching circuit.

If it is considered that the current (2) (y) is fixed as a constant value and the current I2 is varied, the current (2)1 becomes the threshold value.

Furthermore, the circuit of FIG. 3 has an interesting feature. That is, the signal for controlling the floating switch (1F) on and off is a "voltage" signal (voltage mode) (potential of the node (15)). On the other hand, the signal switched by the floating switch (1F) (signal flowing through the floating switch) is a "current"
signal (current mode). A circuit that operates in a combination of voltage mode and current mode in this manner will be referred to as a "hybrid mode circuit." Such a hybrid mode circuit can have a circuit that operates in voltage mode as a control circuit, and can also connect a circuit that operates in current mode to these as a controlled circuit and a control circuit. It is extremely versatile and has a wide range of applications.

Incidentally, the signals compared by the control signal generation circuit (current comparison circuit) (3) are in current mode. Therefore, this third
It can be said that the circuit shown in the figure performs current/voltage/current mode conversion.

FIG. 4 shows a model of a floating threshold switching circuit.

FIG. 4(A) shows the current mirror (11) and its input terminal (13) in FIG. 3 as a current source (21), and the current mirror (12) and its input terminal (14) as a current source (21).
2) respectively. Current comparison circuit (
3) can generally be characterized as two non-linear current sources connected in series and driven by a constant supply voltage.

FIG. 4(B) shows a circuit in which a P-MOS FET is used as a floating switch (1F). This FET has its source connected to a current source (2) and its drain connected to an output terminal (4).

Further, the substrate of this FET is connected to the power supply voltage +vo. In this circuit, when the potential at the node (15) becomes low level at 11×2, the FET
(Floating switch (IF)) is turned on,
Output current■. J is obtained as Furthermore, when the potential at the node (15) becomes high level with 11>12, the FET
turns off and the output current ■.

becomes O.

Based on the floating threshold switching circuit described above, the subtraction circuit of the present invention will now be described.

(3,3) Subtraction circuit The subtraction circuit includes counter cycling (Counter cycling).
r cycling) circuit and full subtraction circuit (full
5ubtracter).

(3, 3, 1) Counter Cycling Circuit The operation of the counter cycling circuit in r-value logic with r as the radix is expressed by the following equation.

f (x, y) three (x-y) Hod r ・(1)
...(1-1) In equation (1), ! 4od is an abbreviation for modulo in modulo algebra. Also, the first (
The value 0.5 in equation 1-1) is the noise margin taken into consideration in the multivalued logic circuit. This can be any value less than 1 if noise margin is taken into account.

An example of a counter cycling circuit that executes the calculation of equation (1-1) is shown by a solid line in FIG.

The two inputs (variables) x and y are input terminals (86X) (86
y) are given as sink input currents representing these values, respectively. The current representing the input X is a current mirror (9
9), its direction is reversed and a two-output current mirror (
or current distribution circuit) (83). Therefore, the two output drains of the two-output current mirror (83) each output a source current having a value of X. Apply a source input current to the input terminal (86x), and output the input current to this terminal (86x).
The current mirror (99) can also be omitted by connecting the current mirror (86x) directly to the input side of the two-output current mirror (83). The N current representing the input y is a two-output current mirror (
84), and the two output drains of this current mirror (84) output sink currents of the value of y, respectively.

One output drain of the two-output current mirror (83) and two
It is mutually connected to one output drain of the output current mirror (84) at a node (85).

A current source (80) is connected to this node (85) which provides a sinking input current with a value of 0.5. Furthermore, this node (85) is a floating switch (81)
(corresponding to the floating switch (1F) in FIG. 4(B)). 2 output current mirror (
83), a part of the two-output current mirror (84), the node (85), and the current source (80) correspond to the above-mentioned control signal generation circuit (3), and the node (85) corresponds to the node (15)
corresponds to Therefore, when (x-y)<-o, s, the potential at the node (85) becomes low level and the floating switch (81) is turned on. And -
〇, When 5≦(x-y), the potential of the node (85) becomes high level, so the floating switch (81)
) is turned off.

On the other hand, the other output drain of the two-output current mirror (83) is connected to the output terminal (88) via a diode (87). The diode (87) is connected in a forward direction to the current discharged from this output drain. Also, between this output drain and the diode (87), a diode (87) is connected from the drain side.
Nodes (89) and (90) are provided in this order. The above-mentioned floating switch (81) is connected between the current source (82) providing a sinking input current of value r and the node (89). Further, the other output drain of the two-output current mirror (84) is connected to the node (90).

(When x-1<-0,5, the floating switch (81) is on, so the current of the value r flows to the node (8
9). Therefore, at the node (89) (
x+r> is performed, and a current representing the addition result flows from node (89) to node (90). Since a current with a value of y flows out from the node (90), a subtraction of [(x+r)-V) is performed at the node (90),
A current representing the result of this subtraction appears at the output terminal (88) via the diode (87). The output current is (x-y+r
) represents the value of

10. When 5≦x−y, a floating switch (
81) is turned off. Therefore, the current flowing from node (89) to (90) is X.

If -035≦(x-y)<O, that is, (
x+0.5)≧y and x<y, the node (90
) The direction of the current representing the subtraction result (xy) is opposite to the diode (87). This current is therefore blocked by the diode (87) and
The output current of the terminal (88) becomes O.

If 0≦(x-y), that is, X≧y, the current representing the subtraction result (x-y) at the node (90) passes through the diode (87) and is discharged to the output terminal (88) as an output current. appears as.

As described above, the calculation expressed by equation (1-1) is performed by the circuit shown by the solid line in FIG.

The input/output characteristics of such a counter cycling circuit in the case of r=4 is shown in FIG. however,
Excluding (-B, o) on the horizontal axis and (, B, o) on the vertical axis.

In this figure, it is desirable that the graph fall at the position of (x-V)=3.5 as indicated by the chain line, but there is no problem in practice.

Current? By changing the output current value (especially the value of r) of 1i (82), this counter cycling circuit can be applied to multi-value logic of any radix r. The noise margin (
By arbitrarily changing the values of 0 and 5), a desired noise margin can be set. If the noise margin is brought as close as possible to O, the circuit shown by the solid line in FIG. 5 will become a counter cycling circuit for analog calculation.

(3, 3, 2) Full subtraction circuit The operation of the full subtraction circuit in r-value logic with r as the radix is expressed as follows.

Difference: f (x, y, B ・) in 3 (x-y-8,') Hodr in = [X - (V + B + n)] Nod r... (
2-1) Here, the difference (o; rrrence) indicates the value of the technique in the subtraction result. X is the minuend and (y+8.) is the subtrahend. Bin represents the borrow-in (rental) for the lower digit.

Equation (2-1) specifically represents the content n obtained by replacing (x-y) with (x-y-8,) in equation (1-1).

...(2-2) What is borrow-out?1
A value or signal that represents a debt to the higher digit and is subtracted from the higher digit.

A full subtraction circuit is easily obtained by making some modifications to the counter cycling circuit described above. The entire circuit of FIG. 5, including the circuit indicated by the broken line, is a full subtraction circuit.

An input terminal (88B) is provided for the borrow-powered Bio, and this terminal (86B) is connected to the input side of the current mirror (84) at a node (95). Input terminal (86B
) is given a sink input current of the value B,o (1 or O). Therefore, the input current of the two-output current mirror (84) is (y+J,). In the counter cycling circuit described above, the subtrahend y is (y + B
in), so the number (2-1
) can be easily understood. A current representing the difference is output from the output terminal (88).

Borrow output B. 8. For this purpose, a current source (92) that provides a sinking input current with a value of 1 and an output terminal (94) of a borrow output Bout are provided, and a floating switch (91) (P-MOSFET) is connected between them. has been done. A control voltage of the same potential as the node (85) is applied to the gate of this floating switch (91).
3).

It should also be noted that since the floating switches are controlled by voltage mode signals as mentioned above, it is possible to share the control signals for the two floating switches (81) and (91) in this way. It is.

(x-'l/-B, o) <-0,5 i.e. (x-B
; n + O-5) <y, the gate of the floating switch (91) is at low level;
This switch (91) is turned on. Therefore, the borrow output B since the current of the current source (92) appears at the output terminal (94) through the switch (91). ut becomes 1. , (x −y −B in)≧−0,5, that is, (
x-B, o+ 0.5) ≧y, floating
Since the gate of switch (91) becomes high level,
The switch (91) is turned off and borrow output B is generated. , t becomes O.

Input/difference output characteristics and input/output characteristics of full subtraction circuit (r-4)
Borrow output characteristics are shown in FIGS. 6 and 7.

Note that the borrow human power Bio may be subtracted from the minuend X, as shown by the input terminal (86Ba) and the node (95a). However, in this circuit, X=0, B 1y
It cannot be used when L=1.

[Brief explanation of the drawing]

FIG. 1 shows the types of switches; FIG. 1(A) shows a grounded switch, and FIG. 1(B) shows a floating switch. FIG. 2 is for explaining the drawbacks of the grounded switch, and shows a state in which two circuits including grounded switches are connected in parallel. FIG. 3 shows an example of a floating threshold switching circuit, and FIG. 4 shows models of two types of floating threshold switching circuits. FIG. 5 is a circuit diagram showing an example of a subtraction circuit including a counter cycling circuit and a full subtraction circuit; FIGS.
The figure is a graph showing the input/output characteristics of these circuits. (1F)...Floating switch, (3)...
・Current comparison circuit, (80) (82) (92)...
Current source, (81) (91)... Floating switch consisting of MOS FET, (83) (84) (
99)...Current mirror, (85) (89) (90)
(93) (95)...Node point, (86X) (86V)
...input terminal, (86B) ...borrow input terminal, (
87)...Diode, (88)...Difference output terminal,
(94)...Borrow output terminal. Above Figure 1 (A) CB) Book 38 Figure 1 Revised - 1; No. 2 Invention title subtraction circuit 3 Relationship with the case of the person making the amendment Patent applicant address 10 Hanazono Tsuchido-cho, Ukyo-ku, Kyoto City Name (2)
94) Tateishi Electric Co., Ltd. 4 Agent address: 4th floor, Fuji Annex Building, 1-12-6 Nishi-Shinbashi, Minato-ku, Tokyo 105 Telephone: (03) 50g-02956 Subject of the amendment Page 7, line 4 From r T, Tlch in the 12th line
Dao, ... (December 1977). ” should be corrected as follows. “Threshold I2L and its application to binary symmetric functions and multivalued logic”, IEE Journal of Solid-State Circuits, Vol. 12, No. 5 No. 463
Page-472 (October 1977) (T, T
lch Dao, “Threshold I 2L
andIts Application to Bi
nary S) +++ metric Punc-tio
ns and Multivalued Logic
”, IEEE Journalof'5olid
-8tate C1rcults, vol, 5c-1
2, No, 5°pp, 483-472 (Octobe
r 1977) ): Te ("Te4-/Chi Dao, Nidward Jiei Mackulski, and Lewis ψ Kay Russell, "Multi-level integration injection reference logic", Ieeeeeeiφtrans compts 2. Volume 26, No. 12. Pages 1233-1241 (December 1977) (T
, Tich Dao. Edward J, MacCluskey a
nd Levls K, Ru5sell. ”Multlvalued Integrated
Injection Logic'. IEEE Trans, CoIflput,...
vol, c-28, No, 12゜pp, 1233-1
241 (Deeeea+ber 1977)), J et al.
Up

Claims (4)

[Claims] (1) A current source that generates a current representing the radix r, the minuend x
a first node for adding a current representing the radix r to a current representing the current, a floating switch consisting of a MOSFET connected between the current source and the first node, and a subtractor y subtracted from the minuend x. a current comparator circuit that outputs a control signal that turns on the floating switch when the current representing the value (x-y) is smaller than the current representing the predetermined value; and a current comparison circuit that represents the subtractor y from the output current of the first node A subtraction circuit comprising a second node for subtracting current. (2) Claim No. (1), wherein the predetermined value is 0.
Subtraction circuit described in section. (3) Claim (1), wherein the predetermined value is a value representing a noise margin with a logical value of 1 or less, and a flow prevention diode is provided on the output side of the second node. Described subtraction circuit. (4) a first current source that generates a current representing the radix r; a first node for adding the current representing the radix r to the current representing the minuend x; the first current source and the first node; a first floating switch consisting of a MOSFET connected between the first floating switch and the second floating switch; a current comparison circuit that outputs a control signal to turn on the switch; a second node for subtracting a current representing the subtrahend y from the output current of the first node; and subtracting the borrow input current from the current representing the minuend x. a third node for adding a borrow input current to a current representing a subtractive value y; a second current source for generating a current representing a logic value 1; and a connection between the second current source and a borrow output terminal; a second floating switch made of a MOSFET connected between the two and turned on and off by an output control signal of the current comparison circuit;