JPS61173541A - Voice and data receiving device - Google Patents

Abstract

PURPOSE:To receive voice data as well as digital data by using a first-in first-on memory and storing analog data which is converted into digital data at a frequency of 500kHz, and outputting this stored data at a frequency of 7,680Hz. CONSTITUTION:The voice data 44 stored in the first-in first-out (FIFO) memory 13 at a frequency of 500kHz is read out to a D/A converter 14 successively with a clock signal of 7,680Hz from an output clock generating circuit 16. The voice data inputted to the D/A converter 14 consists of eight bits as well as when it is inputted to the FIFO memory 13 and the D/A converter 14 converts it into analog data of 130mus with the same clock signal of 7,680Hz. At this time, a voice outputted from a speaker SP is controlled through 6,1440-bit digital capacity and data inputted to a voice and data receiving device from a coaxial cable 23 on time-division basis with a clock of 500kHz is reproduced securely, so that the accurate voice is outputted from the speaker SP.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a voice and data receiving device, and particularly to a device that selects either voice data or digital data by switching a switch and receives it in one time division. It is.

[Conventional technology]

The present applicant filed a patent application for a receiving device in time division synchronous communication in Patent Application No. 151712 filed in 1982, but the device uses the NTSC synchronization signal and the NTSC
It operates as a receiving device in time-division synchronization communication in which frame synchronization is performed using a vertical synchronization signal included in the synchronization signal, and slot synchronization is performed using a horizontal synchronization signal included in the NTSC synchronization signal to allocate time slots.

In addition, the device is equipped with an internal terminal number setting circuit, a terminal self-address setting circuit, a circuit for initializing time division, selecting and subtracting the address of the other transmitter or the number of terminals, and a circuit for paralleling serial information signals. It includes a circuit for converting into an information signal and inputting it, a circuit for determining the maximum number of slots, etc., and initializes time division using the above-mentioned vertical synchronization signal. Next, the above-mentioned horizontal synchronization signal is used to repeat the countdown of the address of the other transmitter, and a parallel information signal is input at the timing of the borrow signal generation, and the subsequent horizontal synchronization signal is used to repeat the countdown of the number of terminals, and the parallel information signal is input at the timing of the borrow generation. input and select the number of terminals, and then input parallel information signals and select the number of terminals every time a borrow occurs, repeatedly within the set maximum number of slots to perform time-division synchronous communication in frame units. It is characterized by:

The interconnection system between the terminal and the processing device is shown in FIG. 2, in which 51 is a coaxial cable, 52 is a synchronizing signal generator, 53 is a terminator, 54 is a tap device, and 55 is a data line.

56 is an inserter, 57 is a terminal, and 58 is a processing device.

[Problem that the invention seeks to solve]

In the above-mentioned so-called local network system, a system that receives audio data in a time-division manner has not yet been put into practical use, and there is also a current demand for a system that receives audio data and digital data in a time-division manner by switching between them. .

[Means to solve the problem]

The present invention provides audio data that solves the above-mentioned problems.

The present invention provides a device for receiving digital data in a time-division manner, the means of which includes a circuit for storing analog data converted into digital data using a first-in-first-out memory in a digital data time-division multiplex reception device;
This is achieved by an audio/data receiving device characterized by having a circuit that samples audio data on a coaxial cable at a frequency of 500 KHz, and a circuit that outputs data sampled at a frequency of 500 kHz at a frequency of 7680 Hz.

[For production]

In the above-mentioned apparatus, first-in, first-out
.

First-out (hereinafter referred to as FIFO) memory is used to convert analog data into digital data and
It is temporarily stored at a frequency of KHz, and this stored data is
It outputs at a frequency of 680Hz and has the effect of reproducing accurate audio data.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit block diagram of a voice/data receiving apparatus according to the present invention. In the figure, numeral 10 is an audio data receiving section, and numeral 11 provided in the audio data receiving section 10 is an operational amplifier (OP amplifier), which amplifies the signal input from the coaxial cable 23 and converts it into a voltage that is passed through internal processing. Convert. 12
is an analog-to-digital converter (hereinafter referred to as A/D converter), which converts the analog signal output from the operational amplifier 11 into a digital signal. 13 is a FIFO memory that temporarily stores digital data output from the A/D converter 12 described above.

This FIFO memory 13 has two
It is driven by a clock input from two terminals,
The data written by the “IN” clock is “OU”.
14 is a digital-to-analog converter (
(hereinafter referred to as a D/A converter), the digital data read from the FIFO memory 13 is sent to the speaker SP.
This is a converter for transmitting to. 15 is an operational amplifier, which outputs the output signal of the D/A converter 14 to the speaker SP.
This is to amplify the signal to a level suitable for the drive level.

16 is an output clock generator, which oscillates a 7680Hz clock. 17 is a reception clock generator;
Oscillates a 500KHz clock. 18 is an inserter, which is a device that mainly converts the line signal level into a data signal level during digital data transfer.
It has the function of converting the synchronization signal on the line to the signal level for internal processing. The latter function is used when handling audio data. A control unit 19 performs line connection, disconnection, and other controls. A serial/parallel converter 20 converts the input serial data into parallel data for internal handling. 21 is the data input cover sofa and inserter 18
Converts the data from the line to the signal level of the line. 22 is R
The 3-232G interface acts as an interface with terminals and computers when receiving digital data.

Further, 23 is a coaxial cable, 24 is a data bus, and 25 is an address bus. The data bus 24 and address bus 25 together constitute an internal bus within this device. Further, in the figure, 5YNC indicates a synchronization signal, and the arrow indicates a digital output. Here, each block and line numbered 19 to 25 is a digital data receiving unit 2 mainly used when receiving digital data.
6.

Next, FIG. 3 shows a system to which the voice and data receiving apparatus of the present invention as described above is connected. In the figure, 31 indicates a synchronizing signal generator, and 32 indicates a coaxial cable. Therefore, the above-mentioned coaxial cables 23 and 32 are the same cable. ).

33 represents an audio data transmitting device, 34a and 34b represent inserters, 35 represents an audio and data receiving device of the present invention, 36 represents a digital data transmitting device, and 37
indicates a couminator.

FIG. 4 shows the symbol structure on the coaxial cable 32 when receiving audio data and digital data in the system shown in FIG. 43 indicates digital data, and 44 indicates audio data. Signals on the coaxial cable 32 can be broadly classified into synchronization signals and data, and the synchronization signals are further divided into vertical synchronization signals 41 and horizontal synchronization signals 42, and data is divided into audio data 44 and digital data 43.

The vertical synchronization signal 41 has a period of 60 Hz and initializes a counter that determines the data output timing of each time division multiplexer in the system.The horizontal synchronization signal 42 is a signal that divides one vertical interval signal by 240. , counts down a counter that determines the data output timing of each time division multiplex transmitter.

The area between the horizontal synchronization signals is the data area, and its configuration is as follows:
In the figure, ST is a start bit, P
o'=P2 is a protocol bit, D.

~D+5 indicates data. In the case of digital data, it consists of 20 bits including a start bit and a protocol bit. In the case of analog data, Do=D+a in FIG. 5 is constituted by analog data each having a weight of 256.

A signal having the above-described data structure is transmitted from the coaxial cable 32 to an audio signal having the above-described structure according to the present invention.

The circuit operation when data is input to the data receiving device will be explained below using FIG.

The data signal input from the coaxial cable 23 to the operational amplifier 11 is the signal shown in FIG. 4, and FIG. 6 (al.
Shown below. 2 us (500Kllz) as shown in the same figure
The audio data 44 having 8-bit digital data a to p is input to the A/D converter 12 via the operational amplifier 11, and the A/D converter converts the same frequency (500
After being sampled by a clock signal (KHz) and converted to 8-bit digital data, it is stored in the FIFO memory 13 having registers as shown in the figure (bl).In other words, the above-mentioned 16 data are The data a-p are input sequentially, and the data a-
Since p has an 8-bit configuration, 8×16 bits are stored in the FIFO memory 13 each time audio data is input once.

On the other hand, the audio data 44 stored in the FIFO memory 13 at a cycle of 500 KHz is transmitted to the output clock generation circuit 16.
The data are sequentially read out to the D/A converter 14 using a 7680 Hz clock signal. The audio data input to the D/A converter 14 has an 8-bit configuration similar to that when input to the FIFO memory 13, and in the D/A converter 14,
The same clock signal (7680Hz) causes the same clock signal (C
1, it is converted into 130 μs analog data. The signal converted to analog data is sent to the operational amplifier 15.
is output from speaker SP via. The sound output from the speaker SP at this time is a sound controlled by a large digital capacity. That is, the above-mentioned 8×16 bits are input eight times between the horizontal synchronizing signals 42, and the vertical synchronizing signals 42 are inputted eight times.
1 is output 60 times per second, resulting in 8 bits per second x 16
is input eight times between the horizontal synchronizing signals 42, and the vertical synchronizing signals 4
1 is output 60 times per second, resulting in 8 (bits) x 16 (data) x 8 (times) x 60 (times/5ec) per second.
) = 61440 (bits) of digital capacity, coaxial cable 23 to 50
It is possible to reliably reproduce the data input to the audio and data receiving device in a time-division manner using a 0 KHz clock, and output accurate audio from the speaker SP.

As described above, the present invention is achieved by adding the audio data receiving section 10, which is also surrounded by a dotted line, to the conventional digital data receiving section 26, which is enclosed by a dotted line in FIG.

A device capable of receiving audio data input through the coaxial cable 23 in the same manner as digital data can be obtained, and the audio and data receiving device of the present invention can process audio data 44 composed of 8 bits. In other words, the audio/data receiving device of the present invention includes: (1) a circuit that temporarily stores analog data converted into digital data using a FIFO memory, and (2) a circuit that samples audio data 44 input from the coaxial cable 23 at a frequency of 500 KHz. and.

■768 audio data sampled at 500KHz
The device is characterized in that it is provided with a circuit that outputs from a speaker at 0 Hz.

The above circuit (■) completely reproduces the audio data 44 input from the coaxial cable 23 at a frequency of 500 KHz, and also reproduces the audio data 44 input from the coaxial cable 23 at a frequency of 1.
4KHz) can be reproduced satisfactorily.

In addition, in the circuit (■), the sampling frequency and the output frequency of the transmitter are the same as the signals used by the digital data time division multiplex receiver, and if processing is performed using this combination, it is possible to receive the input data without damaging it. . In other words, the data input according to the sampling frequency is 1
16 (data) x (8 times) x 60 (times/5ec) per second
)) = 7680 data/sec, the data output according to the output frequency is 7680 data per second, and the input data and output data are the same number.

〔Effect of the invention〕

As described above, according to the present invention, by adding an audio data receiving circuit to a digital data time division multiplexing receiving circuit, an apparatus is provided which can receive audio data as well as digital data.

This has the effect of further increasing the utilization of the local network system.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the present invention. FIG. 2 is a diagram showing an interconnection system between a terminal and a processing device. FIG. 3 is a diagram showing a system configuration using the device of the present invention. FIG. 4 is a diagram showing signals on a coaxial cable. FIG. 5 is a configuration diagram of the data in FIG. 4. Figures 6 (al, bl, and c) are diagrams showing the movement of data for explaining the device circuit operation of the present invention. Converter 13... FIFO memory 14...D/A converter 16...Output clock generator 17...Reception clock generator 18...Inserter. 19...Control unit 20...Parallel-serial conversion Device 21... Data input buffer 22... R8-232c interface. 23... Coaxial cable. 24... Data bus 25... Address buses are shown respectively. Fig. 2 Fig. 3 Fig. 4 # Do DI D2 r)s 040506 DF
DI DI Do On kCssDsCssFigure 6 (b) (C)

Claims (1)

[Claims] A digital data time division multiplex reception device includes a circuit for storing analog data converted into digital data using a first-in first-out memory, a circuit for sampling audio data on a coaxial cable at a frequency of 500 kHz,
An audio data receiving device characterized by having a circuit that outputs data sampled at KHz at a frequency of 7680Hz.