JPS61172298A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To refresh cells with a low power consumption without increasing the number of terminals by selecting the cell refresh mode in accordance with the combination of two specific enable signals and switching the refresh period. CONSTITUTION:When high-level signals are applied to a chip enable terminal anti-CS and an output enable terminal anti-OE together, a signal AS is outputted from a refresh control circuit 11, and a row address switching circuit 6 selects the output of a refresh address counter 12 to set the cell refresh mode. Meanwhile, the circuit 11 selects the refresh period for high temperature or low temperature in accordance with the state of the signal from a write enable terminal anti-WE, and the refresh period is optimized in accordance with the high temperature or the low temperature. Thus, cells are refreshed with a low power consumption without increasing the number of terminals neither hindering the device from being high-density.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention: A dynaic RAM (Rmndarn Access Me) using a 1nos transistor.
mory) Concerning the Nori Fretsunyu method.

[Conventional technology]

Semiconductor memories used in computer storage devices are broadly classified into storage RAM and storage RAM.

In terms of the structure of its memory cells, a dynamic RAM consists of one transistor and one capacitor, and a static RAM consists of two transistors and two resistors (four transistors in parallel may be used). Therefore, dynamic RAM is inexpensive in terms of unit price per bit.

Next, considering power consumption when no read or write is performed, static RAM has a free-lag flop circuit in terms of its memory cell structure, so the refresh operation in tie-back RAM as described later is Since it is unnecessary, the consumption is small. On the other hand, a tie-back RAM stores information (data) depending on the presence or absence of electric charge stored in a capacitor, but as time passes, the electric charge reaches a thermal equilibrium state, and the data to be stored is stored. will be destroyed. Therefore, it is necessary to read/write the data before the data is destroyed. This is called refresh. The data read at this time is controlled so as not to appear at the output terminal, but since the internal operation of the circuit is the same as that for reading data, the power consumption takes approximately the same value as when reading. However, since this value is extremely large, the refresh synchronization is usually extended to the maximum time that data can be held, reducing the number of refreshes within a certain period of time to reduce mental energy consumption. As an example, 64
In bit dynamic RAM, a refresh control terminal is provided, and refresh is performed using the input signal pulse in Nara mode (auto refresh mode).
In response to the low-level input signal, a mode (self-refresh) is performed in which refresh is performed at a predetermined period inside the IC. In this way, efforts have been made to realize memory that is inexpensive and has low power consumption per bit.

[Problem that the invention seeks to solve]

Problems with the prior art: (1) If 64 is a bit memory, a refresh terminal can be provided as shown in reference INJ, but if 256 is a bit, the terminal must be used as an address signal input terminal. Because it does not become
16 IC packages for refresh terminals
The need arises to change from pins to 18 pins. However, I
A major problem with the C package is that as the number of pins increases, its external dimensions increase, resulting in a reduction in packaging density.

A further problem is ■The refresh cycle in the master refresh mode is a constant cycle of 4, so the cycle is
It is set short to prevent data from being destroyed even when data can be retained for the shortest time at high temperatures. Therefore, when performing self-refresh at room temperature, the refresh is performed at a higher speed than necessary, and no matter how many bottles are used, it is not possible to reduce power consumption at room temperature.

[Means for solving problems]

In order to solve the above problems, the present invention is configured so that the number of terminals can be reduced, the refresh operation can be performed, and the refresh cycle can be selected from two types, for example, one for normal temperature and one for high temperature. be.

[Effect]

In dynamic RAM, which has been constructed as shown in the above example, two types of self-refresh cycles can be achieved by combining a chip enable terminal, an output enable terminal, and a write enable terminal, without providing a dedicated refresh terminal. You can choose one of them.

〔Example〕

The present invention will be described in detail below based on examples.

FIG. 1 is a block diagram of the apparatus of the present invention. C8 is the seventh chip terminal that controls chip selection and non-selection. OE is an output enable terminal that controls the output of the chip. WE controls the end surface that requires low manual force during storage and the function to select two types of self-refresh cycles.

RA Q -RA n ke, row address, CAQ-C
An is a column address input terminal. I/OQ-
I/On is the data power terminal. A low level signal input to the CS terminal passes through gate 1 and becomes input to memory control circuit 2 . From 2 to 30, a control signal 1 is used to control the address input circuit and take in the row address, and a control signal is passed through gate 4 to control the column address input circuit 5 to take in the column address. is output. The input row address passes through a 60-address switching circuit and becomes an input to a 70-decoder. On the other hand, the column address is manually controlled by an 8-power ram decoder. Both decoder outputs designate an X address in the 9 memory cell matrix, and the data stored at that address becomes the input to the data input/output control circuit 10. On the other hand, when OE becomes low level, a control signal is supplied from 2 to 10, and 10 outputs data. Korekari 116 = Do cycle dechiru. In the write cycle, after a certain X address of 9 is specified, a write control signal is output from 2, and I
The data up to /OQ=n is input to the 10 data input/output control circuit and written into the designated @ ground of the memory cell.

During refresh, a high level signal is applied to the convex and σj- at the same time, and the refresh control circuit 11 detects that this state is maintained for a certain period of time, generates the AS signal, and inputs 6 to the refresh address counter 12. Switching controls gate 4 to disable the column address input circuit.

Furthermore, in 11, depending on the state of the signal input to Wl,
Select refresh period A or refresh period Bf,
The output is outputted to the CL line to control 2 and serve as a restart signal, and at the same time, 12 is counted up and the row address is incremented every refresh cycle. At that time, if the output of 11 is As, control 10 and prevent it from outputting data! I +jL41.

FIG. 2 shows one embodiment of the refresh control circuit of FIG. The terminal names, As, and CL are the same terminals and fimbriae as in Fig. 1. When C8 and QE take a high level, the gate 101 controls the timer 102 and measures a certain period of time. For a certain period of time (4AS becomes high level, W
If the E4 child input is high level, it passes through gate 103,
104 counter hf is activated. One side, 105
The output signal from the oscillator is supplied as a clock to the counter AlO4.The counter AlO4 applies a pulse to the 106 gate at a constant frequency, and its output is released to the CL line. Also, WE4 child-1710-
At the level, the counter B108 is activated by the signal passed through the gate 107 and emits a pulse to the CL line as in the previous case. The count numbers of counters A and B are relative to refresh synchronization, so for example, set one so that the cycle is long for refreshing at material temperature, and the other so that the cycle is short for refreshing at high temperature. I'll keep it.

In this explanation, a circuit is described in which the refresh mode is set by C8 and OE and the refresh cycle is determined by WE, but the combination of terminals is not exactly the same as the described name. Further, the timer 102 in the second voice layer is not essential to the present invention. In other words, even if the output signal of the gate 101 is directly released to the As line, the present invention
The figure is fully achievable.

〔Effect of the invention〕

As described above, in the present invention, self-refresh can be performed without providing a refresh terminal, and at the same time, by switching between the refresh period for high temperatures and the refresh period for low temperatures, It is now possible to self-refresh at a longer cycle than before, and the number of times the glue is refreshed within a certain period of time can be reduced, resulting in lower power consumption at room temperature (
I get vomited.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a half-quad memory device according to the present invention. FIG. 2 is a diagram illustrating the refresh control circuit in FIG. 1 in detail. 1...Gate 2...Memory control circuit 6...Row address circuit 4...Gate 5...Column address input circuit 6...Row address off/down 47...
Rope coater 8... Column decoder 9... Memory self) IJ box 10... Data input/output control circuit 11... Refresh control circuit 12... Reflex address counter 101... Gate 102...
・Timer 103... Gate 104... Counter AlO3... Oscillator 106... Gate 107.
...Gate 108...Counter B0 or more

Claims (1)

[Claims] Dynamic memory that has a terminal that controls the selected or unselected state of the chip (chip enable terminal), a terminal that controls output (output enable terminal), and a terminal that controls read and write (write enable terminal) The device has built-in means for identifying the refresh mode based on the two input states of the terminal, and a plurality of counters controlled by the input signal of the other terminal, and the refresh address counter is controlled by the output signal of the device. A semiconductor memory device characterized by incrementing.