JPS61170035A - Method for high-accuracy etching - Google Patents
Method for high-accuracy etchingInfo
- Publication number
- JPS61170035A JPS61170035A JP1046285A JP1046285A JPS61170035A JP S61170035 A JPS61170035 A JP S61170035A JP 1046285 A JP1046285 A JP 1046285A JP 1046285 A JP1046285 A JP 1046285A JP S61170035 A JPS61170035 A JP S61170035A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- wafers
- jig
- semiconductor wafers
- rotated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005530 etching Methods 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims description 16
- 235000012431 wafers Nutrition 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000010586 diagram Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体ウェハを高精度にエツチングする方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for etching semiconductor wafers with high precision.
半導体ウェハは、シリコンインゴットをスライスした後
、ラッピング工程、ペベリング工程、エツチング工程及
び鏡面ポリシング工程等を経て製造され、更にウェハ中
に半導体デバイスを作り込むいわゆるウェハプロセスに
投入される。近年、デバイスの高集積化は益々推進され
ており、これに対応してウェハには高平坦度が要求され
るようになってきている。Semiconductor wafers are manufactured by slicing a silicon ingot and then going through a lapping process, a pevering process, an etching process, a mirror polishing process, etc., and are then put into a so-called wafer process in which semiconductor devices are fabricated in the wafer. In recent years, higher integration of devices has been promoted, and correspondingly, high flatness of wafers has been required.
ところで、上述した工程のうち、鏡面加工の前に行なわ
れるエツチング処理は、加工代を大きくとる必要がある
ため、平坦度を維持することが困難である。By the way, among the above-mentioned steps, the etching treatment performed before the mirror polishing requires a large machining allowance, making it difficult to maintain flatness.
従来、半導体ウェハのエツチング工程では、エツチング
槽内に、多数のウェハが収容されたキャリヤを浸し、ウ
ェハをローラ一方式により回転させるなどしてエツチン
グの均一化が図られてきた。Conventionally, in the etching process of semiconductor wafers, uniform etching has been achieved by immersing a carrier containing a large number of wafers in an etching tank and rotating the wafers with one type of roller.
しかし、上述した′従来の方法では設定可能な回転数の
範囲が狭く、しかもウェハの特定部位がキャリヤと接触
するためにエツチングむらが発生する等の問題があった
。このため、エツチングの精度をそれほど向上させるこ
とができなかった。However, in the conventional method described above, the range of rotational speed that can be set is narrow, and furthermore, there are problems such as uneven etching due to contact between a specific portion of the wafer and the carrier. For this reason, it was not possible to improve the etching accuracy much.
本発明は上記問題点を解消するためになされたものであ
り、エツチングむら等のない極めて高精度なエツチング
を行なえる方法を提供しようとするも′めである。The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method that can perform etching with extremely high precision without uneven etching.
本発明の高精度エツチング方法は、多数の半導体ウェハ
を収容した円筒状の容器をエツチング液に浸し、エツチ
ング液内で容器ごと回転させるとともに上下動させ、か
つ半導体ウェハを自転させることを特徴とするものであ
る。The high-precision etching method of the present invention is characterized by immersing a cylindrical container containing a large number of semiconductor wafers in an etching solution, rotating the entire container in the etching solution, moving it up and down, and rotating the semiconductor wafers. It is something.
このような方法によれば、エツチング液の攪拌が良好に
行なわれ、ウェハの回転がスムーズとなり、ウェハの特
定部分のみが治具と接触するようなことがなくなるので
、極めて高精度にエツチングを行なうことができる。According to this method, the etching solution is well stirred, the wafer rotates smoothly, and only a specific part of the wafer does not come into contact with the jig, so etching can be performed with extremely high precision. be able to.
以下、本発明の実施例を第１図（ａ）及び（ｂ）を参照
して説明する。Embodiments of the present invention will be described below with reference to FIGS. 1(a) and 1(b).
第１図（ａ）は、本発明方法に用いられるエツチング治
具を示すものである。エツチング治具本体１は半円筒形
状の２つの部分をヒンジを介して連結して、はぼ円筒形
状をなすものである。この本体１は骨格のみを有し、内
部にはエツチング液が自由に流通する。また、本体ｌ内
には半導体ウェハを１枚づつ隔離するためのガイド２、
・・・が本体ｌの長手方向に沿って等間隔に多数設けら
れている。このガイド２．・・・はエツチング液の流通
を妨げないような枠状のものである。更に、本体１の両
端面には、駆動部に連結される軸３．３が設けられてい
る。半導体ウェハ４．・・・はガイド２、・・・間の溝
内に収容される。前記エツチング治具本体ｌの直径はウ
ェハ４、・・・の直径よりも大きく、ウェハ４、・・・
がガイド２、・・・間の溝内で自由に回転できるように
なっている。FIG. 1(a) shows an etching jig used in the method of the present invention. The etching jig main body 1 has two semi-cylindrical parts connected via a hinge to form a semi-cylindrical shape. This main body 1 has only a skeleton, and the etching solution freely flows inside. Also, inside the main body l, a guide 2 for isolating semiconductor wafers one by one,
... are provided in large numbers at equal intervals along the longitudinal direction of the main body l. This guide 2. . . . is a frame shape that does not obstruct the flow of etching solution. Furthermore, on both end faces of the main body 1, shafts 3.3 are provided which are connected to the drive. Semiconductor wafer4. ... are accommodated in the grooves between the guides 2, .... The diameter of the etching jig main body l is larger than the diameter of the wafers 4, .
can rotate freely within the groove between the guides 2, .
上記エツチング治具を用いたエツチングは、第１図（ｂ
）に示す如く半導体ウェハ４、・・・を収容した後、エ
ツチング治具ごとエツチング槽５内のエツチング液６に
浸し、前記軸３．３を介して図示しない回転駆動機構及
び上下動機構の動力を受け、エツチング治具を回転及び
上下動させるとともに半導体ウェハ４、・・・を自転さ
せることにより行なわれる。Etching using the above etching jig is shown in Figure 1 (b).
), after storing the semiconductor wafers 4, . The etching is performed by rotating and vertically moving the etching jig and rotating the semiconductor wafers 4, . . . .
しかして上記方法によれば、エツチングＷｌＧ中でエツ
チング治具自体を回転させるので、エツチング液６の攪
拌が速やかに行なわれる。また、ウェハ４、・・・の回
転がスムーズで、かつ設定可能な回転数の範囲が広く、
容易にエツチングの適性条件を設定することができる。According to the above method, since the etching jig itself is rotated in the etching WlG, the etching liquid 6 is rapidly stirred. In addition, the rotation of the wafers 4, etc. is smooth, and the range of rotation speed that can be set is wide.
Etching suitability conditions can be easily set.
更に、ウェハ４、・・・がガイド２、川に対して相対的
に回転するので、ウェハ４．・・・の特定部分のみがガ
イド２、・・・と接触することがない、したがって、ウ
ニへ面内及びウェハ間でエツチング液均一に進行し、極
めて高精度のエツチングを行なうことができる。Further, since the wafers 4, . . . rotate relative to the guide 2, the wafers 4, . Only specific portions of the wafers 2, . . . do not come into contact with the guides 2, .
なお、上記実施例では半導体ウェハをそのまま収容し得
る専用のエツチング治具を用いたが、第２図（ａ）及び
（ｂ）に示す如く、エツチング治具本体１１の内部にウ
ェハキャリヤの固定部１２．１２及びウェハのストッパ
ー１３を設けるとともに、本体１１の端面に駆動部に連
結される軸１４．１４を設けたエツチング治具を用いて
もよい。In the above embodiment, a dedicated etching jig that can accommodate the semiconductor wafer as it is was used, but as shown in FIGS. An etching jig may be used, which is provided with a wafer stopper 13 and a shaft 14, 14 on the end face of the main body 11, which is connected to a drive section.
このようなエツチング治具を用いた場合、その内部に多
数のウェハ１５、・・・を収容したウェハキャリヤ１６
を装填した後、上記実施例のエツチング治具と同様にエ
ツチング液中に浸し、治具自体を回転及び上下動させる
とともに、治具内のウェハ１５、・・・を自転させるこ
とによりエツチングを行なう。When such an etching jig is used, a wafer carrier 16 containing a large number of wafers 15, . . .
After loading, the etching jig is immersed in an etching solution in the same way as the etching jig in the above embodiment, and the jig itself is rotated and moved up and down, and the wafers 15, etc. inside the jig are rotated to perform etching. .
このようなエツチング治具を用いた場合でも上記実施例
と全く同様な効果を得ることができる。Even when such an etching jig is used, the same effects as in the above embodiment can be obtained.
以上詳述した如く本発明方法によれば、半導体ウェハを
高精度にエツチングすることができ、半導体製品の歩留
りを大きく向上できる等顕著な効果を奏するものである
。As detailed above, according to the method of the present invention, semiconductor wafers can be etched with high precision, and the yield of semiconductor products can be greatly improved.
【図面の簡単な説明】
第１図（ａ）は本発明の実施例において用いられるエツ
チング治具の断面図、同図（ｂ）は本発明の実施例にお
けるエツチング方法を示す説明図、第２図（ａ）は本発
明の他の実施例において用いられるエツチング治具の断
面図、同図（ｂ）は本発明の他の実施例におけるエツチ
ング方法を示す説明図である。
１、ｉｌ・・・エツチング治具本体、２・・・ガイド、
３．１４・・・軸、４．１５・・・半導体ウェハ、５・
・・エツチング槽、６・・・エツチング液、１２・・・
固定部、１３・・・ストッパー、１６・・・ウェハキャ
リヤ。
出願人代理人 弁理士 給圧 武彦
第１図
（ａ） （ｂ）
第２図
（ａ） （ｂ）[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1(a) is a sectional view of an etching jig used in an embodiment of the present invention, FIG. 1(b) is an explanatory diagram showing an etching method in an embodiment of the present invention, and FIG. Figure (a) is a sectional view of an etching jig used in another embodiment of the present invention, and Figure (b) is an explanatory diagram showing an etching method in another embodiment of the present invention. 1, il...Etching jig body, 2...Guide,
3.14... Axis, 4.15... Semiconductor wafer, 5.
... Etching tank, 6... Etching liquid, 12...
Fixed part, 13... stopper, 16... wafer carrier. Applicant's agent Patent attorney Supply pressure Takehiko Figure 1 (a) (b) Figure 2 (a) (b)
Claims (1)
グ液に浸し、該容器を回転させるとともに上下動させ、
かつ半導体ウェハを自転させることを特徴とする高精度
エッチング方法。A cylindrical container containing a large number of semiconductor wafers is immersed in an etching solution, the container is rotated and moved up and down,
A high-precision etching method characterized by rotating a semiconductor wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1046285A JPS61170035A (en) | 1985-01-23 | 1985-01-23 | Method for high-accuracy etching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1046285A JPS61170035A (en) | 1985-01-23 | 1985-01-23 | Method for high-accuracy etching |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61170035A true JPS61170035A (en) | 1986-07-31 |
| JPH0543176B2 JPH0543176B2 (en) | 1993-06-30 |
Family
ID=11750798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1046285A Granted JPS61170035A (en) | 1985-01-23 | 1985-01-23 | Method for high-accuracy etching |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61170035A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11066277B2 (en) | 2018-04-25 | 2021-07-20 | Otis Elevator Company | Gap-reducing sill assembly for an elevator car |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50188A (en) * | 1973-04-24 | 1975-01-06 | ||
| JPS5521165A (en) * | 1978-08-01 | 1980-02-15 | Nec Corp | Wafer processing device |
| JPS5678246U (en) * | 1979-11-06 | 1981-06-25 | ||
| JPS58157136A (en) * | 1982-03-15 | 1983-09-19 | Hitachi Ltd | Device for etching |
| JPS59169042U (en) * | 1983-04-26 | 1984-11-12 | 日本電気ホームエレクトロニクス株式会社 | Liquid processing equipment |
| JPS602830U (en) * | 1983-06-20 | 1985-01-10 | 日本電気株式会社 | Semiconductor wafer etching tank |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS602830B2 (en) * | 1976-12-09 | 1985-01-24 | ソニー株式会社 | Video signal recording method |
-
1985
- 1985-01-23 JP JP1046285A patent/JPS61170035A/en active Granted
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50188A (en) * | 1973-04-24 | 1975-01-06 | ||
| JPS5521165A (en) * | 1978-08-01 | 1980-02-15 | Nec Corp | Wafer processing device |
| JPS5678246U (en) * | 1979-11-06 | 1981-06-25 | ||
| JPS58157136A (en) * | 1982-03-15 | 1983-09-19 | Hitachi Ltd | Device for etching |
| JPS59169042U (en) * | 1983-04-26 | 1984-11-12 | 日本電気ホームエレクトロニクス株式会社 | Liquid processing equipment |
| JPS602830U (en) * | 1983-06-20 | 1985-01-10 | 日本電気株式会社 | Semiconductor wafer etching tank |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0543176B2 (en) | 1993-06-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |