JPS61168061A - Data protecting system - Google Patents
Data protecting systemInfo
- Publication number
- JPS61168061A JPS61168061A JP60008608A JP860885A JPS61168061A JP S61168061 A JPS61168061 A JP S61168061A JP 60008608 A JP60008608 A JP 60008608A JP 860885 A JP860885 A JP 860885A JP S61168061 A JPS61168061 A JP S61168061A
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- memory
- encryption
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Storage Device Security (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、コンピュータシステムに於いて、製造し使用
されるデータに対し暗号化及び復号化を何なう拳によっ
て、データの盗用及び盗視の防止に胸するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to data theft and eavesdropping by encrypting and decoding data produced and used in computer systems. We are deeply concerned about the prevention of this.
従来、この株の盗用及び盗視に対する方式り。 Traditionally, this method has been used to prevent theft and eavesdropping on stocks.
大別して三方式N!D、M−の方式としてり、データ扛
そのままでそのデータに対しての不正アクセスの防止と
して、ハードウェア及びソフトウェアに於いて谷−キー
ワードを設ゆ、第二者がデータをアクセスする拳を7ス
テム側で監視し糸上する方式でめシ、第二の方式として
扛、データ自体を暗号化する方式でメジ、通常データの
人出力が打なわれる装置ごとに暗号化装置tあるいは回
路金膜ける方式とかめる。Broadly divided into three methods N! In order to prevent unauthorized access to the data while the data is intact, a valley keyword is established in the hardware and software to prevent a second party from accessing the data. The second method is to monitor and thread the stem, the second method is to encrypt the data itself, and the encryption device or circuit gold film is used for each device where the human output of normal data is entered. How to get it.
上述した従米の方式に於いて、第一の方式はデータに対
して殴ったキーに対し、システム側で常時管理する必賛
が有p、第三者によってキーの盗用により簡単に内存を
盗視される欠点をMし、又第二の方式に於いては中央処
理bahに暗号化回路が黒い事から、データの人出力が
行なわれる装[全てに対して、谷植晰号化回路あるいは
装置が必要で、入出力装置自体が高価なものKなシ、更
に谷1)it号化回路ごとに制御を行なう為処理が複雑
となる欠点かめる。In the above-mentioned method, the first method requires the system to constantly manage the keys that are used against the data, and a third party can easily stealth the key by stealing the key. In addition, in the second method, since the encryption circuit is black in the central processing bah, it is necessary to have an encryption circuit or device for all systems in which data is output manually. However, the input/output device itself is expensive, and 1) the processing is complicated because control is performed for each IT encoding circuit.
不発BAh、王メモリとCPU間に於いて、主メモリに
データを誉込む場合の暗号化回路と、主メモリよプデー
タを絖み出す場合のデータ復号化回船と、それぞれの回
路を制御する暗号鍵回路を臂している。Unexploded BAh, between the main memory and the CPU, there is an encryption circuit for loading data into the main memory, a data decoding circuit for outputting data from the main memory, and a cipher that controls each circuit. I'm leaning over the key circuit.
データの暗号化は、データを主メモリに書込む場合でる
り、暗号化鍵回路を動作させ、暗号化回路を製作可能と
し、CPUからのメモリへの薔込み制御ごとにデータを
暗号化し主メモリへ格納する、又この暗号化されたデー
タの復号化は暗号化無回路動作後、復号化回路により、
メモリからCPUへ飢み出すごとにデータの復号化が行
なわれる。When data is written to the main memory, data is encrypted by operating an encryption key circuit and making it possible to manufacture an encryption circuit. This encrypted data is then decrypted by the decryption circuit after the encryption circuitless operation.
Data is decoded each time it is transferred from memory to the CPU.
次に不発明の実施rJKついて図面全参照して説明する
。Next, the implementation rJK of the non-invention will be explained with reference to all the drawings.
図拡不発明の一実施例のブロック図であシ、1は中央処
理装置1llic((、PU)、2tXm−Q北回j6
.3は暗号化回路、4は暗号鍵回路、5は暗号鏝回路制
#融、6は暗号化回路起動線、7は復号化回路起M1m
11.8社命令フィッチ制御1嶽、9はデータバスであ
る。This is a block diagram of an embodiment of the invention, 1 is a central processing unit 1llic ((, PU), 2t
.. 3 is an encryption circuit, 4 is an encryption key circuit, 5 is an encryption circuit system, 6 is an encryption circuit start line, and 7 is a decryption circuit start line M1m.
11.8 company instruction fitch control 1x, 9 is a data bus.
本実施例に於いては、データの暗号化及び復号化動作と
に分けて説明する。In this embodiment, data encryption and decryption operations will be explained separately.
(イ)暗号化製作
データの暗号化を行なう場合、ますCPU1は暗号鍵回
路4を緬動し、暗号化回路3をセット後、CPU1がメ
モリへ誉込む時に出力されるデータが暗号化回路3を通
過するごとにデータの暗号化が行なわれ、データバス9
を経由してメモリへ格納される。又、プログラムの簀込
みを行なう場合あるい轄、暗号を行なわない場合は、暗
号鍵回路−4t−停止することによりデータは暗号化さ
れずにメモリへ格納される。(b) When encrypting the encrypted production data, the CPU 1 activates the encryption key circuit 4, sets the encryption circuit 3, and then outputs the data to the encryption circuit 3 when the CPU 1 writes it into the memory. The data is encrypted each time it passes through the data bus 9.
is stored in memory via . Further, when a program is stored or when no encryption is performed, the data is stored in the memory without being encrypted by stopping the encryption key circuit 4t.
(ロ) 復号化動作
データの復号化は、メモリよpcPUへの続出し時に行
なわれるものであり、lのCPUj″i4の曖号−1g
1結を起動し、5の復号化回路をセット後。(b) Decoding of decoding operation data is performed when successively outputting from memory to pcPU, and the ambiguous code of CPU j″i4 of l
After starting the 1st knot and setting the 5th decoding circuit.
lのCPLIがメモリよりデータを胱出し時に、データ
が5の復号化回路を通過するごとにデータの復号化か行
なわれる。又CPUIがプログラムを実行する場合も同
様にメモリよりデータが復号化回路を通過するがその際
8の命令ツイツチ制御線により復号化回路は動作せずデ
ータは復号化回路を透過し、館令としてCPUIへ入力
辿れ実行される。When the 1 CPLI retrieves data from the memory, the data is decoded every time the data passes through the 5 decoding circuits. Similarly, when the CPU executes a program, data from the memory passes through the decoding circuit, but at that time, the decoding circuit does not operate due to the command twitch control line 8, and the data passes through the decoding circuit, and is The input is traced to the CPUI and executed.
以上rI5!明したように本発明り、三つの回路及びそ
れらを制御する制御14I−よプ構成される為、回路の
一元化か図かれる為、従来のデータに対するキー等は必
要でなく、仮に本発明の暗号鍵回路の起動方式が盗用さ
れたとしても、他のCPUに於いては復号化回路が存在
しない為、データは利用不可となシ、データの盗用盗視
に対して充分な防術効果がある。又、CPUに接続され
ている為、外部機器とは無胸係となり、通常の装置を使
用出来る効果を有する。That’s all rI5! As explained above, since the present invention is composed of three circuits and a control 14I for controlling them, the circuits can be unified, so there is no need for conventional keys for data, and even if the encryption of the present invention is Even if the activation method of the key circuit is stolen, the data will not be usable because there is no decryption circuit in other CPUs, and there is a sufficient defensive effect against data theft and eavesdropping. . Moreover, since it is connected to the CPU, it is not connected to external equipment, and has the effect of allowing the use of normal equipment.
図り本発明の実施例を示すブロック図でめる。
1・・・・・・中央処!ailc(CPU)、2・・・
・・・復号化回路、3・・・・・・暗号化回路、4・・
・・・・暗号鍵回路、5・・・・・・暗号糎回路制御線
、6・・・・・・暗号化回路起動線、7・・・・・・復
号化回路起動縁、8・・・・・・命令ツイツチ制御縁、
9・・・・・・データバス。1 is a block diagram showing an embodiment of the present invention. 1... Central location! ailc (CPU), 2...
...Decryption circuit, 3...Encryption circuit, 4...
... Encryption key circuit, 5... Encryption circuit control line, 6... Encryption circuit starting line, 7... Decryption circuit starting edge, 8... ... Command twitch control edge,
9...Data bus.
Claims (1)
中心として構成されるデータ処理装置に於いて、主メモ
リより前記CPUに入力されるデータ暗号復号化回路と
、前記主メモリに出力されるデータの暗号化回路と、前
記2つの回路の制御を行なわしめる暗号鍵回路からなる
ソフトウェアデータの盗視を防止せしめるデータ保護方
式。In a data processing device that is configured around at least one central processing unit (hereinafter abbreviated as CPU), there is a data encryption/decryption circuit that inputs data from a main memory to the CPU and outputs data to the main memory. A data protection system that prevents eavesdropping on software data consisting of a data encryption circuit and an encryption key circuit that controls the two circuits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60008608A JPS61168061A (en) | 1985-01-21 | 1985-01-21 | Data protecting system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60008608A JPS61168061A (en) | 1985-01-21 | 1985-01-21 | Data protecting system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61168061A true JPS61168061A (en) | 1986-07-29 |
Family
ID=11697671
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60008608A Pending JPS61168061A (en) | 1985-01-21 | 1985-01-21 | Data protecting system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61168061A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0268641A (en) * | 1988-08-17 | 1990-03-08 | Corns & Co Ltd | Security protective system of integrated circuit |
JPH02155034A (en) * | 1988-12-08 | 1990-06-14 | Toshiba Corp | Computer with security function |
JPH05179738A (en) * | 1991-12-28 | 1993-07-20 | Tostem Corp | Fixing device of glass panel for curtain wall |
-
1985
- 1985-01-21 JP JP60008608A patent/JPS61168061A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0268641A (en) * | 1988-08-17 | 1990-03-08 | Corns & Co Ltd | Security protective system of integrated circuit |
JPH02155034A (en) * | 1988-12-08 | 1990-06-14 | Toshiba Corp | Computer with security function |
JPH05179738A (en) * | 1991-12-28 | 1993-07-20 | Tostem Corp | Fixing device of glass panel for curtain wall |
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