JPS61164503U

JPS61164503U -

Info

Publication number: JPS61164503U
Application number: JP4573685U
Authority: JP
Priority date: 1985-03-28
Filing date: 1985-03-28
Publication date: 1986-10-13

Description

[Brief explanation of the drawing]

第１図は本考案一実施例の調節計を示す概略図
、第２図は従来の調節計の一例を示す概略図であ
る。１……デイジタルコントローラ、２……パネル
表示部、３……マルチプレクサ、４……Ａ／Ｄ変
換器、５……アツピダウンカウンタ、６……Ｄ／
Ａ変換器、７……パネル制御部、８……マイクロ
プロセツサ、９……メモリ、１０……キーボード
制御部、１１……システムＰＲＯＭ。 FIG. 1 is a schematic diagram showing a controller according to an embodiment of the present invention, and FIG. 2 is a schematic diagram showing an example of a conventional controller. 1...Digital controller, 2...Panel display section, 3...Multiplexer, 4...A/D converter, 5...Atsupi down counter, 6...D/
A converter, 7...Panel control unit, 8...Microprocessor, 9...Memory, 10...Keyboard control unit, 11...System PROM.

Claims

[Claims for Utility Model Registration] 1. An analog-to-digital converter for converting a measured value signal from a detector into analog-to-digital format, means for storing set values, and control calculation for the measured value signal converted into a digital quantity. The apparatus is characterized in that it comprises means for generating calculation results as operation outputs, and display means provided on the panel surface for displaying measured values, operation outputs, etc., and said display means is constituted by a dot matrix display element. controller. 2. The controller according to claim 1, wherein the process amount, operation amount, etc. are displayed using a bar graph display. 3. The controller according to claim 2, wherein a scale is displayed using a dot matrix display element in conjunction with the bar graph display. 4. The controller according to any one of claims 1 to 3, wherein the dot matrix display element displays setting values, memory pointers for operation outputs, etc.