JPS61158858U - - Google Patents

Info

Publication number
JPS61158858U
JPS61158858U JP11061884U JP11061884U JPS61158858U JP S61158858 U JPS61158858 U JP S61158858U JP 11061884 U JP11061884 U JP 11061884U JP 11061884 U JP11061884 U JP 11061884U JP S61158858 U JPS61158858 U JP S61158858U
Authority
JP
Japan
Prior art keywords
circuit
flip
rising edge
flop
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11061884U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11061884U priority Critical patent/JPS61158858U/ja
Publication of JPS61158858U publication Critical patent/JPS61158858U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Measurement Of Current Or Voltage (AREA)
JP11061884U 1984-07-20 1984-07-20 Pending JPS61158858U (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11061884U JPS61158858U (de) 1984-07-20 1984-07-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11061884U JPS61158858U (de) 1984-07-20 1984-07-20

Publications (1)

Publication Number Publication Date
JPS61158858U true JPS61158858U (de) 1986-10-02

Family

ID=30669742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11061884U Pending JPS61158858U (de) 1984-07-20 1984-07-20

Country Status (1)

Country Link
JP (1) JPS61158858U (de)

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