JPS61157083A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To compensate the dispersion of dark-time output of each picture element by adjoining each 'light output + dark-time output' and 'dark-time output' at the same integral time from each photo sensitive picture element and by outputting in time series. CONSTITUTION:Specified AC voltage is impressed to a barrier gate 12 and an integral clear gate 13 is opened and an electric charge in an accumulated electrode is cleared. After specified time integral, a migration gate 16 is opened and outputted signals (light output + dark-time output) are stored in a CCD register 17. And the CCD register 17 is put forward only one transfer step and stopped. Next, the barrier gate 12 is closed and the migration of electric charge from the photo sensitive picture element 11 to the accumulated electrode 15 is stopped and the electric charge is cleared at integral clear gate 13. After the same time integration of dark current, the migration gate 16 is opened and the electric charge for dark-time output is stored in a CCD register 17. A read-out and a clock pulse are supplied to the CCD register in order to obtain a time series output and the dark-time output is compensated by executing subtraction of adjoining output Si and SBi.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a solid-state imaging device suitable for compensating for dark output components included in signal output and expanding the dynamic range of the device.

[Technical background of the invention and its problems]

Generally, a solid-state imaging device is configured as shown in FIG. 4, for example. In addition, here, to simplify the explanation, 5
Shown as pixels. In the figure, 1 is a semiconductor substrate, 2-1
are photosensitive pixels covered with light-shielding film buttons, 2-2 to 2-5 are photosensitive pixels, 3-1 to 3-5 are integral clear darts, 4-1 to 4
-5 is the drain to which positive voltage is applied, 5-1 to 5 to 5
6 is a storage electrode, 6 is a transfer electrode, 7 is a CCD lenostaff, 8 is an output circuit of the CCD lenostaff, and 9 is an output terminal.

The operation of the above configuration will be briefly described. First, the integral clear f-gates 3-1 to 3-5 are opened to remove the charges under the storage electrodes 5-1 to 5-5. Integration operation starts from here, and after the charges generated by photoelectric conversion by the photosensitive pixels 2-1 to 2-5 are integrated for a predetermined time, they are transferred all at once to the CCD Renostaph by opening the transfer gate 6. Ru. Thereafter, by supplying a clock pulse (not shown) to the CCD lenosphere, charges are sequentially transferred within the CCD lenosphere. The transferred charges are then subjected to charge-voltage conversion in the output circuit 8 and outputted from the output terminal 9 as a time series signal OUT.

By the way, in the above configuration, the dark output, that is, the output component due to the charge generated due to thermal causes in the photosensitive pixel and the charge storage section, is the output of the photosensitive pixel 2-1 whose photosensitive section is covered with a light shielding film. It is measured by reading. Therefore, as shown in FIG.
By subtracting the dark time output component S1 of the photosensitive pixel 2-1 from the signal output portion 82 to S5, an accurate photoelectric conversion output can be obtained. Note that R8 is reset noise.

However, with the method of correcting the dark output component as described above, there is no problem if the dark output of each photosensitive pixel 2-2 to 2-5 is the same, but the dark output of each photosensitive pixel varies. Is it an incorrect correction? There are drawbacks to doing so.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide an excellent solid-state imaging device that can also compensate for variations in dark output for each photosensitive pixel.

[Summary of the invention]

That is, in the present invention, in order to achieve the above object, "light output + dark output" and "dark output" from each photosensitive pixel at the same integral time are respectively arranged as time-series output signals. When reading out "light output + dark output", the charge from the photosensitive pixel is transferred to the storage section, and when reading out "dark output" only, the charge from each photosensitive pixel is transferred to the storage section. A charge transfer control means for stopping the flow, a charge discharge means for clearing the charge under the storage electrode regardless of the state, and after storing "light output + dark output" all at once, reading only one transfer stage, A CCD register is provided for storing and transferring the next dark period output all at once (two transfer stages are required for each storage electrode for such an operation).

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. On the semiconductor substrate 10 in FIG.
, storage electrodes 15-1 to 15-5, transfer? -G16, CC
DL/CCD register 17 path 18 and output terminal 19
are provided to constitute a solid-state imaging device. Note that a positive voltage is applied to the drains 14-1 to 14-5.

Next, the operation in the above configuration will be explained. First, a predetermined DC voltage is applied to the barrier ff-gate 12, and from each photosensitive pixel 1 no. 1 to 11-5 to the storage electrode 15-1 to 15-1.
5-5, and clear the integral e-
Open ports 13-1 to 13-5 and connect storage electrodes 15-1 to 15-1.
5-5 Clear the charge below. After this clearing operation, integration is started, and after integration for a predetermined time, the transfer gate is opened and the signal portion (light output+dark output) is stored in the CCD register 17. Then, the CCD Renostuff 7 is advanced by one transfer stage and then stopped. Next, the pariah gate 12 is closed to stop the transfer of charges from the photosensitive pixels 11-1 to 11-5 to the storage electrodes 15-1 to 15-5. Then, open the integral clear darts 13-1 to 13-5 and store the storage electrodes 15-1 to 15-1.
The charge under 5 is cleared, and the dark current under this storage electrode is integrated for the same integration time as the above-mentioned "light output + dark output".

After this integration is completed, the transfer gate 16 is opened, and the charge corresponding to the output during the dark period is stored in the CCD rhenostaph 7.

Next, the CCD register 17 is supplied with the necessary number of clock pulses t4 for reading to obtain a time-series output. Thereafter, the above-described operations are sequentially repeated.

FIG. 2 shows the waveform of the output signal OUT obtained from the output terminal 19 by the above-described operation. As shown in the figure, the signal of each photosensitive pixel 1-1 to 11-5 (light output +
Dark time output) S1 to S5 and dark time output components BS1 to BS5 are output adjacent to each other. Therefore, these two adjacent outputs St, B51 (i=1.2, 3, 4.5
), the dark time output can be corrected by subtracting the floating f-), or by delaying the output by 1° and subtracting the two outputs Sl and SBi.

According to such a configuration, since the dark output component can be corrected for each photosensitive pixel, even if there is variation in the dark output for each photosensitive pixel, this can be compensated for.

FIG. 3 shows another embodiment of the present invention, in which the charge transfer control function is improved. In the figure, the same components as those in FIG. That is, on the opposite side of the barrier gate 12 of the photosensitive pixels 11-1 to 11-5, an O-G flow control dirt 20 and an overflow drain 2 are installed.
1 was used.

In the above configuration, when a DC voltage is applied to the barrier route 12, the photosensitive pixels 11-1 to ll-5
The charges generated by the storage electrodes 15-1 to 15-
5 and when the veria r-t 12 is closed, it is discharged to the overflow drain 21 via the control y-t 20t-. Therefore, the potential well under the control dart 20 is set to an intermediate value between the potential well under the barrier dart when the barrier gate 12 is open and the potential well when the barrier gate 12 is closed.

According to such a configuration, the photosensitive pixels 11-1 to 11-5
can completely block the charge.

In addition, in each of the above embodiments, in order to simplify the explanation, 5
Although the number of pixels has been described, it goes without saying that the number is not limited to this number.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain an excellent solid-state imaging device that can also compensate for variations in the dark output of each photosensitive pixel.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a diagram showing output waveforms of the device shown in FIG. 1, and FIG. 3 is a diagram showing another embodiment of the invention. Configuration diagram, 4th
This figure is a block diagram showing a conventional solid-state imaging device, and FIG. 5 is a diagram showing an output waveform of the device shown in FIG. 4. 10... Semiconductor substrate, 11-1 to 11-5... Photosensitive pixel, 12... Barrier group), 13-1 to 13-5.
... Integral clear date, 14-1 to 14-5... Drain, 15-1 to 15-5... Storage electrode, 16...
Transfer dart, 17... CCD reno star, 18... Output circuit, 19... Output terminal.

Claims (1)

[Claims] A plurality of photosensitive pixels arranged on a semiconductor substrate perform photoelectric conversion, charge storage electrodes for charge storage arranged adjacent to each of these photosensitive pixels, and charges accumulated under these charge storage electrodes in sequence. A CCD register for transfer,
In the solid-state imaging device, the solid-state imaging device includes a transfer electrode that simultaneously transfers the charges accumulated under the charge storage electrode to the CCD register in synchronization with an external signal, from each of the photosensitive pixels according to an external control signal. A charge transfer control means for stopping and restarting the transfer of charge under the storage electrode, and a charge discharge means for discharging the charge under the charge storage electrode in response to an external control signal are provided, and the CCD register is connected to one storage electrode. A solid-state imaging device characterized in that it has two transfer stages.