JPS61156253U - - Google Patents

Info

Publication number
JPS61156253U
JPS61156253U JP3864885U JP3864885U JPS61156253U JP S61156253 U JPS61156253 U JP S61156253U JP 3864885 U JP3864885 U JP 3864885U JP 3864885 U JP3864885 U JP 3864885U JP S61156253 U JPS61156253 U JP S61156253U
Authority
JP
Japan
Prior art keywords
lead wires
staggered
electronic device
utility
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3864885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3864885U priority Critical patent/JPS61156253U/ja
Publication of JPS61156253U publication Critical patent/JPS61156253U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す斜視図、第2
図は第1図のF―F線矢視図、第3図は本考案の
他の実施例を示す斜視図、第4図は第3図のG―
G線矢視図、第5図は従来の発光ダイオードの一
例を示す斜視図、第6図はこの発光ダイオードの
実装例を示す斜視図である。 10……電子素子(発光ダイオード)、12a
,12b……リード線、16……本体。
Fig. 1 is a perspective view showing one embodiment of the present invention;
The figure is a view taken along line F--F in FIG. 1, FIG. 3 is a perspective view showing another embodiment of the present invention, and FIG.
5 is a perspective view showing an example of a conventional light emitting diode, and FIG. 6 is a perspective view showing an example of mounting this light emitting diode. 10...Electronic element (light emitting diode), 12a
, 12b... Lead wire, 16... Main body.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 2本以上のリード線を有する電子素子において
、前記リード線をツイストペアにして前記リード
線の各始端と各終端とをずらしたことを特徴とす
る電子素子。
1. An electronic device having two or more lead wires, characterized in that the lead wires are formed into a twisted pair and the starting ends and ending ends of the lead wires are staggered.
JP3864885U 1985-03-18 1985-03-18 Pending JPS61156253U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3864885U JPS61156253U (en) 1985-03-18 1985-03-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3864885U JPS61156253U (en) 1985-03-18 1985-03-18

Publications (1)

Publication Number Publication Date
JPS61156253U true JPS61156253U (en) 1986-09-27

Family

ID=30545852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3864885U Pending JPS61156253U (en) 1985-03-18 1985-03-18

Country Status (1)

Country Link
JP (1) JPS61156253U (en)

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