JPS61155964U - - Google Patents
Info
- Publication number
- JPS61155964U JPS61155964U JP3745285U JP3745285U JPS61155964U JP S61155964 U JPS61155964 U JP S61155964U JP 3745285 U JP3745285 U JP 3745285U JP 3745285 U JP3745285 U JP 3745285U JP S61155964 U JPS61155964 U JP S61155964U
- Authority
- JP
- Japan
- Prior art keywords
- processor
- data
- optical transceiver
- adjacent
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 claims description 3
Landscapes
- Multi Processors (AREA)
Description
図はこの考案の一実施例を示す平面図である。
１１〜１ｎ……単位プロセツサ、２ａ〜２ｄ…
…光送受信器。
The figure is a plan view showing an embodiment of this invention. 1 1 to 1n... unit processor, 2 a to 2 d ...
...Optical transceiver.
補正 昭６０．７．１８
図面の簡単な説明を次のように補正する。
明細書４頁５行「図は…である。」を「第１図
はこの考案の一実施例を示す平面図である。」と
補正する。Amendment July 18, 1980 The brief description of the drawing is amended as follows. ``The figure is...'' on page 4 of the specification, line 5, is amended to read ``Figure 1 is a plan view showing one embodiment of this invention.''
Claims (1)
セツサは単位プロセツサの内部でデータの処理を
行なうとともに、隣接する単位プロセツサとの間
でデータの授受を行なうアレイプロセツサ装置に
おいて、それぞれの単位プロセツサに隣接プロセ
ツサとの間で通信を行なうための光送受信器を設
け、この光送受信器を介してデータの授受を行な
うことを特徴とするアレイプロセツサ装置。 In an array processor device that has a plurality of unit processors, each processor processes data within itself and also exchanges data with adjacent unit processors, each unit processor has an adjacent processor. An array processor device characterized in that it is provided with an optical transceiver for communicating with the processor, and data is exchanged via the optical transceiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3745285U JPS61155964U (en) | 1985-03-18 | 1985-03-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3745285U JPS61155964U (en) | 1985-03-18 | 1985-03-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61155964U true JPS61155964U (en) | 1986-09-27 |
Family
ID=30543544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3745285U Pending JPS61155964U (en) | 1985-03-18 | 1985-03-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61155964U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03248258A (en) * | 1990-02-27 | 1991-11-06 | Nec Corp | Arithmetic unit |
| JPH05233568A (en) * | 1992-02-21 | 1993-09-10 | Hikari Gijutsu Kenkyu Kaihatsu Kk | Optically connected parallel microprocessor system |
-
1985
- 1985-03-18 JP JP3745285U patent/JPS61155964U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03248258A (en) * | 1990-02-27 | 1991-11-06 | Nec Corp | Arithmetic unit |
| JPH05233568A (en) * | 1992-02-21 | 1993-09-10 | Hikari Gijutsu Kenkyu Kaihatsu Kk | Optically connected parallel microprocessor system |
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