JPS6115144A - Photomask - Google Patents

Photomask

Info

Publication number
JPS6115144A
JPS6115144A JP59135075A JP13507584A JPS6115144A JP S6115144 A JPS6115144 A JP S6115144A JP 59135075 A JP59135075 A JP 59135075A JP 13507584 A JP13507584 A JP 13507584A JP S6115144 A JPS6115144 A JP S6115144A
Authority
JP
Japan
Prior art keywords
photomask
base material
mask
heater
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59135075A
Other languages
Japanese (ja)
Inventor
Kiyohiro Kawasaki
清弘 川崎
Hiroshi Kuroda
黒田 啓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59135075A priority Critical patent/JPS6115144A/en
Publication of JPS6115144A publication Critical patent/JPS6115144A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

PURPOSE:To improve the yield by using a glass plate, etc. as a base material, forming a thin film pattern for transmitting no ultraviolet rays, on its one main surface, and embedding a heating element heated by electric conduction, into the base material in the outside of an area in which said pattern exists. CONSTITUTION:In order that exposure is not obstructed, a line-shaped or tape- shaped heater 8 is placed in an area except an area 7 in which a mask pattern 6 exists, namely, the peripheral part of a photomask 5. An electric conduction terminal 9 for applying a current for heating to the heater 8 is provided, and the heater 8 is placed on the photomask 5 or embedded in the mask 5. Or the heater 8 is formed on the mask 5, and thereafter, coated with a resin.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、写真食刻用フォト7スクに関し、とぐに大面
積素子または装置の写真食刻に適したフォトマスクに関
するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a photomask for photolithography, and more particularly to a photomask suitable for photolithography of large area devices or devices.

(従来例の構成とその問題点) 写真食刻技術は、ある被食刻材を選択的に食刻するとき
にマスク材として作用する感光性樹脂パターンを形成す
る技術で、構成要素は露光機、感光性樹脂、フォトマス
クおよび感光性樹脂の現像工程である。半導体素子に代
表されるデバイスなどでは通常数回もの各種薄膜の食刻
工程が行なわれるので、浩然写真食刻工程では各工程毎
に・Pターンの相対的な位置合わせ、通称マスク合わせ
が必要である。
(Structure of conventional example and its problems) Photo-etching technology is a technology that forms a photosensitive resin pattern that acts as a mask material when selectively etching a certain material to be etched. , photosensitive resin, photomask, and photosensitive resin development process. In devices such as semiconductor devices, various thin film etching processes are usually performed several times, so in the photo-etching process, relative positioning of P-turns, commonly known as mask alignment, is required for each process. be.

第1図は、マスク合わせの硫念を示すための説明図で、
1 、1’はンリコンなどの基材Sに前の写真食刻およ
び食刻工程で形成された・セターンであり、2,2′は
フォトマスク上に形成されているマスク合わせのための
パターン(通称キー)で必る。
Figure 1 is an explanatory diagram to show the importance of mask alignment.
1 and 1' are setans formed on the substrate S such as silicone in the previous photolithography and etching process, and 2 and 2' are patterns for mask alignment formed on the photomask ( (commonly known as key).

通常キー2は・ぐターフ1内に納捷ればよいように適当
な余裕aが与えられる。第1図(a)では、話を簡単に
するため、キー2がパターン1の中心に合った状態が示
されている。キー2は各チップ毎に設けられているが実
際のマスク合わせでは基板の中心から適当に離れた左右
2ケ所で合わせを行ない、基板全体のバランスを考慮し
ながら基板またはフォトマスクを動かしてマスク合わせ
が行なわれる。フォトマスクと基板が伸び縮みしなけれ
ば第1図(a)の状態を何度でも再現できるわけである
が、フォトマスクと基板との相対関係において、基板の
伸びの方が大きい場合には第1図(b)の状態に、逆の
場合には第1図(C)の状態となることは容易に理解で
きるだろう。一般的に言っても基板は高温工程も含めて
長い工程を経て製作されるので、ある程度の伸び縮みや
反りを避けることはできず、したがって工程管理上フォ
トマスクが伸び縮みしては意味がなくなるので、写真食
刻工程は恒温恒湿のクリーンルームでなされる。
Normally, a suitable margin a is provided so that the key 2 can be stored in the turf 1. In FIG. 1(a), for the sake of simplicity, the key 2 is shown aligned with the center of the pattern 1. Key 2 is provided for each chip, but in actual mask alignment, alignment is performed at two locations on the left and right, appropriately away from the center of the board, and the mask is aligned by moving the board or photomask while taking into account the balance of the entire board. will be carried out. If the photomask and the substrate do not expand or contract, the state shown in Figure 1(a) can be reproduced many times, but if the expansion of the substrate is greater in the relative relationship between the photomask and the substrate, It is easy to understand that the state shown in FIG. 1(b) will be obtained, and in the opposite case, the state shown in FIG. 1(C) will be obtained. Generally speaking, substrates are manufactured through long processes that include high-temperature processes, so it is impossible to avoid some degree of expansion, contraction, and warping, so it would be meaningless if the photomask were to expand or contract in terms of process control. Therefore, the photo-etching process is performed in a clean room with constant temperature and humidity.

次に、合わせ余裕と・ξターン精度との関係について述
べる。第2図では、例えば12μm角のコンタクト4を
パターン3,3′に形成しようとした場合に、第2図(
、)では合わせ余裕が4μmなので・Pターフ3の幅は
20μmにすることができる。第2図(b)では合わせ
余裕が6μmなので・やターン3′の幅は241Rnに
しないとコンタクト4が・eターン;3′からはみ出し
てしまう。即ち同じコンタクト4を形成しようとしても
合わせ精度が低下するとパターン幅は広くしなければな
らない。言い換えると・Pターフ精度が低下して高密度
化が妨げられるのである。
Next, the relationship between alignment margin and ξ turn accuracy will be described. In FIG. 2, for example, when trying to form a 12 μm square contact 4 in patterns 3 and 3',
, ), the alignment margin is 4 μm, so the width of the P turf 3 can be set to 20 μm. In FIG. 2(b), the alignment margin is 6 μm, so unless the width of the turn 3' is 241Rn, the contact 4 will protrude from the turn 3'. That is, even if an attempt is made to form the same contact 4, if the alignment accuracy deteriorates, the pattern width must be increased. In other words, the precision of the P-turf decreases, preventing higher density.

第1図に示したようにフォトマスクと基板との相対的な
伸び縮みは合わせ余裕を低下させる。ところが合わせ余
裕は露光装置の能力、目視で合わせる場合にはオ梨レー
タの習熟度などで決定され、むやみに小さくはできない
。したがって合わせ余裕を維持しようとすると・やター
ン1とキー2との合わせ余裕は、露光装置で決まる合わ
せ余裕と相対的な伸び縮みとの和になり、著しくパター
ン精度の低下をもたらすことになる。
As shown in FIG. 1, the relative expansion and contraction of the photomask and substrate reduces the alignment margin. However, the alignment margin is determined by the ability of the exposure device and, in the case of visual alignment, the skill level of the operator, and cannot be reduced unnecessarily. Therefore, if an attempt is made to maintain the alignment margin, the alignment margin between turn 1 and key 2 will be the sum of the alignment margin determined by the exposure device and the relative expansion/contraction, resulting in a significant drop in pattern accuracy.

ンリコン系のI C、LSIなどの半導体装置は、通常
10角以下のチップとして1枚の基板上に多数同時に形
成される。したがって相対的な伸び縮みの各チップあた
りの平均値は垂直または水平方向に並んだチップ数nの
1/nに低下し、合わせ余裕の低下はnが大きい程小さ
い。ところがn = 1、すなわち1枚の基板全体がチ
ップを構成するような大きな素子、装置では合わせ余裕
の低下は基板の伸び縮みに大きく依存する。このように
大きな素子、装置としては近年開発が盛んな液晶表示装
置がある。単純マトリクス構成の液晶表示装置では、・
やターン幅は最小でも数10μmあるのでほとんど問題
とならないが、アクティブマトリクス構成、即ち絵素毎
にスイッチング素子を内蔵させたものでは、スイッチン
グ素子の特性を良好なものとするためには最小線幅は数
μm以下の値が要求される。
A large number of silicon-based semiconductor devices such as ICs and LSIs are usually formed simultaneously on a single substrate as chips of 10 sides or less. Therefore, the average value of relative expansion/contraction for each chip is reduced to 1/n of the number n of chips arranged in the vertical or horizontal direction, and the larger n is, the smaller the reduction in alignment margin is. However, in the case of a large element or device where n=1, that is, one entire substrate constitutes a chip, the reduction in alignment margin largely depends on the expansion and contraction of the substrate. As such a large element or device, there is a liquid crystal display device, which has been actively developed in recent years. In a liquid crystal display device with a simple matrix configuration,
The minimum line width and turn width are several tens of micrometers, so this is hardly a problem.However, in an active matrix configuration, that is, one in which each picture element has a built-in switching element, the minimum line width is necessary to obtain good characteristics of the switching element. is required to have a value of several μm or less.

しかるに1チツゾあたりの大きさが数儂を超えると基板
の伸び縮みは材質によっては1℃あたり01μmもの熱
膨張を示す物も少なくはない。とくにガラスは軟化点が
数100℃と低く、しかも塑性変形が可逆的でないため
に各種の工程で伸び易く、工程終了後には例えば10c
Inのチソゾが] Ottrn伸びた例がある。このよ
うな条件のもとでは、5μmのパターン精度を有する露
光/ステl、を用いても合わせ精度は10μm必要とな
り、最少線幅は15μmを超える設計基準にならざるを
得ない。1、い換えると、大面積の写真食刻工程ではパ
ターン精度の向上が実現されても合わせ精度の向t−が
図られなければ、高密度化や素子特性向上のための狭パ
ターン化は実現困難であるということである。
However, when the size of one chip exceeds several degrees, the expansion and contraction of the substrate often shows thermal expansion of 0.1 μm per 1° C. depending on the material. In particular, glass has a low softening point of several hundred degrees Celsius, and its plastic deformation is not reversible.
There is an example of In's chisozo] Ottrn being extended. Under such conditions, even if exposure/steeling with a pattern accuracy of 5 .mu.m is used, the alignment accuracy is required to be 10 .mu.m, and the design standard must be such that the minimum line width exceeds 15 .mu.m. 1. In other words, even if pattern accuracy can be improved in the photolithography process for large areas, if alignment accuracy is not improved, narrower patterns for higher density and improved device characteristics will not be realized. This means that it is difficult.

そしてその傾向はチップ面積が大きい程、基板が伸び縮
みし易い程強くなる。
This tendency becomes stronger as the chip area becomes larger and as the substrate expands and contracts more easily.

(発明の目的) 本発明は、かかる状況に鑑みなされたもので、大面積素
子の写真食刻工程において合わせ精度の低下を防止する
露光/ステム、とりわけフォl−マスクを提供すること
を目的とする。
(Objective of the Invention) The present invention was made in view of the above situation, and an object of the present invention is to provide an exposure/stem, particularly a photomask, that prevents a decrease in alignment accuracy in the photolithography process of large-area devices. do.

(発明の構成) 本発明の要点は、フォトマスクと基板との相7]的な伸
び縮みに対してフォトマスクに熱を与えて強制的にフォ
トマスクを伸ばすことにより相対的な差を圧縮せしめん
とするところにある。
(Structure of the Invention) The main point of the present invention is to compress the relative difference between the photomask and the substrate by applying heat to the photomask and forcibly elongating the photomask against the phase 7 expansion and contraction. It's in a place where you can.

(実施例の説明) 第3図は、本発明の一実施例に係るフォトマスクである
。露光に支障をきたさないようにマスク・ぐター76が
存在する領域7を除いた領域、すなわちフォトマスク5
の周辺部に線状またはテープ状のヒータ8を配置せしめ
たものである。9はヒータ8に加熱のための電流を与え
る通電端子である。第3図(b) 、 (c)は、第3
図(、)のh−t(断面を示したものであシ、第3図(
b)では、ヒータが基材であるガラス板5の中に埋めこ
寸れている。あるいはガラス板5の一主面上にヒータ8
を形成した後に樹脂などでコーティングされてもよい。
(Description of Embodiment) FIG. 3 shows a photomask according to an embodiment of the present invention. The area excluding the area 7 where the mask/gutter 76 is present so as not to interfere with exposure, that is, the photomask 5
A linear or tape-shaped heater 8 is arranged around the periphery of the heater. Reference numeral 9 denotes a current-carrying terminal that supplies current to the heater 8 for heating. Figures 3(b) and (c) show the third
h-t (cross-section shown in Figures (,), Figure 3 ()
In b), the heater is completely buried in the glass plate 5 that is the base material. Alternatively, a heater 8 is placed on one main surface of the glass plate 5.
After forming, it may be coated with a resin or the like.

第3図(C)では、ヒータ8が基材のガラス板5の一主
面上に形成されている。通電端子9およびヒータ8はフ
ォトマスク5のどちらの主面上にも形成可能であるが、
投影露光方式でない限りマスクパターン6が形成された
主面は感光性樹脂を塗布された試料と密着または接近す
るので、一般的にはマスク・やターン6が形成されてい
ない主面上に設けることになろう。
In FIG. 3(C), the heater 8 is formed on one main surface of the glass plate 5 as a base material. Although the current-carrying terminal 9 and the heater 8 can be formed on either main surface of the photomask 5,
Unless the projection exposure method is used, the main surface on which the mask pattern 6 is formed will be in close contact with or come close to the sample coated with photosensitive resin, so it is generally provided on the main surface on which the mask pattern 6 is not formed. Would.

第4図及び第5図は、それぞれ本発明の他の実施例に係
るフォトマスクである。この実施例においては透明導電
層10を発熱体として用いるのでマスク・ぞターン6の
配置に関係なくほぼマスク全面にわたって形成でき、先
に述べた実施例と比べて加熱の均一性および速度におい
て著しい改善が得られる。第4図(b)は第4図(a)
のB−ff断面を小したものであり、発熱体である透明
導電層10が基材のガラス板5の中に埋めこまれている
。あるいはガラス板5の一主面上に透明導電層10を形
成した後に樹脂などでコーティングされても構わない。
FIGS. 4 and 5 show photomasks according to other embodiments of the present invention, respectively. In this embodiment, since the transparent conductive layer 10 is used as a heating element, it can be formed over almost the entire mask surface regardless of the arrangement of the mask grooves 6, and the heating uniformity and speed are significantly improved compared to the previously described embodiments. is obtained. Figure 4(b) is Figure 4(a)
The transparent conductive layer 10, which is a heating element, is embedded in the glass plate 5, which is a base material. Alternatively, the transparent conductive layer 10 may be formed on one main surface of the glass plate 5 and then coated with a resin or the like.

透明導電層10が露出されない場合には金属製の通電端
子9が併せて形成される。また、第5図(b)は第5図
(a)のC−C’断面を示したものであり、発熱体であ
る透明導電層10が基拐のガラス板5の一主面上に形成
されているが、先述した理由によりマスクパターン6が
形成されていない主面上に設けると好都合である。透明
導電層10は露出しているので、通電端子10′は・ぐ
ターニングにより簡単に得られ、通電端子10′への電
流供給は適当な金属製の端子の圧着によってなされる。
If the transparent conductive layer 10 is not exposed, a metal current-carrying terminal 9 is also formed. Moreover, FIG. 5(b) shows the CC' cross section of FIG. 5(a), and shows that the transparent conductive layer 10, which is a heating element, is formed on one main surface of the base glass plate 5. However, for the reason mentioned above, it is convenient to provide it on the main surface where the mask pattern 6 is not formed. Since the transparent conductive layer 10 is exposed, the current-carrying terminal 10' can be easily obtained by turning, and current supply to the current-carrying terminal 10' is achieved by crimping a suitable metal terminal.

透明導電層10の配置は、この他にも幾つか考えられる
。例えばn = 2以上の複数形成の場合にはチップと
チップとの隙間であるスクライブグリッドに選択的に配
置するなどである。透明導電層、例えばITO(Ind
ium−Tin、−0xide )やネサがラス(5n
o4)などは紫外線の波長が短くなるほど透過率が低下
するので、スクライブグリッドに配置すると露光時間が
長くなる障害は避けられる。
There are several other possible arrangements for the transparent conductive layer 10. For example, in the case of forming a plurality of chips where n = 2 or more, they may be selectively arranged in a scribe grid that is a gap between chips. A transparent conductive layer, for example ITO (Ind
ium-Tin, -0xide) and Nesa is last (5n
o4) etc., the transmittance decreases as the wavelength of ultraviolet rays becomes shorter, so if they are arranged in a scribe grid, the problem of long exposure time can be avoided.

なお、言うまでもないことだが、フォトマスクの通電に
よる加熱、温度上昇時にはフォトマスクの露光装置内に
おける固定機能を解除して、フォトマスクの伸びを自由
にする必要があり、少なくとも感光性樹脂を塗布された
試料およびそれを支持または固定する試料台まで加熱さ
れることのないように両者を離すとか断熱シールドを施
す必要がある。フォトマスクをマスク合わせに支障をき
たさない程度に強制的に伸ばした後は、もちろんフォト
マスクを固定した状態でマスク合わせを1■なう。
Needless to say, when the photomask is heated due to energization or the temperature rises, it is necessary to release the fixation function of the photomask in the exposure equipment and allow the photomask to stretch freely. To prevent the sample and the sample stage supporting or fixing it from being heated, it is necessary to separate them or provide an insulating shield. After forcibly stretching the photomask to the extent that it does not interfere with mask alignment, of course the mask alignment is performed once while the photomask is fixed.

(発明の効果) 以上の説明からも明らかなように、本発明によるフォト
マスクは、従来とは異なり加熱によりその長さを調整す
る機能が与えられている。したがって大面積の素子−!
、たは装置の製作工程において何らかの原因で伸びが生
じてもマスク合わせが困難もしくは不可能となることは
皆無になり歩留りの向上は著しい。寸た合わせ精度の向
上に伴ない・ξターン精度の低下が阻止されるので、前
記素rまたは装置の高密度化や高性能化も容易となる。
(Effects of the Invention) As is clear from the above description, the photomask according to the present invention has a function of adjusting its length by heating, unlike the conventional photomask. Therefore, a large area element!
Even if elongation occurs for some reason during the manufacturing process of the device, it will never be difficult or impossible to match the mask, and the yield will be significantly improved. As the alignment accuracy is improved, the ξ-turn accuracy is prevented from decreasing, making it easier to increase the density and performance of the element or device.

本発明の適用は必らずしも大面積素子に限られるもので
はなく、通常の集積回路素子にふ・いても合わせ精度の
向上に伴ないチップ間の特性のばらつきが抑制されて歩
留りが向上することは言う壕でもないだろう。
The application of the present invention is not necessarily limited to large-area devices, but can also be applied to ordinary integrated circuit devices, which improves yield by suppressing variations in characteristics between chips as alignment accuracy improves. It's not even a moat to do that.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(C)は、マスク合わせの概念[′ンl
、第′、′!図(a) 、 (b)は、合わせ精度と・
ぞターン精度との関係を示す概念図、第3図は、本発明
の一実施例の構成図であり、第3図(a)は平面図、第
3図(b) 、 (c)は第3図(a)のp、−1断面
図、第4図及び第5図は、それぞれ本発明の他の実施例
の構成図であり、第4図(a)及び第5図(、)は各平
面図、第4図(b)及び第5図(b)は各断面図である
。 5・・フォトマスク、6・・・マスクA’ターン、8・
・・発熱体、9 、10’・・・通電端子、10・・・
透明導電層。 特許出願人 松下電器産業株式会社 第1図 第2図 第3図
Figures 1(a) to (C) illustrate the concept of mask alignment ['nl
,th ′,′! Figures (a) and (b) show alignment accuracy and
FIG. 3 is a conceptual diagram showing the relationship between turn accuracy and FIG. 3 is a configuration diagram of an embodiment of the present invention, FIG. The p, -1 sectional view of FIG. 3(a), FIG. 4, and FIG. 5 are configuration diagrams of other embodiments of the present invention, respectively, and FIG. 4(a) and FIG. Each plan view, FIG. 4(b), and FIG. 5(b) are sectional views. 5...Photomask, 6...Mask A' turn, 8...
... Heating element, 9, 10'... Current-carrying terminal, 10...
Transparent conductive layer. Patent applicant Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] (1)ガラス板または石英板を基材とし、その一主面上
に紫外線を透過させない薄膜パターンが形成されており
、かつ前記薄膜パターンの存在領域外に通電によって発
熱する発熱体が前記基材中に埋めこまれているか、ある
いは前記基材のいずれかの主面上に形成されていること
を特徴とするフォトマスク。
(1) A glass plate or a quartz plate is used as a base material, and a thin film pattern that does not transmit ultraviolet rays is formed on one main surface of the base material, and a heating element that generates heat when energized is located outside the area where the thin film pattern exists, and the base material is a glass plate or a quartz plate. A photomask, characterized in that the photomask is embedded in the substrate or formed on one of the main surfaces of the substrate.
(2)ガラス板または石英板を基材とし、その一主面上
に紫外線を透過させない薄膜パターンが形成されており
、かつ前記薄膜パターンの存在領域を含んで透明導電層
が前記基材中に埋めこまれているか、あるいは前記基材
のいずれかの主面上に形成され、前記透明導電層に通電
端子が設けられていることを特徴とするフォトマスク。
(2) A glass plate or a quartz plate is used as a base material, and a thin film pattern that does not transmit ultraviolet rays is formed on one main surface of the base material, and a transparent conductive layer is formed in the base material including the area where the thin film pattern exists. 1. A photomask, characterized in that the transparent conductive layer is provided with a current-carrying terminal, which is embedded or formed on one of the main surfaces of the base material.
JP59135075A 1984-07-02 1984-07-02 Photomask Pending JPS6115144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59135075A JPS6115144A (en) 1984-07-02 1984-07-02 Photomask

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59135075A JPS6115144A (en) 1984-07-02 1984-07-02 Photomask

Publications (1)

Publication Number Publication Date
JPS6115144A true JPS6115144A (en) 1986-01-23

Family

ID=15143255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59135075A Pending JPS6115144A (en) 1984-07-02 1984-07-02 Photomask

Country Status (1)

Country Link
JP (1) JPS6115144A (en)

Similar Documents

Publication Publication Date Title
US6348301B1 (en) Method of reducing a critical dimension of a patterned photoresist layer
TW447147B (en) Exposure apparatus and method for forming thin film transistor
KR0158779B1 (en) Process for exactly patterning layer to target configuration by using photo-resist mask formed with dummy pattern
KR970067914A (en) Electronic device manufacturing method
KR20040007622A (en) Temperature-controlled chuck and method for controlling the temperature of a substantially flat object
GB2196476A (en) A method for manufacturing a component and a component produced by the method
JP4308407B2 (en) Manufacturing method of semiconductor device
KR20020082580A (en) Plasma etching chamber and method for manufacturing photomask using the same
KR940001258A (en) Method of manufacturing polycrystalline silicon thin film
JPH05326900A (en) Solid-state image-sensing device and manufacture thereof
JPS6115144A (en) Photomask
KR100355231B1 (en) Photomask for fabricating opening of semiconductor memory device, photolithographic method using the same, and semiconductor memory device fabricated by the same method
TW201110194A (en) Semiconductor manufacturing process and apparatus for the same
JP2002151381A (en) Method for forming pattern
US6432207B1 (en) Method and structure for baking a wafer
US6483068B2 (en) Apparatus for hard baking photoresist pattern
JP2000314894A (en) Device structure for liquid crystal display equipped with alignment post and optical interference layer, and its production
TWI238456B (en) Composite layer method for minimizing PED effect
US4557986A (en) High resolution lithographic process
JPS6115146A (en) Exposing device
KR950005263B1 (en) Fine pattern forming method of semiconductor device
KR970063578A (en) Manufacturing method of wiring
JP2854921B2 (en) Method for manufacturing semiconductor device
TW577110B (en) Method for forming photoresist pattern
JP2002099006A (en) Integrated thermo-optical silica switch