JPS61150516A - Delaying device - Google Patents

Abstract

PURPOSE:To delay an input pulse train by a desired time by applying a reference clock to a clock pulse train PC which is frequency-divided into 1/N, and using a reference clock pulse train PF, too. CONSTITUTION:When the first pulse of a 1/N frequency-divided pulse train PC is inputted, the output S1 of an OR gate 85 is changed to '1' by an up-down counter 87. Also, a preset counter 89 starts to count a reference pulse train PF, and when it reaches the set value of a preset register 90, a pulse S3 is sent as a set input to an FF82. Therefore, a 1/N decade counter 81 generates an output pulse PD, whenever the PF is counted by N pieces. On the other hand, the counter 87 executes the counting at every PC and PD, and when the count value becomes '0', a pulse is outputted from a one shot timer 88, the FF82, etc. are reset, and the output PD is stopped. As a result, at the time of a start, the pulse PC is outputted by being delayed by a portion added with the time TD and the pulse width of the pulse PC, and after the stop command of a process control is given, the pulse PC is outputted during said delay time. In such a way, the optional delay of plural multiple of the pulse interval of the PF can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a clock pulse train delay device, and particularly to a process control device that controls a plurality of control target value patterns using a preprogram control method. The present invention relates to a clock pulse train delay device used to delay a clock signal by an arbitrary amount of time longer than the output clock cycle.

[Technical background of the invention and its problems]

For process control devices that need to control the control targets of multiple controlled devices in synchronization, such as control devices for magnet and power sources of accelerators, the control target value pattern for each controlled device must be calculated in advance by a computer. A preprogram control method is used in which the control target value is calculated and transferred to each storage device, and during process control, the control target value is read out from the storage device in synchronization with the black and white signals to control the controlled device.

FIG. 6 shows a block diagram of a pre-program control type control device.

In the figure, 71 (i=a, . . . + n ) is a controlled device such as a magnet power supply, and 21 (1=l
r ''' r n ) is each controlled device 1s (t=a, ・
. . . , n), storage devices 31 (i=a r .
1 (1=a, . . . r n ), and 4 is an address counter that specifies the address when writing and reading the corresponding storage device 21. 4 is an address counter 31 (1=a, . . . r n ).
a, .
=a,...r n ) settings, storage device 2S (t=a
.

In such a configuration, the controlled device 11 (1=a,
. . , n), first calculate the mother turn of the control target value using the computer 5, and send this data via the data bus 6 to the address color 7p-3i (1=a, . . .
・, n) address counter and storage device 2i (1=a
,...+1).

Next, the address counter 31 (i=a,・
...on), and set the initial value of clock pulse generator 4.
A START signal instructing generation of a clock pulse train is input to the clock pulse train. The clock pulse train sent from the clock pulse generator 4 causes the address counter ji (1=a
,...In) are counted and f at regular intervals, and are stored in the storage device ji (1=a.

. . . , n) Controlled device Ji (1=a.

..., n) Output K. To end the operation, input the 5TOP signal to Kuro, Kunoyarusu generator 4,
Stops Kutsugurusu train from occurring.

By the way, in the above-mentioned process control device using the solenoid control method, when the loads of each controlled device Ji (1=a,...,n) are significantly different, such as the magnet power supply of an accelerator, the control The delay time of the actual control amount (for example, the current flowing in a magnet) relative to the target value is determined by the delay time of each controlled device Ji (i=a,...+n
) different situations arise.

Therefore, each controlled device Ji (1=a, . . . ).

In process control equipment where synchronization of n) is strictly required,
Correction of delay time is required. In other words, the controlled device [1
1 (i=a+...+n), the control target value of the other controlled devices 15 is delayed so that it can be synchronized with the actual control amount of the controlled device with the longest delay time. Perform the processing to

Therefore, conventionally, the computer 5 calculates the control target value and the arm turn by taking this delay time into consideration in advance, and the storage device 21 (
t=a,...,n) and was driving. However, with this method, when recompensing the delay time,
Since it is necessary to recalculate and transfer the control target value gloss turn of the controlled device 11 (1; 1. . . r n ),
There was a problem that the operating efficiency decreased. In order to improve this, as shown in FIG. 7, a clock/-P pulse generator 4 and an address counter Ji (1=a, . . .

A method has also been proposed in which the delay time is corrected by inserting the delay time (n).

However, conventional delay devices are unsuitable as clock pulse train delay devices used in the above-mentioned applications. This is due to the following reason.

FIG. 8 shows a conventional delay device 71 (i=a.

..., n) input 1? Shows the relationship between Rusu and Dekakkarusu.

As shown in FIG. 8(&), the input pulse f of the delay device 71 is
: Pls, and if the output pulse is potrte, then in the conventional delay device 71, if the interval T between the input black and shoe strings is small compared to the delay time To, then as shown in FIG. 8(b)
As shown in the figure, once the black, ri/ll soot is in the
When input as IN, delay time TD elapses and pouT
Until the clock pulse is output, either the hexagonal pulse PIN is ignored, or the counter that counts the elapsed time is cleared each time the clock pulse is input, as shown in FIG. 8(c). Either the last pulse of the incoming pulse train was input and the pulse was output after the delay time TD had elapsed.

In other words, in the former case, the clock pulses are not delayed by the delay time Tn, but are thinned out so that 1/# pulses are generated every time TD passes, and in the latter case, the clock pulses are thinned out so that 1/# pulses are generated every time TD passes. After the first operation and 'rn time, output one output Nors POUT,
This causes the operation to stop the output, and this cannot be used for process control.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to provide a delay device that can delay an input/four pulse train by a desired time and output it. be.

[Summary of the invention]

That is, in order to achieve the above object, the present invention provides pulse generation means for generating and outputting a reference clock pulse, dividing the frequency of this reference clock pulse by a predetermined value, and outputting the same, and the pulse generation means provided by the pulse generation means. a frequency divider that divides a reference clock pulse by a predetermined frequency to generate an output/4'pulse; a delay time generator that counts the reference clock pulse and generates an output when a preset desired count value is reached; Frequency division control means operates the frequency division means by the output of the delay time generation means and stops the frequency division by a reset signal; It consists of an up/down counter that counts down in response to an output signal from the noise generating means, and a reset means that generates a reset output when the count value of the up/down counter returns to zero.・A/Rus is generated and outputted, and this reference clock A/Rus is divided by a predetermined frequency and outputted, and this l? The reference clock pulses given by the delay time generating means are counted by the delay time generating means to obtain a preset delay time, and the frequency dividing means is activated when the delay time obtained by the delay time generating means has elapsed; , causing an up/down counter to count up using the divided output of the pulse generating means;
By down-counting the output/4 pulses of the frequency dividing means, the number of pulses of the divided output of the pulse generation means generated during the delay time elapsed period is held, and after the divided output is stopped. Holding the above, the frequency dividing means outputs pulses equivalent to 41 pulses, and then the frequency division is stopped, so that the divided output of the pulse generating means can be output after a desired time delay. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

FIG. 2 is a block diagram showing an example of a process control device configured using the device of the present invention.
n is a controlled device, 2a to 2n are storage devices, 31. ~3
n is an address counter, and 5 is a computer, which have the same structure and function as those explained in FIG.

4A is a clock pulse generator, 81. ~8n is a delay device according to the invention.

The clock pulse generator 4A includes a reference clock generator 9 that generates a reference pulse train, and a 1/N decade counter 1o that also divides the output pulse train of the reference clock generator 9 into 1/2 and outputs it.

A flip-flop 11 is set by a start signal 5TART applied from the outside and reset by a stop signal 5TOP applied from the outside; ) consists of 12, ANDI'
- The pulse train PF output from the pulse generator 9 is outputted to the 1/N divided frequency of the 1/N decade counter 1'0 outputted through the gate 12.

The delay devices 8m, to 8n of the present invention have a configuration as shown in FIG.
After delaying the N-divided pulse PC by a desired delay time, the 1/N-divided pulse PC (=PD) can be output for a predetermined number of minutes.

The difference between the delay devices 8m and 8n of the present invention from the conventional delay devices 17a and 7n is that the output of the reference clock generator 9 is divided into a clock/pulse train pc by the 1/N decade counter 10. In addition, the output pulse train P of the basic clock generator 9 is also used.

The frequency of py is typically on the order of I MHz,
If a decade counter with a frequency divided by 1/10' is used as the 1 day decade counter 10, a 100 Hz preprogram control clock pulse train PD can be obtained.

Details of the delay devices 8a to 8n will be explained with reference to FIG. In the figure, 81 is a 1/N decade counter that divides the pulse train S5 by 1/N and outputs it as the pulse train PD, and 82 is set by the pulse signal S6 and outputs the pulse train S5 as the pulse train PD.
Flip 70 is reset at 3, F1a, 84 is AND dart, and 85°86 is 0Rf-to. 87 is refrequented by inputting the initialization signal INZ to the CLEAR terminal, and the 1//N frequency output from the clock pulse generator 4A is counted up and 1/N by inputting it to the terminal UP of the clock pulse generator 4A. The up/down counter 88 counts down by inputting the pulse train PD output from the decade counter 8) to the terminal DOWN, and the OR? - a one-shot timer which receives the output of the up-down counter 87 via the gate 115 and operates at its negative edge to generate a pulse with a predetermined pulse width; 89 is the initialization signal INZ or the output of the one-shot timer 88; OR? ” - is shifted by the falsification signal S6 obtained by passing through the pulse 8g, and the value to be set in the preset register 90 that holds the preset value is preset, and the input/J pulse train 2 is counted by the preset value. A preset counter 91 outputs the /9 pulse signal S3, and is a N0Tf-) that inverts and outputs the negative output (i output when set) of the free lag flop 82.

Note that the ANDf-) 84 performs an AND logic of the output S1 of the 0Rf-) 85, the output of the NOT l''-) 9J, and the output pulse train pr of the clock pulse generator 4A to output an output S2, and outputs an output S2. It is given as an input sequence S2.

Next, the operation of this apparatus having the above configuration will be explained. In this device, the oscillation of the reference clock generator 9 generates a pulse train PF at a predetermined clock rate as shown in FIG.
, ~8n.

Furthermore, when the start signal 5TART is applied to start up the process control device, the flip-flop fil of the clock pulse generator 4A is set, thereby AND'
l'-) 12 is opened. On the other hand, the pulse train PF generated by the reference clock generator 81 is input to the 1/'N decade counter 1θ, and is frequency-divided by 1/N to ANDr-
Since this ANDe-) IF is opened, the clock pulse generator passes through this AND 4A, and the delay devices 8a, . . .
8nK is given.

In the delay devices 8a to 8n, these given Pc, P
Of F, iJ? The loop sequence P is ANDf-to83°84
Furthermore, the 1/N frequency-divided pulse PC is input to the up-count input terminal UP of the up-down counter 87.

Here, in the delay devices 8a to 8n, the initialization signal INZ is inputted to the up/down counter 87 before inputting the 1/N frequency dividing signal pc.
7, Free, Zoflop 82, Preset counter 89.
It is assumed that the 1/N decade counter 81 is cleared.

In addition, the preset register 9o has M = (To Tc) / Tr ・−・(
1) Set a value M defined as 1.

Here, TD is the delay from when the input Norse sequence Pc is input to when the output Noculus sequence PD (the output pulse of the 1/N decade counter 81 becomes the output pulse of the delay device Fj a , ~8n) is output. The time Tc is the Noculus interval of the input pulse train PC or the output pulse train PD, and Tr is the Noculus interval of the pulse train PF, which is a reference clock.

As shown in FIG. 3, when the first pulse of the input/4' pulse train pc from the four clock pulse generators is input to the delay devices 8a to 8n, the count value of the up/down counter 87 changes from "0" to "11". OH that receives the output
The output S1 of the 2''-gate 115 also changes to ``1''.Furthermore, the free lug float 82 is in the reset state and the i output is ``O'', and the output of the N0TI''-gate 91 that inverts this is 11.
'', and the AND gate 84 passes the input pulse train Py, so the preset counter 89 that receives this starts counting the pulse train PF, which is the reference clock signal. Since the set value M of the grisset register 90 has been preset, as a result, when the count value of the preset counter 89 reaches M, the grisset counter 89 becomes free and f
A pulse S3't is sent to the flop 82 as a set input. Therefore, the flip-flop 82 is set and its silkworm output becomes "1", which is output as the signal S4 to AN.
D f -t 8 J is given, and AN'Dr -t 83 is opened. Therefore, since the pulse train PF is inputted to the 1 day cade counter 81 through the ANDr gate 83, from now on, the 1 day cade counter 81 is inputted to the PF
f: Generates an output Noculus PD every time N counts, that is, every time TC elapses.

On the other hand, the up/down counter 87 has a frequency divided by 1
It counts up every time PD is input, and counts down every time an output pulse PD is output. Therefore, when the stop signal 5TOP is applied to the clock pulse generator 4A to stop the output of the 1/N frequency/# pulse train Pc in order to stop process control, the up/down counter 87 enters a state where it only counts down.

And the count value of up/down counter 87 is @0”
Then, the output of the 0Rr-t 85 becomes 10'', so the negative edge one-shot timer 88, which operates at the fall of the output, outputs a pulse.

This pulse is 0R)I'h-M? 6 and is outputted as a signal S6, and this signal S6 resets the floating flag 82, and also resets the 1/N decade counter 81 and reset color counter 89, returning to the initial state. And this flip-flop 82
By resetting A, its mutual output becomes “0”, so A
The NDR gate 83 is closed, and therefore the output pulse train pn of the 1/N decade counter 81 is stopped.

As a result, at startup, the pulse train PF is divided by 1, and the pulse train is delayed by the time TD determined by the preset value of the reset counter 89 and the pulse width of the 1-pulse, f, - before being output. However, when stopping process control, a pulse whose frequency is divided by 1/N is output from when the stop command is given until the above delay time elapses, and then...
Stop output of Heirusu.

Also, using the preset counter 89, the Noculus column PF
Since the target delay time is obtained by counting up to the preset value, it is possible to make an arbitrary delay that is multiple times the arm interval of the input clock pulse train PF.
Moreover, the delay time and the interval of the output pulse train can be set with the time precision of the base clock PF.

Therefore, the output pulses PD of the delay devices 8a to 8n
are given to the corresponding address counters 3&, ~JnK to advance the address, and control is performed by reading out the control target turn from the storage devices 2m and ~2n, so that reliable control can be performed according to the controlled device with the largest delay time. become.

Incidentally, in the above embodiment, the value M defined by equation (1) is set in the reset register 90 in order to obtain the desired delay time, but in order to make the setting easier to understand, M' ” TD /TF ・・・・・・(2
) It is also possible to obtain the target delay time by setting the value V defined by . An example in this case is shown in FIG. 4, and an operation timing chart thereof is shown in FIG.

The fourth configuration is such that the output S3 of the preset counter 89 can also be used for down-counting the up/down counter 87.
This allows the pulse output from the preset counter 89 to be the first pulse of the output pulse train, and therefore the 1/N frequency division pulse of the preset counter 89. Since there is no need to consider the time delay of the width numerator c, the output/4' pulse sequence P starts from the point when the count value reaches M'.
You can start outputting D.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to output the necessary number of pulse trains delayed by the desired delay time, and the delay time of the pulse trains can be determined by using the reference clock, the 41 pulse train, and the frequency dividing circuit output. The resulting pulse interval is not fixed, and any delay can be set simply by changing the gliset value.The delay time and the interval between the output and pulse train can also be set with the time precision of the reference clock.As a result, multiple units can be used. It is possible to provide a delay device having characteristics such as being able to perform synchronous control of controlled devices with high accuracy.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a modification of the process control device to which the device shown in FIG. 1 is applied, and FIG. FIG. 8, a block diagram showing an example, is a diagram for explaining a conventional delay device. 4A...Clock pulse generator, 8&, ~8n...
Delay device, 9... Reference clock generator, 10°81.
...1/N decade counter, 11,112...7
1J f71=t Tsubu, 12, 113, I
I 4 ・AND f-to, 85, 86.92...O
R dirt, 81...up/down counter, 88...
・One-shot timer, 89...Preset counter, 90...Preset register, 91...NOT
? -t. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] pulse generating means for generating and outputting a reference clock pulse, and dividing the frequency of this reference clock pulse by a predetermined frequency and outputting the same; a frequency dividing means; a delay time generating means for counting the reference clock pulses and generating an output when a preset desired count value is reached; the output of the delay time generating means activates the frequency dividing means and a reset signal; a frequency division control means for stopping frequency division by a frequency division control means; an up-down counter for up-counting upon receiving the frequency-divided output of the pulse generating means; and an up-down counter for up-counting upon receiving the output pulse of the frequency dividing means; A delay device comprising: reset means for generating a reset output when a count value returns to zero.