JPS61147551U - - Google Patents
Info
- Publication number
- JPS61147551U JPS61147551U JP2904285U JP2904285U JPS61147551U JP S61147551 U JPS61147551 U JP S61147551U JP 2904285 U JP2904285 U JP 2904285U JP 2904285 U JP2904285 U JP 2904285U JP S61147551 U JPS61147551 U JP S61147551U
- Authority
- JP
- Japan
- Prior art keywords
- bus voltage
- charging current
- section
- charging
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2904285U JPS61147551U (enrdf_load_html_response) | 1985-02-28 | 1985-02-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2904285U JPS61147551U (enrdf_load_html_response) | 1985-02-28 | 1985-02-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61147551U true JPS61147551U (enrdf_load_html_response) | 1986-09-11 |
Family
ID=30527492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2904285U Pending JPS61147551U (enrdf_load_html_response) | 1985-02-28 | 1985-02-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61147551U (enrdf_load_html_response) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6893916B2 (en) | 2001-06-15 | 2005-05-17 | Hrl Laboratories, Llc | Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same |
| US6897535B2 (en) | 2002-05-14 | 2005-05-24 | Hrl Laboratories, Llc | Integrated circuit with reverse engineering protection |
| US6919600B2 (en) | 2001-06-15 | 2005-07-19 | Hrl Laboratories, Llc | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact |
| US6979606B2 (en) | 2002-11-22 | 2005-12-27 | Hrl Laboratories, Llc | Use of silicon block process step to camouflage a false transistor |
| US7166515B2 (en) | 2000-10-25 | 2007-01-23 | Hrl Laboratories, Llc | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering |
| US7217977B2 (en) | 2004-04-19 | 2007-05-15 | Hrl Laboratories, Llc | Covert transformation of transistor properties as a circuit protection method |
| US7242063B1 (en) | 2004-06-29 | 2007-07-10 | Hrl Laboratories, Llc | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable |
| US7294935B2 (en) | 2001-01-24 | 2007-11-13 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide |
| US7514755B2 (en) | 2002-12-13 | 2009-04-07 | Hrl Laboratories Llc | Integrated circuit modification using well implants |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6130925A (ja) * | 1984-07-19 | 1986-02-13 | ヤマハ発動機株式会社 | 太陽電池を電源とする充電装置 |
-
1985
- 1985-02-28 JP JP2904285U patent/JPS61147551U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6130925A (ja) * | 1984-07-19 | 1986-02-13 | ヤマハ発動機株式会社 | 太陽電池を電源とする充電装置 |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7166515B2 (en) | 2000-10-25 | 2007-01-23 | Hrl Laboratories, Llc | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering |
| US7294935B2 (en) | 2001-01-24 | 2007-11-13 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide |
| US6893916B2 (en) | 2001-06-15 | 2005-05-17 | Hrl Laboratories, Llc | Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same |
| US6919600B2 (en) | 2001-06-15 | 2005-07-19 | Hrl Laboratories, Llc | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact |
| US6897535B2 (en) | 2002-05-14 | 2005-05-24 | Hrl Laboratories, Llc | Integrated circuit with reverse engineering protection |
| US7008873B2 (en) | 2002-05-14 | 2006-03-07 | Hrl Laboratories, Llc | Integrated circuit with reverse engineering protection |
| US6979606B2 (en) | 2002-11-22 | 2005-12-27 | Hrl Laboratories, Llc | Use of silicon block process step to camouflage a false transistor |
| US7344932B2 (en) | 2002-11-22 | 2008-03-18 | Hrl Laboratories, Llc | Use of silicon block process step to camouflage a false transistor |
| US7514755B2 (en) | 2002-12-13 | 2009-04-07 | Hrl Laboratories Llc | Integrated circuit modification using well implants |
| US7217977B2 (en) | 2004-04-19 | 2007-05-15 | Hrl Laboratories, Llc | Covert transformation of transistor properties as a circuit protection method |
| US7541266B2 (en) | 2004-04-19 | 2009-06-02 | Hrl Laboratories, Llc | Covert transformation of transistor properties as a circuit protection method |
| US7242063B1 (en) | 2004-06-29 | 2007-07-10 | Hrl Laboratories, Llc | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable |