JPS61147317A - Reference voltage generating circuit - Google Patents

Reference voltage generating circuit

Info

Publication number
JPS61147317A
JPS61147317A JP26746284A JP26746284A JPS61147317A JP S61147317 A JPS61147317 A JP S61147317A JP 26746284 A JP26746284 A JP 26746284A JP 26746284 A JP26746284 A JP 26746284A JP S61147317 A JPS61147317 A JP S61147317A
Authority
JP
Japan
Prior art keywords
reference voltage
transistor
resistor
base
voltage generation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26746284A
Other languages
Japanese (ja)
Other versions
JPH0560128B2 (en
Inventor
Akihiko Ono
彰彦 尾野
Yoshiaki Sano
芳昭 佐野
Chikara Tsuchiya
主税 土屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP26746284A priority Critical patent/JPS61147317A/en
Publication of JPS61147317A publication Critical patent/JPS61147317A/en
Publication of JPH0560128B2 publication Critical patent/JPH0560128B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

PURPOSE:To decrease the temperature dependancy by using two transistors (TRs) whose collectors are connected to a common connecting point between a reference voltage generating terminal and a constant current source via a resistor. CONSTITUTION:An emitter of a TRQ7 acting like a constant current source is connected to a reference voltage terminal Vref, and collectors of the TRs Q3, Q4 are connected to the common connecting point via the resistors R1, R2 respectively. Bases of both the TRs are connected across a resistor R4, a base VB1 of the TRQ3 is connected to the reference voltage terminal Vref via a resistor R3 and a base VB2 of the TRQ4 is connected to common via a resistor R5 and a TRQ5. Since both the base voltages VB1, VB2 depend on a reciprocal of the voltage gain of the TRs Q3, Q4, even when collector voltages VC1, VC2 are fluctuated, the effect is very less.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路に関し、特にアナログtC回路
における定電圧源等に用いる基準電圧発生回路に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a reference voltage generation circuit used as a constant voltage source in an analog tC circuit.

〔従来の技術〕[Conventional technology]

既に知られるように基準電圧発生回路はアバランシェブ
レークダウンダイオードを用いる方法と、半導体内のエ
ネルギーバンドを利用したバンドギヤ・Xプリファレン
スによる方法とに大別される。
As is already known, reference voltage generation circuits are broadly divided into methods using an avalanche breakdown diode and methods using a band gear/X preference using an energy band within a semiconductor.

いずれも目的は発生基準電圧の温度依存性を改善するも
のであるが、ここでは後者による方法を用いた基準電圧
発生回路について第3図を参照しつつ概説する。第3図
回路は基本的にはトランジスタのベース・エミッタ間の
エネルギーバンドを利用した基準電圧発生回路であって
、発生される基準電圧Vrefは次の関係式で表わせる
。すなわち、Vref = (R3+Ra +Rs )
  ’  (Va+  Vsz)“ /Ra+Vmt。
The purpose of both methods is to improve the temperature dependence of the generated reference voltage, but here a reference voltage generating circuit using the latter method will be outlined with reference to FIG. The circuit shown in FIG. 3 is basically a reference voltage generating circuit that utilizes the energy band between the base and emitter of a transistor, and the generated reference voltage Vref can be expressed by the following relational expression. That is, Vref = (R3+Ra +Rs)
' (Va+Vsz)“ /Ra+Vmt.

   −−−−−−・・−一−−−−−−−・・ (1
1=(R,I +Ra +、−,Rs )’ VT  
’ ln  (N)/Ra+Vmt。、−・−−一−−
・−・−−−(2)ここで、V□、■、2はそれぞれト
ランジスタQ31Q4のベース電位、vllEoはトラ
ンジスタQ、のベース・エミッタ間電位、VTはkT/
qで示される定数でkはボルツマン定数、Tは絶対温度
、qは電荷、そしてin’ (N)はトランジスタQ3
 。
−−−−−−・・−1−−−−−−−・・ (1
1 = (R, I + Ra +, -, Rs)' VT
' ln (N)/Ra+Vmt. , −・−−1−−
・-・---(2) Here, V□, ■, 2 are the base potentials of transistors Q31Q4, vllEo is the base-emitter potential of transistor Q, and VT is kT/
In the constant denoted by q, k is the Boltzmann constant, T is the absolute temperature, q is the electric charge, and in' (N) is the transistor Q3.
.

Q4のエミッタ比Nにおける自然対数である。It is the natural logarithm of the emitter ratio N of Q4.

トランジスタQsのVIEはベース・エミッタ接合によ
る負の温度係数を有し、一方、各抵抗R3+Ra、Rs
は正の温度係数を有し、さらにv7も温度依存性を有し
ている。従って基準電圧Vrefは上式+11 、 (
2)中の各抵抗およびトランジスタQ3゜Q4のエミッ
タ比を適切に選択することによって温度補償を行ってい
る。この場合、トランジスタQ、、Q、と抵抗R+、R
zによって定電流回路を構成しており、R,=RZであ
り、ここを流れる電流11.1□はカレントミラー構成
となっているので整合している時にはI、=lzである
The VIE of transistor Qs has a negative temperature coefficient due to the base-emitter junction, while each resistor R3+Ra, Rs
has a positive temperature coefficient, and v7 also has temperature dependence. Therefore, the reference voltage Vref is calculated using the above formula +11, (
2) Temperature compensation is performed by appropriately selecting each resistor and the emitter ratio of transistors Q3 and Q4. In this case, transistors Q, ,Q, and resistors R+, R
A constant current circuit is formed by z, and R,=RZ, and the current 11.1□ flowing therein has a current mirror configuration, so when matching is achieved, I,=lz.

またエミッタ比とはトランジスタのエミツタ面積比であ
るが、等価的にトランジスタを並列に並べた使用個数比
と置換えることができる。
Further, the emitter ratio is the emitter area ratio of a transistor, but it can be equivalently replaced with the ratio of the number of transistors arranged in parallel.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記の構成にあっては、トランジスタQ+、Qzによる
定電流源によってトランジスタQ3  、 Qaに等し
い電流を供給しているが、何らかの要因によって定電流
源の整合性がずれた場合、即ち、1、#I、の場合には
、Q3 、Q4に供給する電流値の変化が各々のベース
電位V□+VlKの変化となって表われ、基準電圧Vr
efに変動を生ずる。
In the above configuration, the constant current sources formed by transistors Q+ and Qz supply equal current to transistors Q3 and Qa. However, if the consistency of the constant current sources deviates due to some factor, In the case of I, a change in the current value supplied to Q3 and Q4 appears as a change in the base potential V□+VlK, and the reference voltage Vr
This causes fluctuations in ef.

この場合、不整合を生ずる要因は、回路を構成する素子
自体に存在し、IC化した場合にPNP トランジスタ
はNPN)ランジスタに比べて特性バラツキが大、パタ
ーン設計上で配線の長さによる特性バラツキ、製造プロ
セス上のバラツキ等が考えられ、これらによって定電流
回路に不整合を生じ、基準電圧Vrefに変動を来して
いる。
In this case, the factors that cause mismatch exist in the elements themselves that make up the circuit, and when integrated into an IC, there are large variations in characteristics compared to PNP (NPN) transistors, and variations in characteristics due to wiring length in pattern design. , variations in the manufacturing process, etc. are considered, which cause mismatch in the constant current circuit and cause fluctuations in the reference voltage Vref.

〔問題点を解決するための手段および作用〕本発明は上
記の問題点を解消した基準電圧発生回路を提供すること
にあり、その手段は、第1の抵抗を介してコレクタが基
準電圧発生端子と定電流源との共通接点に接続されベー
スが第3の抵抗を介して該基準電圧発生端子に接続され
る第1のトランジスタと、第2の抵抗を介してコレクタ
が該共通接点に接続されベースが該第3の抵抗および第
4の抵抗を介して該基準電圧発生端子に接続される第2
のトランジスタと、該第2のトランジスタのベースと該
第4の抵抗との共通接点に第5の抵抗を介してコレクタ
が接続されエミッタが接地される第3のトランジスタを
具備し、該第1のトランジスタのベース電位と該第2の
トランジスタのベース電位を該第1のトランジスタおよ
び第2のトランジスタの電圧利得の逆数によって設定さ
れるようにしたことを特徴とする。
[Means and effects for solving the problems] The present invention provides a reference voltage generation circuit that solves the above problems, and the means is to connect the collector to the reference voltage generation terminal via a first resistor. and a constant current source, a first transistor having a base connected to the reference voltage generation terminal via a third resistor, and a collector connected to the common contact via a second resistor. a second resistor whose base is connected to the reference voltage generation terminal via the third resistor and the fourth resistor;
a third transistor whose collector is connected to a common contact between the base of the second transistor and the fourth resistor via a fifth resistor and whose emitter is grounded; The base potential of the transistor and the base potential of the second transistor are set by reciprocals of the voltage gains of the first transistor and the second transistor.

〔実施例〕〔Example〕

第1図は本発明に係る基準電圧発生回路の一実施例回路
図である。第1図から明らかなように、従来の定電流源
を構成していたトランジスタQllQz、トランジスタ
Q8、トランジスタQ、は除去され、代わりに第1のト
ランジスタとしてのトランジスタQ、のコレクタと抵抗
R,とトランジスタQ6のヘース、および第2のトラン
ジスタとしてのトランジスタQ4のコレクタと抵抗R2
とトランジスタQ1゜のベースとが接続される。また抵
抗R+=Rzとし、基準電圧Vrefは基準電圧発生端
子Vref  (便宜上同一参照記号とする)から発生
され、第3のトランジスタとしてのトランジスタQsお
よび第3.第4.第5の抵抗R13゜Ra  、、Rs
は従来通りである。
FIG. 1 is a circuit diagram of an embodiment of a reference voltage generating circuit according to the present invention. As is clear from FIG. 1, the transistor QllQz, transistor Q8, and transistor Q, which constitute the conventional constant current source, are removed, and the collector of the transistor Q as the first transistor, the resistor R, and the The base of transistor Q6 and the collector of transistor Q4 as the second transistor and resistor R2
and the base of transistor Q1° are connected. Further, the resistor R+=Rz, the reference voltage Vref is generated from the reference voltage generation terminal Vref (same reference symbol for convenience), and the transistor Qs as the third transistor and the third . 4th. Fifth resistor R13゜Ra,,Rs
is the same as before.

このような構成において、トランジスタQ3 。In such a configuration, transistor Q3.

Q4のコレクタ電位を各々VC1+ VC2とし、第1
および第2の抵抗R+、Rtを流れる電流を各々It、
Igとすると、トランジスタq、、Q4の増幅作用によ
って各々の電圧利得A@1.A(14は次の如く表わせ
る。すなわち、 A@3=△V c + /△V m + = R+ /
 T el  −−−−(3)A、4=△V cz/△
V tz = Rz / r e2 −−− (4)こ
こで、Tel、re2は各々トランジスタQ3  、 
Qsのエミッタ抵抗であって、rel=V? /I I
 。
The collector potential of Q4 is set to VC1+VC2, respectively, and the first
and the currents flowing through the second resistors R+ and Rt, respectively.
Ig, each voltage gain A@1. A (14 can be expressed as follows. That is, A@3=△V c + /△V m + = R+ /
T el -----(3) A, 4=△V cz/△
V tz = Rz / r e2 --- (4) Here, Tel and re2 are the transistor Q3,
Qs emitter resistance, rel=V? /I I
.

re2=Vy /Igである。re2=Vy/Ig.

式(3) 、 (4)から明らかなように、トランジス
タQ3 、Qaのベース電位V Ill * v@2は
各h VCI 。
As is clear from equations (3) and (4), the base potentials V Ill * v@2 of transistors Q3 and Qa are h VCI .

VBの1/A93.1/A(14である。従って前述し
たように何らかの要因によって電流I、≠■2が生じて
もVIII、■、に与える誤差は上述の如く各々(1/
AO3)倍および(1/A114)倍となり極めて影響
の小さいことが解かる。基準電圧V refは式(11
で示したように■□、v0の値に大きく依存するが、こ
のような回路構成とすることにより、r、、■、の変動
に対してVII + vmzの影響を極めて小さくする
ことが出来、その結果基準電圧Vrefを安定化させる
ことが出来る。尚、第3図の従来の回路ではトランジス
タQ3.Q4に増幅作用がないためにI+、Itの変動
が直接V、1゜■、!に表われ基準電圧Vrefの変動
を来している。
1/A of VB is 93.1/A (14). Therefore, even if the current I,≠■2 occurs due to some factor as mentioned above, the error given to VIII,
It can be seen that the influence is extremely small, which is AO3) times and (1/A114) times. The reference voltage V ref is calculated using the formula (11
As shown in , ■□ greatly depends on the value of v0, but by using such a circuit configuration, the influence of VII + vmz on the fluctuation of r, ,■ can be made extremely small, As a result, the reference voltage Vref can be stabilized. In the conventional circuit shown in FIG. 3, transistor Q3. Since Q4 has no amplification effect, the fluctuation of I+, It is directly caused by V, 1°■,! This appears, causing fluctuations in the reference voltage Vref.

本発明ではトランジスタQ3  、 Qaの利得のより
大きいもの、あるいは抵抗R+、Rtの値より大きいも
のを使用すれば、当然V□、V、tの変動を、より小さ
く押えることができる。尚、トランジスタQ、、Jは電
源Vccを定電流化する定電流源である。
In the present invention, if the transistors Q3 and Qa have larger gains or the values of the resistors R+ and Rt are used, fluctuations in V□, V, and t can be suppressed to a smaller value. Note that the transistors Q, , J are constant current sources that make the power supply Vcc a constant current.

第2図は本発明に係る基準電圧発生回路の他の実施例回
路図である。この回路では回路構成上電源端子Vccを
持たず、外部抵抗Rによって電源から電流の供給を受け
るものである。この場合にはトランジスタQs  、 
QlおよびトランジスタQ1゜。
FIG. 2 is a circuit diagram of another embodiment of the reference voltage generating circuit according to the present invention. This circuit does not have a power supply terminal Vcc due to its circuit configuration, and receives current from the power supply through an external resistor R. In this case, the transistor Qs,
Ql and transistor Q1°.

Qllによって定電流回路を構成し、トランジスタQ3
  、Qa等の作用は第1の実施例と同様である。
Qll constitutes a constant current circuit, and transistor Q3
, Qa, etc. are the same as in the first embodiment.

図から明らかなように第1図回路ではVref  。As is clear from the figure, in the circuit of Figure 1, Vref.

Vcc、GND用の3端子を必要としたが、この回路で
はVrefとGNDの2端子となり回路を簡素化するこ
とができる。
Although three terminals for Vcc and GND were required, this circuit has two terminals for Vref and GND, which can simplify the circuit.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、何らかの要因によって不整合を生じて
も確実に温度補償することが出来、温度依存性の少ない
基準電圧発生回路を提供することが出来る。
According to the present invention, even if a mismatch occurs due to some factor, temperature compensation can be reliably performed, and a reference voltage generation circuit with less temperature dependence can be provided.

【図面の簡単な説明】 第1図は本発明に係る基準電圧発生回路の一実施例回路
図、 第2図は本発明に係る基準電圧発生回路の他の実施例回
路図、および 第3図は従来の基準電圧発生回路である。 (符号の説明) Q、、〜Q、・・・トランジスタ、 R,−R,・・・抵抗、 Vref・・・・・・・・・基準電圧発生端子、Vcc
  ・・・・・・・・・電源電圧端子。
[Brief Description of the Drawings] FIG. 1 is a circuit diagram of one embodiment of the reference voltage generation circuit according to the present invention, FIG. 2 is a circuit diagram of another embodiment of the reference voltage generation circuit according to the present invention, and FIG. 3 is a circuit diagram of another embodiment of the reference voltage generation circuit according to the present invention. is a conventional reference voltage generation circuit. (Explanation of symbols) Q, ~Q,...Transistor, R, -R,...Resistor, Vref...Reference voltage generation terminal, Vcc
......Power voltage terminal.

Claims (1)

【特許請求の範囲】[Claims] 1、第1の抵抗を介してコレクタが基準電圧発生端子と
定電流源との共通接点に接続されベースが第3の抵抗を
介して該基準電圧発生端子に接続される第1のトランジ
スタと、第2の抵抗を介してコレクタが該共通接点に接
続されベースが該第3の抵抗および第4の抵抗を介して
該基準電圧発生端子に接続される第2のトランジスタと
、該第2のトランジスタのベースと該第4の抵抗との共
通接点に第5の抵抗を介してコレクタが接続されエミッ
タが接地される第3のトランジスタを具備し、該第1の
トランジスタのベース電位と該第2のトランジスタのベ
ース電位を該第1のトランジスタおよび第2のトランジ
スタの電圧利得の逆数によって設定されるようにしたこ
とを特徴とする基準電圧発生回路。
1. A first transistor whose collector is connected to a common contact between a reference voltage generation terminal and a constant current source via a first resistor and whose base is connected to the reference voltage generation terminal via a third resistor; a second transistor whose collector is connected to the common contact via a second resistor and whose base is connected to the reference voltage generation terminal via the third and fourth resistors; a third transistor whose collector is connected to a common contact point between the base of the transistor and the fourth resistor via a fifth resistor and whose emitter is grounded, the base potential of the first transistor and the second transistor 1. A reference voltage generation circuit characterized in that a base potential of a transistor is set by a reciprocal of voltage gains of the first transistor and the second transistor.
JP26746284A 1984-12-20 1984-12-20 Reference voltage generating circuit Granted JPS61147317A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26746284A JPS61147317A (en) 1984-12-20 1984-12-20 Reference voltage generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26746284A JPS61147317A (en) 1984-12-20 1984-12-20 Reference voltage generating circuit

Publications (2)

Publication Number Publication Date
JPS61147317A true JPS61147317A (en) 1986-07-05
JPH0560128B2 JPH0560128B2 (en) 1993-09-01

Family

ID=17445170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26746284A Granted JPS61147317A (en) 1984-12-20 1984-12-20 Reference voltage generating circuit

Country Status (1)

Country Link
JP (1) JPS61147317A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0447717U (en) * 1990-08-30 1992-04-23

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0447717U (en) * 1990-08-30 1992-04-23

Also Published As

Publication number Publication date
JPH0560128B2 (en) 1993-09-01

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