JPS61143864A - Data transfer system - Google Patents

Abstract

PURPOSE:To attain the transfer of data of multi-bit width with an extremely small bus width by regarding the transfer data as the serial data on a common bus and also using a data line with time division for each module. CONSTITUTION:A data line 10 is connected to both a transmission system circuit 20 and a reception system circuit 30. An input data line is connected to a transmission data register SDR21 of the circuit 20, and the output of the SDR21 is applied to the line 10 via a parallel/serial converting circuit PSC22. A circuit SPC32 of the circuit 30 is connected to the line 10, and the parallel data output is applied to a reception data buffer RDR31. The input at one side of the comparison data on a comparison circuit 38 of the circuit 30 is connected to a timing generator TMG26. While the input at the other side of the comparison data is connected to a module number selecting register MSR33. Both the RDR31 and SPC32 are controlled by the output of the circuit 38.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data transfer method on a common bus in a data processing device having a common bus structure.

(Prior art) When constructing a system that connects multiple modules (central processing unit, main memory, etc.) to a single bus (common bus) and transfers data, it is conventional to transfer the data handled within the module. A data line corresponding to the bit width, an address line for indicating the transfer destination module, and a control line for instructing the start of transfer, etc., were provided on the common bus.

In a module that initiates a data transfer when transferring data between modules, the identification number of the destination module is set in an address line, and the transfer is initiated through a control line. In addition, other modules determine whether the address data on the address line indicates the number of their own module at the timing of receiving the activation signal, and if it is the own module, the data on the data line is specified by the control line. Data transfer was performed by either importing the data from the module itself or sending the data from the own module onto the data line.

(Problems to be Solved by the Invention) However, with the method described above, it is necessary to secure data lines for the data width handled within the module on a common l(s), and as the number of connected modules increases, Address lines also require a lot of width. For this reason,
The disadvantage is that the physical width of the common bus becomes very wide. As a result, the physical size of common LX signal transmission paths (connection cords, backboards, etc.) and circuit elements such as drivers and receivers increase in proportion to the data width, which impedes miniaturization and increases costs. There was a problem in that it led to an increase in

The present invention eliminates the above-mentioned common bus width limitations and the problems of increased implementation space and cost due to an increase in the amount of hardware, minimizes the physical width of the common bus, and allows data to be stored in a simple manner. The purpose of the present invention is to provide a data processing device that can perform data transfer.

(Multiple membranes for solving problems) The present invention is directed to a data transfer method between modules in a data processing device having a plurality of modules connected to a common bus. The use of the data lines of the bus is allocated to each module in a time-sharing manner. That is, the time during which the data line can be used is determined for each module. Each module is configured as follows when transmitting transfer data and receiving transfer data.

First, when transmitting transfer data, each module sends the transfer data to the data line at the time allocated to the module. At this time, parallel transfer data handled within each module is converted into serial transfer data and sent out. On the other hand, when receiving transfer data, each module can receive the transfer data only during the time allotted to the module that sent the transfer data to be received. Each module then converts the serial transfer data received within this time into parallel data.

(Operation) In the above configuration, for example, assume that the central processing unit, which is one of the modules, receives a data transmission request. The central processing unit converts parallel transfer data into serial transfer data and sends it to the data line during the allotted time. On the other hand, it is assumed that another module, for example, a main memory processing device, receives a request to receive transfer data from the central processing device. In this case, the main storage device can receive data during the time allotted to the central processing unit, in other words, during the time when the central processing unit is transmitting transfer data. Therefore, the main memory receives serial transfer data within this time and converts it into parallel data.

This parallel data is then stored in the main memory.

(Example) Hereinafter, the present invention will be described in detail based on an example with reference to the drawings.

FIG. 2 is a block diagram showing a configuration example of a data processing device to which the present invention is applied. In the figure, functional modules 2 to 5 are connected to a common bus l. The number of modules is not limited to four, and any number can be connected. Furthermore, the modules 2 to 5 may be, for example, a central processing unit, a main memory, a channel, or the like.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, which is built in each module shown in FIG. 2. In FIG. The data line 10 is a bidirectional data transfer signal line included in the common bus l in FIG.
0 and the reception system circuit 30.

The input data line OUT DATA is connected to the transmission data register 21 (hereinafter referred to as SDR) of the transmission system circuit 20,
The output of the SDR 21 is connected to a parallel-serial conversion circuit 22 (hereinafter referred to as PSC) that converts parallel data into serial data, and P! The serial data output of 9G22 is connected to data line IO. One side of the comparison data input of the comparison circuit 28 is connected to the module number register 27 (hereinafter referred to as MNR) in which the own module number is set, and the other side is connected to the timing generator 2B (hereinafter referred to as TMG). There is. The AND gate 25 uses the input signal SDRWRT and the coincidence output of the comparison circuit 28 as two inputs, and the output is SD
Connected to the set signal input of R21.

Serial-to-parallel conversion circuit 3 that converts serial data to parallel data
2 (hereinafter referred to as SPC) is connected to the data line 10, and the parallel data output is connected to the reception data buffer 31 (hereinafter referred to as R
(referred to as DR). The output of RDR31 is an input data line IN DATA. One of the comparison data inputs of the comparison circuit 38 of the receiving system circuit 30 is TM.
G2B, and the other end is connected to module number selection register 33 (hereinafter referred to as MSR). Further, the coincidence output of the comparison circuit 38 is sent to the differentiation circuit 39, SPC
32 and an AND gate 40. The other input of the AND gate 40 is
The MSR33 write signal MSRWRT is connected, and the output is connected to the set input of the MSR33 and the set input of a warning notification flip-flop 37 (hereinafter referred to as ALM FF).

The output of the differentiating circuit 39 is the set input of the RDR31 and the A
Connected to the reset input of LM FF37, and also connected to the ALM
The output of the FF 37 is the warning notification signal AI, M.

Note that the TMO 26 provided in each module is synchronized by a synchronization means (not shown).

Next, the operation of this embodiment will be explained.

FIG. 3 shows a time chart during data transmission. The signal line IN is a data line 10 that is used in a time-division manner.
The module identification number (hereinafter referred to as module number) on the top is a signal indicating which module is the timing to send data (Fig. 3 (a)), and TMo 2
Generated in 8.

First, in the circuit shown in Fig. 1, when there is a data transfer request to this module, the data to be transmitted is sent to the output data line OUT DATA before the data is sent under the control of this module. Figure 3 (b))
, the set pulse signal SDRWRT of the SDR 21 is input (FIG. 3(C)). At this time, the comparison inputs of the comparison circuit 28 do not match, and the output signal 5END TIN is "0".
Therefore, the AND gate 25 opens and a set pulse is input to the 5DR 21, and the contents of OUT DATA (7) are falsely input to the SDR 21 (Fig. 3(d)).
In the example shown in the figure, OUT DATA has an 8-bit width and a value of "03" (hexadecimal number) is written to the DR21.

In this example, the module number of the module is assigned to number 5, and MNR2? is set to 5. In this state, the output MN of TMG 2El is 5
When counted, the comparison inputs are matched in the comparator circuit 28, and the output signal 5END TIN becomes "1" (
Figure 3(e)).

The PSC 22 is configured to sequentially output input data one bit at a time starting from the upper bit (MSB) when 5END TIM is "L" (Fig. 3(f)), and the output 5END TIN of the comparison circuit 28 is is “L”, the output data “D3” (hexadecimal number) of SDR21 is converted to serial data on the data line IO and “1” is output.
1010011'' (Figure 3(g)).

Similarly, other modules connected on the common bus
data line 1 at the timing assigned to its own module.
Send data to 0.

During 5END TIN signal “L”, 5DT21
While the SPC 22 converts the output data into serial data and sends it to the data line 10, the AND gate 25 is closed even if the SDRIII RT signal is input, so the SDR
A write pulse to 5DR 21 is not generated, and the contents of 5DR 21 are prevented from being rewritten during data transmission from SUR 21, thereby guaranteeing output data.

FIG. 4 shows a time chart at the time of data reception.

The signal line MN is the same signal as ◯ in FIG. 3 (FIG. 4(a)).

When attempting to receive data sent from another module, first, the module controls the output data line O.
After sending the module number of the receiving module to UT DATA (Figure 4 (b)), generate the write pulse MSR%IRT of MSR33 (Figure 4 (C))
, As a result, the receiving target module number is MSR3.
3 (FIG. 4(d)).

MSRWRT pulse is ALM FF 37 (7)
ALM FF 3? is inputted and written to the MSR33 mentioned above. is set, and the output signal ALM becomes l'' (Fig. 4 (j)). By referring to this ALM signal, it is possible to confirm whether or not the data transmitted from the target module to be received has been received.

In the example of FIG. 4, the module number to be received is number 15, and the module number 15 is output from the MSR 33. The timing when the module with module number 15 sends data, that is, the output MW of MG28 is 15.
Then, the output of MSR 33 and the content of the signal line capacity match, and the comparison signal 38 Ichinarita force R, which uses both signals as comparison inputs,
EV TIM becomes "l" (Fig. 4(e)).

The SPC 32 is configured to take in serial data on the data line IO only while REV TIN is "L" and convert it into parallel data. In the example in Figure 4, the serial data sent by the module with module number 15 is “
01011101" (Figure 4 (g)), and when all 8 bits of this serial data are taken in, the SPC
The output of 32 is the MSB of the first bit of the serial data.
When data transmission from the module with module number 15 is completed, that is, the signal line MW
changes to 16 (Fig. 4(a)), the comparison inputs cannot match in the comparator circuit 38, so the -Narita force signal REV TIN changes from "1" to "0" (Fig. 4(a)).
e)), the SPC 32 stops taking in the data on the data line 10, and the output of the SPC 32 becomes the above-mentioned "5 D' (
4 (h)).

The differentiating circuit 39 is composed of a circuit that takes a differential after the REV TIN signal, and when the REV TIN signal is
One pulse is generated when the state changes from "" to "O" (Fig. 4(f)), and the output signal R of the differentiating circuit 39
EV END is connected to the set input of RDR31, and the output data of SPC32 is set to RDR31 by the REV END pulse, and the output IN of RDR31 is
Data "5D" (hexadecimal number) sent by the receiving target module (module number 15) is obtained from DATA.

At the same time as the above-mentioned setting operation to RDR31, REV E
ALM FF37 that treats ND pulse as a reset signal
is reset, and the output signal ALM changes from “l” (data not received from the receiving module) to “0” (reception completed)
4 (j)), this ALM signal allows the data sent out by the receiving module to be received, and RDR3
You can check that it is set correctly to 1.

The AND gate 40 is for controlling the data write operation to the MSR 33, and when the data on the data line 10 is being received by the SPC 32, that is, when the REV TIN signal is in the “L” state, the MSRWRT pulse is input. Even if the data line 1 is
During data reception from 0, the REV TIM signal is “
There is no longer a change from "1" to "O", it is possible to prevent reception from being interrupted in the middle of data, and it is possible to guarantee received data.

Furthermore, by writing its own module number in the MSR 33, it is possible to receive data sent from its own module, and self-diagnosis of the data transmitting/receiving circuit system can be easily performed.

In the above embodiment, the data sent from each module is divided into 8-bit units, but the unit of division is not limited to this, and it goes without saying that it can be divided into bit units suitable for the device configuration. , differentiation circuit 39,7
Since each circuit such as M021m, PSC22, and SPo32 can be easily realized using currently known circuit technology, detailed explanation will not be given here.

As explained above, according to this embodiment, the transfer data is handled as serial data on the common bus, and the data lines are used in a time-divided manner for each module, so the data lines for the data width are used as in the conventional method. Also, address lines and control lines are not required, and multi-bit width data transfer is possible with an extremely small path width. Furthermore, the amount of hardware such as drivers and receiver circuit elements can be reduced, and the device can be constructed at low cost. For data transmission, all you need to do is set the data to be sent, and for reception, all you need to do is set the number of the receiving module and wait for the reception completion notification, so the procedure is very simple, and the part that controls data transfer It is possible to easily design software or firmware for the software.

(Effects of the Invention) As explained above, according to the present invention, transfer data is treated as serial data on a common bus, and data lines are used in time division for each module, so There is no need for data lines, address lines or control lines, and multi-bit width data transfer is possible with a very small bus width. Furthermore, the amount of hardware such as driver and receiver circuit elements can be reduced, and the device can be constructed at low cost. Furthermore, in data transmission, data is sent out at the time given to the own module, while in data reception, data can be received only during the time when the data to be received is being sent out, which simplifies the data transfer procedure.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a data processing device to which the present invention is applied, and FIGS. FIG. 4 is a timing diagram illustrating example operation. l...Common bus, 2-5...Module, 10...Data line, 20...Transmission system circuit. 21... Transmission data register (5DR), 22...
Parallel-serial conversion circuit (PS), 2B...timing generator (TMG), 27... module number register (M
NR), 2B... Comparison circuit, 30... Reception system circuit, 31... Reception data buffer (RDR), 32...
Serial/parallel conversion circuit (5pc), 33...Module selection register (MSR), 37...Warning notification flip-flop (ALM FF), 38...Comparison circuit. 38... Differential circuit.

Claims (1)

[Claims] In a data transfer method between modules in a data processing device having a plurality of modules connected to a common bus, use of data lines of the common bus is time-divided and allocated to each module, and each module transfers data. When transmitting, the parallel transfer data in the module is converted into serial transfer data and sent to the data line at the time allocated to the module, and when receiving transfer data, the transfer data to be received is sent. A data transfer method characterized by being able to receive data only during the time allocated to the module and converting received serial transfer data into parallel data.