JPS61141433A - Display device of camera - Google Patents

Abstract

PURPOSE:To show distinctly a preview operation to the user by the constitution in which the display state of the part for displaying the characters or marks associated to a stop changes during the preview operation. CONSTITUTION:The title device is provided with a display part consisting of the characters and marks associated to the stop of a camera, a detection means for detecting the execution of the preview operation and a control means for changing the display state of the above-mentioned display means in the stage of the preview operation. The display state of the display part associated to the stop out of the display part of the camera is changed by the detection signal and, for example, the character F provided along the numerical value indicating aperture quantity flickers to indicate that the camera is under the preview operation.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a display device for a camera.

[Prior Art] Among cameras equipped with a preview mechanism for checking the depth of field by narrowing down the lens before photographing, there is no known conventional camera equipped with a means for displaying that a preview operation is in progress.

[Object of the Invention] An object of the present invention is to provide a display device that can display that a preview operation is in progress.

[Structure of the Invention] The present invention includes a display section consisting of characters and marks related to the aperture of the camera, a detection means for detecting that a preview operation is being performed, and a display state of the display means when the preview operation is performed. and control means for changing.

[Operation of the Invention] When it is detected that a preview operation is being performed on the camera, this detection signal causes the display state of the display part related to the aperture of the camera's display section to change, so that, for example, the display state of the display part related to the aperture changes. The provided letter F flashes to indicate the preview state.

[Example 1] Fig. 1 is a diagram showing the external appearance of a camera to which this invention is applied. 1 is a camera body, 2 is a shutter button, 3 is an interchangeable lens, and the interchangeable lens 3 contains data about the lens, such as when opening the camera. A device is provided that outputs data indicating the aperture value and the like to the camera body as an electrical signal. Further, the glossy button 2 is provided with a photometry switch Sl and a release switch S2, which are operated according to the amount of depression of the button, by a known method.

Reference numeral 4 denotes an external display section, which displays the calculated EV value and operation mode, as well as various other data that will be described in detail later.

5 is a finder, and within the field of view of this finder 5 is provided an internal display section 6 (see FIG. 2) for displaying data and the like displayed on the external display section 4.

SM is the main switch.

FIG. 2 shows details of the display on the external display section 4, and from the top there are PROGRAMS for displaying the AE mode. When the AE mode is program mode (hereinafter referred to as P mode), PROGRAM is displayed and S is turned off, and when the AE mode is in aperture priority mode (hereinafter referred to as A mode), A is displayed and PROGRAM is displayed.
Turn off R and MS. M and S are displayed in the manual mode (hereinafter referred to as M mode) and in the shutter speed priority mode (hereinafter referred to as S mode), respectively. Below that is the ISO mark when in 1SO mode, and immediately below there is a 7-segment, 4-digit SS, ISO, and CTR display.
To the right of it is a setting instruction mark TAI. Below that, there is a bar display that only turns off when the camera's main switch SM is turned off, and a 7-segment, 2-digit F, +/- display, and to the right of it is a setting display. There is an instruction mark TA2. On the left side of the two digits is an aperture value discrimination mark F, and furthermore on the left end is a +/- mark which is a sign when setting an override.

Furthermore, FIG. 2C shows details of the display on the internal display section 6.
2 close to the temple from the left edge for camera shake (camera shake) display
There are two camera-shaped marks CAI and 'CA2, followed by a 7-segment, 4-digit SS.

There are ISO and CTR display sections, followed by S, P, and A for AE mode display. The S mark consists of a 7-segment arrow pointing toward the 4-digit side to indicate shutter speed priority.
Similarly, A mark requires aperture priority! l! ! 7! t<, e
L: Ah, 7 discoloration. It is composed of arrows pointing in one direction. The P mark has nothing to do with prioritizing both aperture and seconds, so there is no arrow between S and A. A.E.
The 7 segment 2 digits on the right side for mode display display the F value and the +/- value in +/- mode. Immediately to the right is the M mark for AE mode display. this is,
Since the metered manual display lights up at the same time, it is displayed near the meter display to make it easier to understand. On the right side there are ten and - marks, which are the oval ride and metered manual codes, followed by a numerical band consisting of seven segments. This numerical value band displays +/- values during AE mode (P, A.

(Only in S mode) and also displays the metered manual value in <AE mode (Only in M mode).

Finally, there are the ASI and AS2 marks that indicate the metering mode. For average metering, only ASI lights up, and for partial metering,
Both ASI and AS2 are lit.

321ilJa, b, Fig. 33 a, b shows the override being displayed, but in the internal display of the finder, the place where the override value is displayed is not the override (
+/-) mode and AE mode. This is because during the override mode display, an attempt was made to display the information near the center of the display section to make it easier to understand.

FIG. 3 shows the overall configuration of the control device related to the above-mentioned camera display. The CPU10, which uses a central control microcomputer that controls the operation of the entire camera, is supplied with power +E from the battery II, and the main switch SM, which is pulled up with a resistor R, and the reference oscillator XL19 peripheral circuit for operating the CPU10 (especially control signal group for display).

cs, pwc, serial data 5DATA necessary for serial data transfer, and serial clock SCK are connected to the peripherals.

An outline of the operation of CPU10 will be described later.

On the other hand, the display circuit unit 20 is inputted with the power source E from the battery 11, the main switch SM, the signals σ'', pw, 5DATA, SCK, the reference oscillator XL2 from the CPU10, and the reference power supply 21 for driving the liquid crystal. As outputs, there is a drive output group for the common and segment electrodes of the external display section 4 and internal display section 6 using a liquid crystal display.The drive output terminal group is for the external display section of the camera connected in parallel. 4 and an external display section 6 in the finder.

Inside the display circuit 20, there is a data latch section 22 that latches serial data. Decoder section 23 that decodes the latched data. Segment driver unit 2 that drives the LCDs of external and internal display units 4 and 6 using decoded signals
4. Common driver section 25 that drives the common section of the LCD
．． Oscillation frequency dividing section 26 that creates operating clocks for each section. L.C.
There is also a voltage generating section 27 that generates a driving voltage of D.

FIG. 4 is a detailed diagram of the oscillation frequency dividing section 26 shown in FIG.
). flip flop F
The PI is provided with a reset terminal R so that it can be initialized by installing a battery.

FIG. 5 is a detailed diagram of the common driver section 25.
, VLCD2. VDD voltage analog switch A
C0M1. through SI-AS4 and PchFET FPI, FP2 at timings of φ, , φ1°. It is configured to output to C0M2. Nantes Gate NAI, 2. (Noa game) NRI, 2 and inverter IN3.4 are gates for creating timing.

FIG. 6 is a part of a detailed diagram of the segment driver section 24,
VLCD2. The analog switch AS5 and PchFET EP3 for switching each voltage of VDD are made of φ1. Of the timing of φ1°, segment data S2n, 52n-
It is configured to be driven according to the state of No. 1. Nant gates NA3 to NA7 and inverter IN6.7 are S2n
, 52n-1 constitute a clock selector, and inverters IN5. The flip-flop FF2 has a diameter of φ1. Glue for creating clocks with 4 types of phase differences from φ1°
, j-lock generator.

The entire segment driver section is of the type shown in FIG. 6, in which the clock selector, analog switch, and Pc1FET parts are prepared in the same number as the SEG output terminals, and a clock generator is added.

FIG. 7 is a detailed diagram of the data latch unit 22. There are seven 8-bit shift registers 5RI-SR7 that receive serial data 5DATA from CPolo, and the parallel outputs of these shift registers are latched at the falling edge of the LTCH signal. Seven 8-bit latches LTI-LT7
is connected to.

A reset R input is applied to the jlO data of the latch LTI, and a set S input is applied to the j11 data.
It is reset and set by the OR signal. Therefore, the initial state is jlO="Low", jll="High"
It is.

On the other hand, the external Norial clock SCK is applied to the NOR gates NR3 to NR as a φS signal that has passed through the OR gate ORI.
9, and also serves as the φ manual power of the counter decoder CD. When the set manual power S of the counter decoder CD is “°High”, the output BSI of the counter decoder CD
~BS7 is all “High” and S human power is “Low”
”, every 8 pulses of φλ force sequentially changes from BSI to B
One of the signals up to S7 becomes “Low”.

When any one of B11-B57 is “Low”,
One of the corresponding NOR gates NR3 to NR9 becomes active, and inputs the φS signal, which is the output of the NOR gate, to the φ input of one of the serial registers 5RI-SR7. External control signal pw from CPU10
c and σ1 are logically summed by OR3 to become a P-CS signal, which is input to the other input of the OR gate OR+ and the S input of the counter decoder. or,
It becomes one input of OR gate OR2, and the other input BS
7, and the D of flip-flop FF3 is
It serves as an input and one input of the Nant gate NA8. The FOR signal is input to the set input S of the flip-flop FF3, and its output is connected to the other input of NA8. In addition, the φλ force of flip-flop FF3 includes φ,
A small output is connected.

FIG. 8 is a detailed block diagram of the decoder section 23 shown in FIG. 3, and shows switch circuits SWI, SW2 . Data converter DCI-DC
4. Segment decoder sections SDI to SD6. It is composed of an output control section CTLI. The switch circuit Swl receives the outputs j12 to 0 of the decoder 22 as inputs.
6. j22-j27. j32-j37. j40
25 outputs j50 to j53 of the decoder 22 are input to the data conversion unit DC3, and outputs NO and jll of the decoder 22 are input to the data conversion unit DC4.

j20. j21. j54-j57. j60～j67゜j
A total of 53 pieces of 24 pieces from 70 to j77 are latch L in Fig. 7.
It is connected to the output of TI-LT7. Further, two signals SM and vW from the main switch shown in FIG. 3 are input to the data converter DC4. As shown in Fig. 4, φ14 is connected as an input to the output controller unit CTLI, and 70 lines from S to S70 are connected to the segment driver unit 2 as outputs.
Connected to 4.

FIG. 9 is a detailed diagram of the switch circuit SWl in FIG. 8,
jn from data latch 22 (n=I 2~47(
However, 17, 20, 21, 30.31 are excluded <)) → Pn
(n = 12~47 (however, 17, 20, 30゜31
25 signals to 25 Nant gates N
Using A, FOM, CTR, ISO.

It is switched by the SS signal. FON, CTR.

When the ISO and SS signals are “Low”, the Pn signal is “
High” and the jn signal is cut off, but the FON.

When the CTR, ISO, and SS signals are “High”, Pn
= jn, and the switch is turned on.

The first theta figure is the first one! 1, 13 to 15, and 23; A, B, and C.

For each input of D, mark the intersection of the arrow with the output Q to indicate the same function as the Nantes gate, i.e., Q.
=B'D.
1. Figure 1f shows the data converter DC in Figure 8.
3, for inputs j50 to j53, output p!
~ Shows the logic of p9. This output serves as an input to the switch circuit SW2 shown in FIG.

FIG. 12 is a detailed diagram of the switch circuit SW2 of FIG. 8, in which input pl-99 is connected to q71-q78 . It represents the logic switched to q82 to q89. The input p signal enters the Nantes gate,
When the switching signal MON and the +/-ON signal are "Low", the output q signal becomes "High" and the p signal is cut off. M.O.
When the N,+/-ON signal is "High", the output q signal becomes equal to the input p signal, and the switch is turned on.

Figure 13 shows the segment decoder section 5DI-9D in Figure 8.
In the detailed diagram of 4, the output rl-r2 for the input Ql-939
It shows the logic of 9. This figure shows segment decoder section S.
Since the basic configurations of DI to SD4 are the same, they are shown in the same drawing, but the necessary parts of 5DI to SD4 are extracted from this drawing. This output is provided by the human power of the output control unit CTLI shown in FIG.

FIG. 14 is a detailed diagram of the data converter DC2 of FIG. 8, showing the logic of outputs q40 to q62 for inputs p12 to p16. This output is from the segment decoder SD in Figure 8.
5 input.

FIG. 15 is a detailed diagram of the segment decoder section SD5 of FIG. 8, with inputs Q40 to Q62. For Q71-Q78,
The logic of outputs r30 to r43 is shown. This output is an input to the output control section CTLI shown in FIG.

FIG. 16a shows the output control section CTL! of FIG. Part of the detailed diagram of the segment decoder! l5DI-SD6
The outputs S1 to S70 are obtained by the output of the data converter DC4 and the clock φ14.

In this figure, r2n and Bs are shown in arbitrary combinations, but in reality they are connected in the combinations shown in Table 1.

Table 1 shows a truth table by replacing the circuit diagram of FIG. 16a with logical expressions. Furthermore, the combination of r2n and Bm is specifically shown. (1≦1≦8).

(I≦2n≦68) Regarding r69, it is shown in FIG.

FIG. 16 shows input r69 and output s69. It shows the logic to s70.

FIG. 17 shows the relationship between the outputs q1 to Q39 of the data conversion unit Del of the decoder unit 23 and the characters displayed on the display units 4 and 6, and the relationship between the inputs p22 to p to the data conversion unit DC1.
27. p32-p37, p40-p47. When q1 to Q39 are output according to the state of CTR, Ql-439
The displayed characters are controlled depending on the state of 'Low' or 'High'.

That is, if the output Ql is "High", SDI, I, and therefore the display at lθ° on the display unit 4 (and 6) is 0°92
If is "High", it means that the display of the IOo digit is 2. For the shutter speed SS value, p22 to p27,
Data are given in 1132 to p37 for the ISO value, and p40 to p47 and the CTR signal for the CTR value. Also, p22-p27゜p32-p37, p40
-p47 are all "High", the configuration is such that no output is produced for that data. Therefore, for example, p22 to p2 for the shutter speed SS value.
7 data is displayed, other p32 to p37. p4
The data converter DC4 and the switch circuit 5WII are configured so that all of the signals 0 to p47 are set to "High". (See FIGS. 9 and 21) The contents that can be displayed are illustrated in FIG. 18. There are 36 types of SS values, 31 types of ISO values, and 100 types of CTR values.

FIGS. 19 and 20 are diagrams showing the relationship between the data of the data conversion unit DC2 and the switch circuit SW2 and the characters displayed on the display units 4 and 6. SW2 pi-p9, MON
, q40 to q62, depending on the +/-ON state. q71
-q78. The outputs of q82 to Q89 output data as shown in this figure. Data is given in p12 to pl6 for the F value, and pl to p9 for the override value and metered manual value.
jFigure 21 is the 8th
This is a part of the detailed diagram of the data converter DC4 in the figure, and shows the switch switching signals MON, +/- of the switch circuits SWI and SW2.
ON, FON.

CTR, ISO, SS logic and CT [, 1 part ON
, the logic of the OFF signal and the logic of the 0FFVLCD signal applied to the voltage generator 27 in FIG. 3, respectively. The input signal is the output signal N O,jl 1 of the data latch section.
j55. j56. j60～j67゜j70. j71, external signals, SM, and PWC.

FIG. 22 is a part of a detailed diagram of the data conversion section DC4 of FIG. 8, and shows the logic of the B1-88 signal of the CTLI section.

The input signal is the output signal j20. of the data latch section. j55
~j57. j61 to j64, j70 to j74, and external signal PW.

FIG. 23 is a part of a detailed diagram of the data conversion section DC4 of FIG. 8, and shows the logic of the r51 to r69 signals of the control section CTLI. The input signal is the output signal j of the data latch section
2+, j54~j57° j70~j73. j75～j7
7 and the output signal q40 of the DD2 section. and external signal PWC
It is. Second! Data conversion section D of Fig. 8 in Fig. 23
Contains all C4.

FIG. 24 is a detailed diagram of the voltage generating section 27. Create a reference voltage VLCD by externally connecting a diode DI and a resistor R1 between 1E and GND, and connect a capacitor C+.

By supplying the voltage to the booster circuit 27a (the part surrounded by the broken line) including C1, the voltage doubled (+E −VLCD) (10E
-V LCDI). VLCD and VLCD
Both I are led to V LCD0 and V LCD2, respectively, by an output control circuit made of an analog switch and a PchFET.

V LCD0 and V LCD2 change their outputs depending on the state of 0FFVLCD. OF F V LCD is “L”
ow”, V LCD0 = V LCD , V
LCD2 = V LCDI, 0FFV LC
When D is “High” + 7), V LCD0 = V
LCD2 = V DD.

Further, the booster circuit section 27a obtains a clock from φ in FIG. 8 to switch the connections of the capacitors c and C2 to boost the voltage. Further, FOR is a terminal for starting the booster circuit, and the booster circuit is started by the FOR output shown in FIG.

FIG. 26 is a time chart of the data latch section 22 of FIG. 7. Both external signals PWC and C3 become “Low”, and at the falling edge of SCK, serial register 5RI-9
The data in R7 will be rewritten.

The contents of SRI are all rewritten at the falling edge of the first 8th pulse of SCK, and from the 9th pulse onwards, they are rewritten in order in shift registers SR2 to SR7 every 8 pulses. At the rising edge of the 49th pulse immediately after SR6 is rewritten, BS7 becomes "Low", and at the same time as SR7 rewriting begins, flip-flop FF3 reads the D input at the rising edge of φ, so the Q output of FF3 becomes "Low". LOW
", and does not change until BS7 becomes "H4gh" again.

The LTCH pulse is created by the output signal and the p-cs signal, and the contents of the 5RI-8R7 serial register are transferred to the LTI
~It will be taken into the latch of LT7.

FIG. 25 is a time chart showing the overall general operation from after the battery is installed in the camera. Immediately after the battery is installed, the display circuit section 20 is initialized by the FOR signal. Signal VL
CDI becomes earth GND level and becomes 0FFVLCD or "H4gh". Therefore, no voltage is applied to the liquid crystal. After that, the XLI of CPU10 starts oscillating, and CPU10 starts operating. After a while, the oscillator XL2 of the display circuit section 20 starts oscillating, and the clocks φ0 to φ1. starts to start. When the clock φ starts to operate, the data latch unit 22 starts operating, and the CPol
If serial data comes from o, it operates as shown in Figure 26. When the clock φ6 starts operating, the voltage generating section 27 shown in FIG. 24 starts operating, and after a short period of time, the potential of the signal VLCDI becomes stable. After that, 0FFVLCD as necessary.
If you set it to “Low”, the liquid crystal drive voltage, VLCDO
, VLCD2 are supplied to the display sections 4 and 6.

28 to 35 and 37 to 39 show various display modes of the external display section 4 and the internal display section 6, and each figure a except for FIG. Figure 5 H section display section 6'' display 2 shows.
1. Figures 28a and 28b are AE displays in program mode, showing auto second time 1/250, auto aperture value 5°6, PROGRAM of the program, and times.

The mark ASI at the right end of FIG. 28 indicates the photometry mode and indicates average photometry. - Figures 29a and b are
This is the AE display in the aperture priority mode, and when the aperture setting mark is pressed, the set aperture value is 5.6 and the auto second time is 1/250, and the aperture priority A and D represent the AE mode.

FIGS. 30a and 30b are AE displays in the shutter speed priority mode. When the shutter speed setting mark is turned off, the set shutter speed value is 1/250 and the auto aperture value is 5.6 degrees, and the AE mode is indicated by S with glossy speed priority and ■.

FIGS. 31a and 31b are AE displays in manual mode.

The setting mark for the shooting time and aperture value indicates the shooting time value 8" and the setting aperture value summer, 4, and the manual mode M, !=[j7 indicates the AE mode. The right end of the internal display is the metering This is the partial metering mark for the mode, and the left side is the error amount of the manual setting value against the appropriate value, which is the so-called metered manual indication value, +
This indicates that there is a difference in indication of 6.5EV. The mark on the far left is a camera shake (hand shake) warning mark.
The two marks will light up alternately.

FIGS. 32a and 32b are displays during override setting. It represents the override direction 10 and the absolute amount 1.5EV.

FIGS. 33a and 33b show the AE mode display after override setting. Compared to FIG. 28, ten override directions have been added. The internal display also displays the absolute override amount of 1.5 EV. However, the internal display shows +1.5 or blinking.

FIGS. 34a and 34b are ISO setting display.

The ISO mark and ISO value 100 are displayed.

However, the ISO mark does not light up on the internal display.

FIGS. 37a and 37b show hand shake (camera shake) warning displays. On the internal display section 6, mark CA on the leftmost camera
I, CA, and 2 light up alternately to indicate movement.

FIG. 37C shows the display on the external display section 4.

FIG. 35 is a display in standby mode.

Only the bar display was dimmed, and all other lights were off. The camera functions other than display are suspended.

<Operation Description> - Overall Operation - The basic operation of the display circuit section 20 will be explained. When the DC voltage +E is supplied from the power supply 11, the momentary F generated by the power-on reset circuit 40 (right end in Figure 4)
The OR signal causes the flip-flops FFI (FIG. 4) of the frequency division stage, the flip-flops 7O-71FF2 (FIG. 6) of the clock generator of the segment driver section 24, and the flip-flops FF3 . Latch L
TI (Figure 7), starting FET 27b of voltage generator 27
(FIG. 24) are each set to the initial state. Latch LT
1, each data terminal is set to NO=“Low”.

Set jl 1=“High”. flip flop FF
I.

In FF2, the output state is set to Q-“Low” and σ-“High”
”-.In FF3, set the output state to Q=“Hi”.
gh”.

Set to "Lov". In the voltage generating section 27, FE
By momentarily turning on T27b, the capacitor C2 is charged, and the level of VLCDI becomes the GND level. In this state, since the crystal oscillator XL2 of the oscillator 41 (Fig. 4) has not started oscillating, there is no circuit operation at all, and the oscillation rise of XL2 ( Waiting for the oscillation rise of =φ. In one direction, VDD, VLD2. V
Although the LDO is given in an undefined state (COMI is V LCD2 .

C0M2 is VLCDO, 5EGn is S2n, 52n-
1) VDD or V LCD2) 0FFVLCD input to the voltage generator 27 is j 10 = 'L
ow”, jl By the initial setting of I=“High”, AND gate A50° inverter 150. OR gate 050
In order to set it to "High" through the circuit shown in FIG. The applied voltages are equal, and there is no DC voltage application that is harmful to the liquid crystal.

Next, the crystal oscillator XL2 starts oscillating and φ. When a clock enters the flip-flop FFI in the frequency dividing stage, all parts start operating at the same time.

The clock φ enters the flip-flop FF3 of the data latch section 22 and serves to generate an LTCH pulse when the serial data exchange (word) from the CPU 10 starts.

Clock φ. enters the booster circuit of the voltage generator 27, and C1
, Ct, the voltage boosting operation is performed.

Clock φ3. φ10 enters the common driver section 25 and segment driver section 24 and becomes a clock for the liquid crystal drive waveform.

The clock .phi.24 is input to the output control section CTLI of the decounter section 23 and is used to control the blinking state of the display contents.

The operation after the rise of oscillation of the crystal oscillator XL2 will be explained first with respect to the voltage generating section 27. The clock φ input to the booster circuit 27a in FIG. 24 starts the boosting operation, and the initial VLCD
ILCD display Indicates the D level (V DD-
2V LCD) level and stabilize. Thereafter, it continues to work without interruption until the power supply voltage drops and it stops operating, or the oscillation circuit stops, causing the lifting and lowering operation to stop. On the other hand, the terminal 0. “L” on j11
ow'.

The moment a signal other than "High" is input and latched, OF
Wait for output of VLCDl, VLCDO=VLCD.

These are common drivers 25. The voltage is guided by the segment driver 24 and applied to the LCD display of the inner and outer display sections 4.6 as a voltage for driving the liquid crystal, and a liquid crystal display is performed based on the latched data.

Next, the data latch section 22 will be explained with reference to FIG. 26. This circuit starts operating when both the σ signals become "Low" at VW. PWC is, for example, a timing signal for supplying power to a photometry circuit of a camera (not shown), and p
The photometry circuit starts operating when wc=“Low”. Further, C8 is a signal for determining the other party for serial data communication, and one signal is outputted from CPU10 to other circuits in the camera (not shown). σ1
="Lo" selects the other party for serial data communication.

When either PWC or CS is “High”, P・C
8 signal is "High", the counter decoder CD is set, and all BSI to BS7 outputs are set to 'High'.
''.Also, ORI output φS is 'H
The output LTCH of the Nant gate NA8 is also “High't'A6°PWC and CS are both “L”.
ow”, the counter decoder CD enters the operating state, the OR gate ORI and the OR gate OR2 open, and the S
The CK and BS7 signals become detectable. SCK's 1st
At the rising edge when the pulse is input, BSI becomes "Low 1" and NOR gate NR3 opens. At the falling edge of the first pulse, the φ input of shift register SRI rises, so 5DAT at that time
Only one shift register SRI takes in the contents of A.

The data at this time is jlO. Then a second pulse comes and the same operation is repeated. At the falling edge of the eighth pulse, eight pieces of data are taken into the shift register SRI, and the eighth data is called j147. Until this time signal B
SI is “L ov”.

When the next 9th pulse rises, BSI becomes "High", BS2 becomes °LO °, Noah Gate N R3 closes,
Noah Gate NR4 opens. Since the φλ force of shift register SR2 rises at the fall of the 9th pulse, the 5DAT at that time
Take in the contents of A by one shift register SR2M. The data at this time is j20. Thereafter, the process continues in the same manner, and at the rise of the 49th pulse, BS6 becomes "High", BS7 becomes "LO", Noah Gate NR8 closes, and Noah Gate NR9 opens. Furthermore, or gate OR2
The output of shift register SR7 becomes ``Low''.The contents of shift register SR7 are 56'<'L'7m'r''rj70~j77(
Df-1h "1 is taken in, but the LTCH output remains °High" from the first pulse until the 56th pulse, and each shift register SR
Data is not fetched from the latch LT to the latch LT. In other words, the output of the OR gate OR2 becomes "Low'" due to the OR gate OR2 opening at the 49th pulse, but the flip-flop FF3 receives "Lot" from the D input due to the rise of the clock φ, and the ζ output becomes "High". become. Since the other input of the Nantes gate NA8 becomes "L ov" before the ζ output changes, the LTCH output remains "High".

Here, the output of the OR gate OR2 becomes "High" depending on whether the 57th pulse comes or whether either pwc or C3 becomes "High". At this moment, the ζ output of the flip-flop FF3, which is the other input of the Nantes gate NA8, is also "High", so the output of the Nantes gate NA8 is L.
TCH becomes “Low”. This “High”→’Lo
The falling edge of "w" is a latch signal, and the data stored in shift register 5RI-SR7 at 1 is latched LTI.
- Latched into data memory of LT7. After that, with the rise of the clock φ, the flip-flop FF3 takes in the "High" of the D input, and the output becomes "Low", and the counter decoder CD is set to "High" of either pwc or cs, and each Return to initial state.

The above is an overview of the operation of the data latch. Here, if the number of clock bytes for serial data communication is insufficient, the last latch pulse LTCH will not be output, so no data error will occur, and even if the number of clock bytes exceeds 5.
It is automatically turned off at the 7th pulse, and naturally no abnormality occurs.

Furthermore, since the clock within the same byte is processed so as not to be interrupted on the sending CPU side, abnormalities in data communication are completely prevented.

On the other hand, even if the external signals PWC, C6, SCK, and 5DATA operate normally, if the internal φ is not operating, the LT
CH pulse no longer appears and shift register 5RI-SR
It is no longer possible to latch the data taken into LTI-LT7 into latch LTI-LT7. This means that when φ is not operating, the liquid crystal drive wave is also not operating, and a DC voltage is applied to the liquid crystal. Therefore, at that time, jl O = “Low”, jl 1 = “High”
' and set OFF VLCD="High" so that no voltage is applied to the liquid crystal.

For this reason, external data is not taken in when the clock φ is not operating.

Next, the common driver section 25 and the segment driver section 2
I will explain about 4.

In Figures 5, 6, and 27, Nant Gate N
AI, NA2. Noah Gate NRI? JR2, inverter IN3. The analog switches ASI to AS4°Pch are connected to PET PP1.
Controls each switch of PP2. The input signal of the gate circuit is φ1. φI, and due to this timing, C0M2
．． The outputs of COMI change as shown in FIG. 27.

The signals C0M2 and COMI have the same period of -1°, and are shifted from each other by 1/4 period.

Let the output value be -IVDD,! :VLCDO and VI, CD
2 (7) Has three levels.

In FIG. 6, a clock φ is processed by a clock generator composed of an inverter INS and a flip-flop FF2. and φ. 4 types of black that can be created by is selected by a clock selector made up of Nant gates NA3 to NA7. The selection condition is 92F1
．． There are two signals S2+1-1, and the output waveform of sSEcn is determined by these conditions.

This state is shown in FIG. 27, and each state is different depending on four types of states determined by S2n and 52i-1.

The period is the same as that of the clock φ1°, and there is a difference of 1/4 period from each other. The output values are VDD and V
It has two LCD levels. signal COMI,
The potential difference between 2 and segment signal 5EGn is 2xVLC.
The LCD display lights up depending on the waveform of the portion that becomes D2.

5EGn (LH), 5EGn (H
The segment of the LCD display to which voltage H) is applied lights up, and 5EGn (HL), 5E for C0M2
Gn (HH) electric
, j pressure is applied, the segment of the LCD display lights up. For 5EGn (LL), the segment will not light up even for COMI and C0M2.

In other words, the 52n-1 signal is a signal that controls lighting of the segment for COMI+, and 52n-1="Lot
”, it is OFF, and when 52n-1 = “High”, it is O.
Become N. The 92i signal is a signal that controls the lighting of the segment for C0M2, and when 52n="Low", it is O.
When FF, 52n = 'High', it becomes ON.

Data latched in Figure 7 No-07゜j20~j2
7. j30-j37. j40- j47゜j50- j
57. j60-j67,. 70-j77 is month 7. j3
0. All bits except 3 bits of j31 are input to the decoder section shown in FIG. SWI.

SW2. DCI-DC4,5DI-SD6 is single. :This is a gate circuit and has no timing relationship at all.

The explanation is below.

First, the contents of the serial data will be explained.

jlO, jll are signals that control the supply of liquid crystal drive voltage, j10=“L ov”, month 1=”High
The liquid crystal drive voltage stops only when ''', and the voltage applied to the liquid crystal becomes 0.

j12 to j16 are data signals (
(see Figures 9, 14, 15, and 20),
There are 23 types. Also, j12 to j16 are all “High”
Nothing is displayed when .

j20 is a signal related to a warning of insufficient battery voltage in the camera (see Figure 22), and j20="High"
All the displays displayed at this time repeat blinking at a period determined by φI4.

j21 is a hand shake (camera shake) warning signal (see FIG. 23), which becomes "High@" when the shutter speed becomes slower than near the limit that causes hand shake (camera shake).

At this time, the camera shake mark CA1 on the internal display section 6 in the viewfinder. CA2 lights up alternately.

j22 to j27 are data signals (
(see Figures 9, 13, 17, and 18),
There are 36 types. Also, No.22 to J27 are all “High”.
”, nothing is displayed.

j32 to j37 are data signals related to the ISO value of film sensitivity (FIGS. 9, 13, and 17).

(see Figure 18), and there are 31 types. Also, j32~j
When all 37 are "High", nothing is displayed.

j40-j47 are data signals regarding the timer seconds value (
(see Figures 9, 13, 17, and 18),
There are 100 types from 0 to 99.

Further, when all of j40 to j47 are "High", nothing is displayed.

j50 to j53 are data signals regarding the override value and the metered manual deviation amount (see Figures 11, 12, and 19.20), and depending on the content to be displayed, 9 types of override values and the metered manual deviation amount are displayed. The 14 types of deviation amount values in the manual are switched and sent from the CPU. When j50 to j53 are all "°High", nothing is displayed.For switching the display contents, please refer to j5.
The receiver has 5,356 signals (explained later).

j54 to j56 are 5IGN signals (see Figures 21, 22, and 23) related to the override value, the sign of the metered manual deviation amount, and signal switching, and j54 is [+Go and " − Signal related to the sign of ko,
55 and j56 are signals for switching data between the override value and the metered manual deviation amount for each external display and internal display.

j57 is a signal used for display during so-called preview operation (see Figures 22 and 23), in which the aperture of the lens is narrowed down and the depth of field is checked before shooting, and this signal is displayed when preview operation is being performed. is set to "High", and becomes "Low" when no preview operation is performed, and controls the flashing of the aperture mark F on the external display section 4 and the lighting of the bars of the set number chain band indication marks TA1 and TA2.

j60 is an ISO display priority signal l5OPRI. This means that the main switch SM is OFF, and OFF
Even if the LCD signal is "High" and the liquid crystal drive voltage has stopped, when this signal becomes "High", the liquid crystal drive voltage will change to the driver 24.
The 0FFV LCD signal is set to “Low” so that it is supplied to the 1-mon driver 25. (21st
(See figure) This signal is not used alone, but the data of the ISO display mode and ISO value are sent from the CPU 10 at the same time as this signal. In terms of camera operation, this is the state immediately after the battery is installed.

j6I is a blinking signal of the deviation amount of meter doma=Ufur M'dMOVEH (see Figure 22), and this signal is "Hi".
gh", the deviation value of the metered manual flashes.

j62 is the shift signal 5HIF for blinking the program mode mark during the shift of the camera's program mode.
T (see FIG. 22), and when j62 is "High", this mark blinks. Here, "soft" refers to a state in which the combination of the aperture value and the shutter speed value in the program mode is changed and operated. Incidentally, all AE modes can be blinked as needed, regardless of the program mode.

j63 is the control interlocked warning signal Not, C0NT (22nd
(see figure), and this signal goes “High” when an exposure value that exceeds the aperture value and second value that the camera can control is required.
h”, and the aperture value and/or second value flashes on the calculation control value side depending on the AE mode to issue a warning.

j64 is a brightness-linked warning signal BV (see Figure 22), and this signal becomes "High" when the brightness value exceeds the brightness value that the camera can measure, and when the light metering mode display is displayed, AS! and AS2 flashes to warn you.

j65 is the bulb time signal BULB (see Figure 21), and the camera switches the 4-digit, 7-segment display content from the bulb exposure seconds display (buLb) to the bulb exposure seconds count display. ” to display the valve count and display the contents of j40 to j47.

j66 is an all-lights-off signal ALLOFF (see Figure 21), which controls the waveform of the driving SEG terminal so that it becomes an OFF waveform (see Figure 27, 5EGn (LL)). The OFF display will appear. However, camera marks CAI and CA2 cannot be controlled.

j67 is an all-on signal ALLON (see Fig. 21), which turns all the waveforms of the SEG terminals for driving into ON waveforms (see Fig. 21).
(See Figure 5EGn(HH)).
When set to “High”, all are displayed as ON.

However, camera marks CAI and CA2 cannot be controlled.

j70. j71 is the camera operation mode signal CALL
MODE (see Figures 19, 20, and 21), normal °AE mode, main switch SM is ON.
But the camera is not working in 5TANDBY mode, I
There are four states: XSO mode for SO settings and display, and +/- mode for +/general settings and display, and the display contents are switched according to each mode. (See Figures 28 to 35)j72. j73 is the camera's AE mode signal AEMOD
E (see FIGS. 22 and 23), and has four states: program mode, aperture priority mode, shutter speed priority mode, and manual setting mode, and the display contents are switched according to each signal.

j74 is the ISO output when prompting to set the ISO value
This is a warning signal ISOARM (see FIG. 22), and when this signal becomes "High", the ISO mark and ISO value in the interior and exterior display sections 4 and 6 flash.

j75 is a mode light-off signal MODE OFF (see FIG. 23), and when this signal becomes "High", the AE mode display being displayed is turned off. Turn off the mode display when loading film into the camera.
Make it.

j76 and j77 are photometry mode switching signals AVE/5POT
(Refer to Figure 23), and when the partial metering mode is selected between the average metering mode and the partial metering mode (either or one of j76 and j77 becomes "Low"), the internal display of the viewfinder Turn on AS2 in section 6. ASI is always lit during AE mode.

DC4 also uses external signals SM and PWC as data.
j, and Nyatta second time value,
A data code converter (Fig. 23) related to the display of values outside the numerical range such as aperture value, and a decode unit (Fig. 22) related to blinking control of each display segment of the LCD display of the display unit 4.6.
and a decoding section (FIG. 21) relating to two signal switching sections SWI and SW2.

Figure 21 is created mainly with the SWI and SW2 switching signals, and the FOM, CTR, ISO, and SS signals are SWt.
, MON, +/-ON signal controls SW2. In addition, the ON and OFF signals are commands to control the CTLI and display an ON display and an OFF display for all segments. Furthermore, the 0FFVLCD signal is “H”.
The purpose of this is to prevent DC voltage from being applied to the liquid crystal when the XL2's primary oscillation is stopped, and when the main switch SM of the camera is turned off. On the other hand, j70 and j71 of the CALL MODE signal represent four camera operation modes, but when j70 and j71="High"
” is called the AE mode for normal shooting. j70・
When j71 = 'High', i for ISO sensitivity setting
so mode and y debug. When j70-j71 = ``H4gh'', it is called 5TANDBY mode in which the camera is on standby.j
70. When j71 = "High", it is called +/- mode for setting the override amount.

To explain the signals for SWl and SW2 in accordance with the above four modes (see Figure 21), in AE mode, when Wτ goes low (the camera starts operating), FON The signal becomes "High", SWI operates, aperture value information j12 to j+6 is selected, and decoded and displayed. When PWC becomes "High" (the camera enters the standby state), the FON signal becomes "Low" and the aperture value information is erased by SWI.

On the other hand, PW is "L ov" and 365 is "L ov"
At the time (normal time), the SS signal becomes "High", and the shutter time information j22 to j27 are selected and decoded and displayed. At this time, the other CTR signals and ISO signals are “L”.
ow”, and the timer count information and ISO value information are erased by SWI.

When PWC is "Low'" and j65 is "High" (during valve count), the CTR signal is "High".
Then, timer count information j40 to j47 are selected and decoded and displayed. At this time, other SS signals, 150
The signal is “°Low”, and the shutter speed information and IS
O value information is erased by SWI.

In addition, the +/-ON signal is "Loy", but the MON signal is pwc force "Loy" and j50 or j5B data is "Hi".
If it is gh', it is 'High', so the line information of the metered manual deviation amount is selected and decoded and displayed by SW2, but the line information of the override is erased.

SS, CTR, FON, MON in ISOS mode.

All the +/-ON signals are "LOW", only the ISO signal becomes "High", the SWI operates, and the ISO value information 332 to j37 are selected and decoded and displayed. At this time, other numerical bands are erased.

5 During TANDBY mode, SS, CTR, FON, I
SO, MON, 10/-ON signals are all “Low”
, all numerical bands are erased.

During +/- mode, SS, ISO, CTR, FON, M
All ON signals become “Low” and pwc becomes “L ov
”, the +/-ON signal becomes “High”.

At this time, override information j50 to j53 are selected and decoded and displayed.

Figure 22 shows a control signal for the blinking display of each display segment. When the output Bl-B8 becomes "High", if the corresponding segment (see Table 1) is lit, that segment is turned on. Flashing.

The B8 signal is a signal that causes the F mark on the external display section 4 to blink, and is mainly controlled by the j57 data.

The B7 signal is the 7th segment of the LCD of the internal display section 6.
and 8 and the COl between them, 2 is a signal that flashes the second digit, the main 1. :j55. j56. It is controlled by the data of j6■.

The B6 signal is a signal that blinks ASI and AS2 on the internal display section 6, and is mainly based on 764 data. The B5 signal is a signal that causes numbers 5 and 6 of the 7 segments, cal, and l to blink on both the external and internal display sections 4 and 6, and is mainly controlled by the j63 data.

The B4 signal is a signal that causes 7 segments 1 to 4 to flash on both the external and internal display sections 4.6, and is mainly controlled by data 363 and j74.

The B3 signal is a signal that causes both the external and internal display sections 4.6 to flash, and is mainly controlled by 362 data.

The B2 signal is a signal that causes the ISO mark on the external display section 4 to blink and is mainly controlled by 374 data.

The B1 signal is a signal that causes all of the segments other than the segments 88 to B2 to blink except for C:AI and CA2, and there is no particular data signal. However, including Bl, blinking control is performed by j20 data from 82 to B8.

23rd floor! ! J is 7 for number display on inner and outer display parts 4.6
Segments 1-8 and col, I, col,
This is a decoder for segments other than 2. Serial data j54 to j57. j70~jrs, j75~
j77, j21. The output is controlled by the external signal pwc and the decoded DC2 output signal Q40, and the outputs are up to r51-r69, and each output is “H”.
When it becomes "high", each segment corresponding to it lights up.

FIG. 9 shows SWI, which selects signals.

The input signal is an aperture value of 02 to 06, j22 to j2
Shabta second value of 7, ISO value of j32 to j37, j
The timer count values are 40 to j47, and there are FON signal, CTR signal, ISO signal, and SS signal to select each of them. When each selection signal is "High", the NAND gate opens and the output data p = input data j, while "
When “Low”, the NAND gate closes and the output data p=
It becomes “High”.

(Example) When FON=“High” Outputs p12 to p16 transmit inputs j12 to j16 as they are.

When FON="LO", all outputs p12 to p16 are "
High''?Konaru.

Next, although there are no detailed diagrams, DCI will be explained.

DCI is serial data processed by 5WII
22-j27. j32-j37. j40~j4
p22-p27, p32-p37 corresponding to 7
, p40 to p47 as inputs, and outputs data of ql-q39 corresponding to the 7-segment 4-digit part. Figure 17.

Figure 18 is for explaining the concept of DCI,
The input data is 36 kinds of shutter time values (SS values) (t+uLb-1/4000) corresponding to p22-1)27 and A
LLHigh, summer SO value 3 corresponding to p32 to p37
11 (1506-15O6400) and ALLHigh,
Timer count value (CTR
Value) 100 types (00 to 99 and A L High).

For example, data p27~corresponding to SS value rbuLbJ
When p22="LLLLLL" is input (other data p32 to p37.p40 to p47 at that time are A L L
Processed with DC4 and SWI to make it High.

) Output data is q for segment decoder SDI.
'7 data "b", q18 data for SD2 "
Q29 data is "U" for L' and SD3, and q39 data is "b" for SD4.

Also, data p37 to p corresponding to rso value r200J
32="LHHHLL" is input, other data p22 to p27.32 at that time is input. p40-p47 are ALLHigh
Processed with DC4 and SWI to make it look like this. ) The output data is ql data for segment decoder SDI, q8 data for SD2, and q2 data for SD3.
1 data, and no data is output to SD4.

Also, p22-p27. p32-p37. p40~M
When all 7 are “High”, segment decoder 5
There is no output to DI-5D4.

All segments for 5DI-SD4 are turned off.

It is composed of a gate circuit having the above configuration.
First, segment decoders SDI to SD4 shown in FIG. 13 will be explained. The data signals Ql to q39 obtained in the previous section are respectively qt-q7
98 to +118 to DI is 5D21, q19 to (129
is input to SD3, and q30-q39 are input to SD4. 5D
The inside of I-8D4 is basically the same, but among the 14 terminals, the terminals to which the corresponding data signals are not input are
Each block is pulled up to the power supply side. This circuit is configured so that when the input becomes "Low", a valid output can be obtained. For example, when the q7 data signal (b of buLb) is output for SDI, the ITJ power is Low''
At this time, other SDI inputs ql-q6 and the input being pulled up are “High”, but “Lo”
Outputs (c), (d), related to the line that became t”
(e), (D, (g) are all 'High' and the other (a), (b), (h) lines are 'Low'. This output (c), (d), (e ), (f),
(g) corresponds to SDI terminals r3 to r7, which are connected to the next stage CTL I and connected to the liquid crystal display. This r output corresponds approximately to the liquid crystal segment (see FIG. 16a, FIGS. 2 and 2C, and Table 2). Output here (c), (d), (e),
(D.

(g) each corresponds to the numerical segment name of the 7 segments and represents the character "6" (see 2nd v! Jb).

Furthermore, for example, q21 data signal (r2
When J) is output, the "2" input becomes "°Low" (a).

(b), (d), (e), (g) are 'High'
Then the character "2" will be displayed.

1112 to I)16 obtained by SWI enter the decoder DC2 shown in FIG. p16~l)+2=“LLLL
The output at LL is q40, which is a "Low" output. The output of q40 goes to segment decoder SD5 while it goes to decoder DC4.

Other outputs are exclusively connected to SD5.

The contents of the outputs of q40 to Q62 based on the data of 912 to p16 include 23 types of aperture values shown in the concept of SD5 shown in FIGS. 19 and 20. These are segment decoded by a part of SD5 (manual power section q40 to q62) shown in FIG. 15, and outputs r30 to r43 are obtained.

For data j50 to j53, decoder D in FIG.
There is C3. j50 data is decimal data,
A p1 output and a p2 output are obtained.

The j51-j53 data represents information from 0 to 6, and the outputs are p3 to p9, and the output is "High" and becomes active. This output is input to the switch SW2 in FIG. 12, and the output light is switched according to the selection information MON, +/-ON. When MON is “H, high”, +/-ON is “L”
ov", and the outputs of p2 to p9 are inverted and 482
~q89, but all q71-478 are “H”
becomes “High”.-Sumo wrestler/-When ON is “High”,
MON is Low', and the output of pi-p7 is inverted and output to 471 to q77, but all of 482 to Q89 become "High". Also, q78 is “Low”
It is. When both MON and +/-ON are “Lot”, all outputs of q71-Q78゜q82 to q89 are High.
"become.

The output of SW2 is q71-Q78 to SD5, q82 to q
89 is output to SD6.

q71-q78. output by SW2. q82~Q89
The contents are q71 to q78 as shown in Figures 19 and 20.
is 7 kinds of numerical values for override value and 1 kind of decimal point, q82
~q89 corresponds to seven types of integer digit numerical values for metered manual values (including override values) and one type of decimal display.

Although the contents of SD6 are not shown, the basic idea is the same as that of SDI to SD4 in FIG. 13, and is shown in FIG.

The gate configuration is such that there is a relationship between the data shown in FIG. 20 and the output display example.

Finally, r made by 5DI-SD6 and DC4
l=r69 and Bl~B8. When ON, OFF signals and φ14 clock are input, output control section C
TLI will be explained.

The internal configuration of CTL l is already shown in Figure I6.

r69 →S69. Except for the configuration of the S70 portion, the configuration is basically as shown in FIG. 16a. First, in Figure 16, when a 'High' signal is input to r69, S69
The gate for 870 opens and repeats "High" and "Low" by the clock of φ141°, but S69
and S70 are output in reverse phase. This way, the corresponding CA
The I and CA2 marks light up alternately, giving the impression that the camera mark is blurring. Regarding circuits for signals other than r69, logical expressions and truth tables showing the relationship between the output S and the input r are shown in Table 1.

As shown in this table, when the surface signal becomes "Low", the output S becomes S69. All except S70 become 'High' and all the display contents except CAI and CA2 light up.

Next, when the δN signal is “High”, the OFF signal is “
When it becomes "High", all outputs S except S69 and S70 become "Low", and all the displays except CAI and CA2 turn off.

When the δN signal is “High” and the OFF signal is “Low”, if B-0 (Bl-88) becomes “LOW”, the output S
=r, and the display is lit according to the display information given by the serial data.

ON signal is “High”, OFF signal is “Low”,
When any part of Ba (Bl to B8) becomes “High” by DC4, r in the same group will be determined according to the combination of B and r under the truth table in Table 1.
The output S corresponding to .phi., 4 flashes according to the display contents at that time in accordance with the clock of .phi.,4.

For example, when the B6 signal is "High" and the other B1 to B
5. B7. When the B8 signal is 'Low', the corresponding outputs S59 and S of r59 and r60 in the B6 signal group
60 repeats "High" and "Low".

However, when the states of r59 and r60 are "Low", S59 and 960 cannot become "High". Therefore, As2 and AS corresponding to S59 and S60
If I is lit, it will change to flashing.

The outputs 5l-870 obtained from the above CTL 1 are inputted to each segment driver (Fig. 6) and output as a liquid crystal drive waveform (see Fig. 27) to the final output SEG terminal (SEGI-SEG35). Ru.

The relationship between the CTL1 output S and the SEG terminal is shown in Table 2.

The names of the segments shown in this table are Figure 2b and 2Ec7.
This is the same name as all the segment diagrams shown here.

1. When starting the camera: When the camera is started by turning on the main switch SM, an interrupt is generated in the CPU10, the CPU10 is released from the stopped state, and the camera starts operating according to the program in the internal ROM. At the same time, voltage is supplied to a photometric circuit (not shown), etc., but it takes several +1 seconds for the photometric circuit, etc. to operate reliably and provide the necessary data to the CPU 10. .

However, the CPU 10, which operates at high speed, has communicated serial data with the display circuit section one or more times at this point. The contents of serial data communication (see Figure 36) mainly include exposure information such as shutter speed and aperture value, but when the photometering circuit etc. is not operating normally, it is difficult to confirm the accuracy of this exposure information. No value is obtained. Therefore, it is not good to carry out serial data communication in this state because it not only has no meaning but also causes erroneous display. Therefore, at startup, until the CPU10 takes in accurate information and completes the calculation, a troublesome inaccurate value is displayed on the display by sending data for turning off the light or data for standby display. You can make things go away. The display section of the embodiment has a structure in which the previous display is maintained unless new serial data communication occurs. There is no particular problem until the calculation is completed using this - as long as there is no serial data communication, but since the program flow of the CPU10 program is designed to avoid exceptions as much as possible, serial The method of data communication is better in the sense that it does not increase the capacity of the ROM for programming. Therefore, the above method becomes better.

Immediately after the battery is installed in the camera, a voltage of 10 E is applied to the CPU 10 and the display circuit section 20, and each starts operating. Each circuit has separate crystal oscillators XLI and XL2.
, and starts operating independently, but in this case, XLI
Generally speaking, XL has a higher frequency than XL2.
I starts oscillating early. After starting oscillation, CPU10 starts operating according to the program in the internal ROM. However, since there is little work to be done immediately after installing the battery, it takes several tens of seconds.
It goes into a suspended state and stops functioning, waiting for it to be woken up again. Generally, at this point, the oscillation of XL2 of the display circuit 1120 rises (generally 100ssec-1sec)
c) is not guaranteed. When XL2 of the display section is not oscillating, serial data communication with CPU10 is not received, and the clock φ shown in FIG. 7 is not generated, so the operation is as shown in the time chart shown in FIG. 26. LTCH pulse will not be generated unless Furthermore, even if XL2 is oscillating, the data in the display circuit section 20 is not rewritten unless there is serial data communication. (Since PWC, C8, 5DATA, and SCK in Fig.
does not occur, and no LTCH pulse occurs. ), the operation of the CPU 10 as described above is not good because the display content continues to be an indefinite display of the battery installed state. Therefore, the 7th part of this circuit
Figure j10 reset, j11 set, Figure 24, Figure 25
One countermeasure is to prevent the initial indefinite display by turning off the power for driving the LCD using a power-on reset circuit as shown in the figure. Furthermore, if the power-on reset circuit does not work for some reason, or if it is not good for the display to remain off, continue serial data communication from CPU10 until the guaranteed time for the XL2 oscillation to rise after the battery is installed. As soon as the oscillation of XL2 starts, normal operation starts and the display contents change immediately. The contents of the soreal data at this time may be data for turning off the light, data for standby display, or any other arbitrary data.

Therefore, the operation of CP[J is to perform serial data communication using display data from the time it performs necessary processing immediately after battery installation until the guaranteed start-up time of XL2 oscillation, and after a predetermined period of time has elapsed, If not, it will go into a stopped state and stop functioning. However, the CPU 1O must prohibit interrupt operations during the guaranteed rise time of the XL2 oscillation.

- Display during preview operation - When the preview operation is performed, the lens is narrowed down and the photographer can check the depth of field, but at the same time, a display indicating the preview operation is displayed to notify the photographer that the preview operation is in progress. Inform. To display this preview behavior,
This is done by changing the display state of the mark related to the aperture of the camera (for example, as shown in FIG. 45, by blinking the aperture mark F, which is normally lit, on the external display section 4).

Now, the display control unit 20 is sent out from the CPU10.

The display of the display section 4.6 is driven based on the displayed display data (step 818 in FIG. 18), and these data include data indicating whether or not to display a preview operation. In other words, as the j57 signal, data that is "Low" when no preview operation is performed and "High" when a preview operation is performed is sent to the CPUI.
Sent from G. The data converter DC4 is configured so that the control signal B8 that controls the blinking display of the aperture mark F, which is normally lit, is controlled by the signal j57 (Fig. 22), and when j57 is "High", the control signal B8 is controlled by the signal j57. is “H”
In other words, when the preview operation is being performed, the control signal 88 h4 becomes "High", and the aperture mark F blinks during the preview operation. In this way, the characters or symbols related to the camera aperture are By changing the display state from lighting to blinking, for example, it is possible to clearly notify the photographer that the preview operation is in progress.

- Before CPU1G stops - Immediately before CPUIO stops its operation, CPU10 sends standby mode display data to the display. After that, until CPU10 is activated again, there is no data transfer, so the display remains unchanged and the standby mode display continues. Immediately before the main switch SM is turned off and the CPU10 stops operating, CPU10 sends the display data for the light-off mode to the display in the same manner as described above. After that, there is no data transfer until the main switch SM is turned on again, so the display remains unchanged and continues to be in an unlit state.
Sea ALLON and ALLOFF- Serial data jl O, jl 1 are the most priority data that cut LCD [j[ from its roots.

jlO・Turns off when H1=“High”.

On the other hand, data 366 and j67 are prepared for connection checking and are second priority data. j67=
A waveform in which all segments light up when “High”,
When j66 = 'Low', a waveform in which all segments are turned off is output from the COM and SEG terminals.When each waveform is applied to a properly connected LCD, it will be displayed whether all the lights are on or all off. However, if the connection with the LCD is misaligned, a part of the LCD may be off or on, or the brightness may be different from other segments, which clearly indicates a connection error. become.

Also, as a method of providing signals for serial data communication, 5DA
By connecting the TA line to +E through a small resistor, that is, pulling it up, all serial data is
It becomes High@ information, the priority bit j67 becomes active, and the all-lighting mode is activated. On the other hand, if you pull it down by connecting it to GND, all the serial data will be '
"Low" information, the priority bit 36B comes alive, and the all-lights-out mode is activated.This is a very easy check that can be done even after the camera is assembled.

Furthermore, there is no need to provide a dedicated terminal, which is ideal.

- Off mode and standby mode - Fig. 35 shows the display on the external display section 4 in standby mode. Only the bar is lit and all other external and internal displays are turned off. As the camera body, the CPU
l0 is in a stopped state and is waiting for an input corresponding to an interrupt instruction. Further, although power is supplied to the display circuit 20, no power is supplied to any other circuits (not shown) other than the CPU10. However, when an interrupt input such as a photometry switch is input to the CPU10, power is supplied, other circuits start working, and the camera function starts.

On the other hand, the display in the lights-out mode turns off all displays.

The method is to use OFFV LC to turn off the liquid crystal drive power.
Set D to “High”. At this time, the camera main body operates only in a stopped state in which the CPU 10 waits for an input interrupt from the SM terminal, and power is not supplied to any other circuits except for the display circuit (not shown).

The difference between standby mode and lights-out mode as a camera is that in lights-out mode, only the main switch SM is active. On the other hand, in the standby mode, other operation start switches such as a photometric switch (not shown) come into play. Further, the current consumption is lower in the off mode, which is energy saving, and the voltage applied to the liquid crystal is zero in the off mode, so the liquid crystal has a good shelf life.

- Manually configurable data indication marks - Figure 29 a, b
In the A mode, since the aperture can be set, the black mark TA2 on the aperture value side is lit, and the black mark TAI on the Nyatta second side, which cannot be set, is turned off.

Similarly, in the S mode, that is, the shutter priority mode shown in Fig. 30a and b, since the shutter speed can be set, the red mark TAI on the shutter speed side is lit, and the gray mark TAI on the side of the aperture value, which cannot be set, is lit. Mark TA2 goes out.

In FIGS. 31a and 31b, in manual (M) mode, since both values can be set, both 4 marks TA1. TA2
lights up to indicate that both can be set.

In the P mode shown in FIG. 28, since there are no numerical values that can be set, both marks are turned off to clearly indicate their meaning.

Please note that these marks can be turned on or off using j72. Control is performed using the AE monid information provided by j73 as is.

However, if the function for determining the presence or absence of a lens (not shown) determines that there is no re-lens, the aperture of the lens cannot be set. Therefore, in this case, the setting mark TA2 regarding the aperture is specially set not to light up regardless of the mode. This is controlled by the q40 signal shown in FIG.

1 Open F value display -, 1 The aperture value display is a 7-segment numerical display as shown in FIGS. 28 to 31. The contents of the aperture value are shown in FIG. Here, the r q40 J signal indicates a state equivalent to no lens by displaying -1. rq43J to rq62J is 0.5
is the aperture value (rounded to each EV). On the other hand, the lens opening F number is 3, 5, and 4.5, which have been popular for a long time.
There are numbers such as

However, since these are values that are not multiplied by the aperture value for every 0.5 EV, these values are treated as special and prepared as rq41J and rq42J signals. In this way, the result of the calculation performed by CPU10 or the set aperture value is the aperture value (determination is made by an unillustrated aperture signal), and furthermore, 3. - When the value is 5 or 4.5, a display signal is given from the CPU10 to display 3.5 or 4.5 instead of the normal display of 3.4 or 4.8. Also, CPU1O
When the result of the calculation or the set aperture value is not the open value, the normal display such as 3.4 or 48 is used for display.

The above two series of display formats are provided.

As an example, FIGS. 33a and 33b show display examples of the open F value.

The open F value is determined, for example, as follows.

As shown in FIG. 40, in step S1, the control CPU10
reads the open F value Avo from the lens 3 and stores it in an internal register. On the other hand, CPU10 uses the calculated F value Ay calculated in step S2 based on the camera settings and the value obtained from the photometry results, and in step S3, Avo=Av.
If Avo=Av, take out the open FllAvo (step S4), and if Avo≠Av, calculate the F value A
Step S5) rounding v to 0.5Ev
,j! 2 to [6 data (AVDSP) are determined, and the extracted outputs are displayed on display units 4 and 6 (step S6
).

-Combined display of override indicator and metered manual amount- The +6.5 in Figure 31 is the deviation amount of the metered manual, and it is always lit during the manual mode, which is the only internal display of the infinder. The displayed range is +6.5
~-6.5 EV (see Fig. 20), and when that amount is exceeded, +6.5 and -6.5 are displayed blinking. As data during blinking, M'dMOVER of j61 data is set to "High".

Also, Figure 33 Suno+! 5 is the oval ride amount,
It always appears depending on the setting when in AE mode other than manual mode. Similarly, only the internal display of the infinder is displayed.

The displayed range is +4.0 to -4.0 EV (see Figure 20), and settings cannot be made beyond that amount. Here, the override display is constantly flashing to distinguish it from the metered manual, and at the same time draws attention to the override setting.

On the external display, +/- symbols (OR+,
OR-, 0RS) lights up, but in metered manual mode the +/- signs (OR+, OR-) light up.

0RS) is turned off and not displayed.

In order to receive and receive the data for each quantity of override and metered manual using the same renostar,
A separate identification signal is required.

This signal is provided by the 5IGN signal of the data 54 to 56.

Table 3 shows the relationship between the contents of data 354 to 356 and their output display states. This makes the portions j54 to j56 of FIGS. 21 to 23 easier to understand.

-8 and A mode display- The display mode is shown in FIGS. 29 and 30.

The 29th vlJb is a display in the A mode, and the A mode display section with an arrow pointing toward the display of the manually settable aperture value is lit. FIG. 30 shows the display in the S mode, in which the S mode display section with an arrow pointing toward the display of the shutter speed value, which can be manually set, is lit. By doing this, the meaning of the mode display and the meaning of the numerical display can be understood at a glance, making the mode display very easy to use.

Figures 38a and 38b show the display contents at the time of initial loading after mounting the film. initial load
When the film is not fed during the ν period, 1
It is controlled with a shutter speed of 74,000 seconds and a minimum aperture value (F22 in this case). At that time, all exposure mode displays have disappeared, but this is because the j75 bit is set to “H”.
igh” and the mode display is turned off.

Figures 39a and 39b show the display contents when the lens is not attached. When the CPU 10 detects that there is no lens by a mechanism not shown, all of the display signals j12 to j16 are set to "Low". This is done in step 818 of the flowchart of FIG. 41, and the display decoder that receives this outputs the 940 signal of FIG. 20 and F62 of FIG.
Therefore, the aperture value will be displayed, and the aperture chain side mark T of the settable marks will be displayed.
A2 disappears.

Note that FIG. 42 shows another embodiment in which camera shake is displayed on the internal display section 6. In this case, as shown in (a) in the figure, it is composed of three segments, and the type of camera is indicated by lighting two of these segments. This 2
There are two types of segment selection, (b) and (C), and camera shake is displayed by turning on 2N alternately.

FIG. 41 shows an outline of the operation of the control CPU10.

By installing the battery, the CPU 10 starts operating from a reset start (step SO). At the same time, voltage is also applied to the display circuit. First, in CPU10.

Perform initial settings for both cameras (step 510)
Then, display data, turn-off data, standby data, ISO data, etc. are sent out once for the display circuit (step 5ll). (n is a value determined depending on the time it takes for the display circuit to guarantee normal operation) When the transmission is finished, interrupts from a switch group (not shown) are permitted (step 5I2)
. If there is no problem, the internal operation clock is stopped and the system enters a stopped state (step 513). Among the switch groups not shown, the photometric switch 81 or the initial rotor switch SB has a relationship with the main switch SM as shown in FIG. 44, and the other switch groups have the same configuration as SL and SB. When the main switch SM is OFF, the SL and SB large inputs are pulled down and the SL.

SB large input is dead. In this state, only the SM signal generates the INTset signal that generates an interrupt. When the main switch SM is turned on and an IN
4) Enter. This INT flip-flop is set at the rising edge, enabling interrupts (step S+
2), the INT flip-flop is reset and waits for another interrupt.

Now, when entering INT (step 5I4), check the switch SB that detects the initial load state (step 515), and if it is 0FF (not in the initial state), power is supplied to the photometering circuit (not shown), etc., and step SI6 Start metering. After that, in step S17, the AE
The calculation is performed, display data necessary for the display circuit is prepared, and sent out in step St8. Thereafter, the main switch SM is checked in step S19, and if it is OFF, data for turning off the light is sent out as display DATA in step S20, power supply is stopped, and photometry is stopped in step S21. After that, step S+2. Proceed to S13. If the main switch SM is ON in step S19, the switch SL is checked (step S26) L; if it is OFF, data for standby display is sent out as display DATA, and step SI6. S21. Proceed to SI2,513. Further, if it is turned on in step 826, the release switch 52 is checked in step S22. If it is ON, exposure control (step 523) is performed, and step S
Proceed to I7, but if it is OFF, do nothing and go to step S+7
Proceed to step 3 and perform the AE calculation again.

On the other hand, if the switch SB for detecting the initial load state is ON in step 515, the second value and aperture value for initial load and MODE OFF information 5 data = "High" are sent out in step S24. Then, an initial load is performed to control the shutter mechanism using the seconds value and aperture value (step 525). Thereafter, in step S15, the switch SB is checked again, and depending on the state of the switch SB, the photometry (photometry) starts in step SI6.

The transition from step S13 to SI4 depends on the SM, SL, and SH switches, as shown in FIG.
At F, the Sl and SB switches are in the "Low" state and are dead as switch signals. Therefore, S.M.
The INT Set signal is generated only when the INT is turned on, and the interrupt (INT) operation starts. Also, when SM is ON, Sl
, SB switch comes alive and IN by SL or SB
The Tset signal is generated and interrupt (INT) operation begins.

Although not shown, the SB switch is turned on when it detects the presence of film and that the back lid is closed, and turned off when a film counter (not shown) reaches 1.

FIG. 43 is a flowchart showing the operation for detecting camera shake. In step S31, the CPU 10 reads necessary information such as focal length from the lens. Then, in step S32, a TV value for image stabilization control is calculated by exposure calculation, and a TVL value for camera shake warning limit is calculated from lens information. Then, in step S33, TV and T
Comparing the size with VL, if TV<TVL, YES is returned to step S34, and if TV and -TV L, NO is returned to step S35. In step S34, LOWSS
The signal is set to "High", the marks CAI and CA2 are vibrated to issue a camera shake warning, and in step S35, the signal is set to LOWS.
Set the S signal to "Lov" and mark CA1. Turn off CA2.

FIG. 44 shows CPU10 and switch S1. S2゜SR,S
Indicates the relationship with M.

Table 1 <Combinations of r2n and Ba> Bl -r51 to r53. r61~r65B2 -r
54 B3-r55-r58. r67, r68B4-r
l ~ r29 B5 - r3 (1-r43 B6 - r59. r60 B7 - r44 ~ r50 B8 - r66 Table 2 Table 2 (continued) Table 2 (continued) [Effects of the invention] As detailed above, During preview operation, this invention
Since the display state of the portion displaying characters or symbols related to the aperture changes, the preview operation can be clearly shown to the user.

[Brief explanation of drawings]

FIG. 1a is a flowchart showing the operation of the main parts of the display device of the present invention. Jb is a perspective view showing an example of a camera to which the present invention is applied, FIG. 2a is a front view of the finder of the camera shown in FIG. 1, and FIG. FIG. 2C is a diagram showing an example of all segments displayed on the internal display section of the display device of the present invention. FIG. 3 is a block diagram showing an example of an embodiment of the present invention. , Fig. 4 is a detailed circuit diagram of the oscillation divider section in Fig. 3, Fig. 5 is a detailed circuit diagram of the common driver in Fig. 3, and Fig. 6 is a detailed circuit diagram of the segment driver in Fig. 3. , Figure 7 shows the design of Figure 3.
1-Detailed circuit diagram of the clutch section, No. 8
The figure shows a detailed circuit diagram of the decoder section in Fig. 3, and Fig. 9 shows the detailed circuit diagram of the decoder section in Fig. 8.
10 is a circuit diagram showing details of symbols in the circuit, FIG. 11 is a detailed circuit diagram of the data conversion section, and FIG. 12 is a detailed circuit diagram of the switch circuit SWI in FIG. 8.
13, 14 and 15 are detailed circuit diagrams of the segment decoder of FIG. 8, and FIG. 16a is a detailed circuit diagram of the output control section of FIG. 8. 1
Figure 6 is a detailed circuit diagram of a part of the circuit in Figure 8, Figures 17 to 20 are diagrams showing the relationship between input signals and displays, and Figures 21 to 23 are data in Figure 8. 24 is a detailed circuit diagram of the voltage generating section of FIG. 3, FIGS. 25 to 27 are waveform diagrams of the main parts of the circuit of FIG. 3, and FIG. 28a, Figures 28-34a, 34
35 is a diagram showing various aspects of display, FIG. 36 is a diagram showing the relationship between signals and registers, and FIG. 37 a, b,
c, Figures 38a and b, and Figures 39a and b show various aspects of the display; Figure 40 shows the CPU display selection operation;
FIG. 41 is a flowchart showing the operation of the CPU in FIG. 3. FIG. 42 is a flowchart showing another aspect of camera shake display, and FIG.
FIG. 44 is a circuit diagram showing details of a part of the CPU shown in FIG. 3, and FIG. 45 is a diagram showing an example of a display during a preview operation. 4... External display section, 6... Internal display section, 10...
CPU, 22...Data latch, 23...Decoder, 24...Segment driver.

Claims (1)

[Claims] (1) A display means for displaying characters or symbols related to the aperture of the camera, a preview detection means for detecting a preview, and changing the display state of the display means when it is detected that a preview operation is being performed. A display device for a camera, comprising a control means.