JPS61139041U - - Google Patents
Info
- Publication number
- JPS61139041U JPS61139041U JP2138785U JP2138785U JPS61139041U JP S61139041 U JPS61139041 U JP S61139041U JP 2138785 U JP2138785 U JP 2138785U JP 2138785 U JP2138785 U JP 2138785U JP S61139041 U JPS61139041 U JP S61139041U
- Authority
- JP
- Japan
- Prior art keywords
- transformer
- input
- output
- output signal
- whose
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Transceivers (AREA)
- Telephone Set Structure (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
図面は本考案に係る電話装置の送受信回路を示
す図である。
1はトランス、3は送信用トランジスタ、4は
受信用トランジスタ、9は加算手段。
The drawing is a diagram showing a transmitting and receiving circuit of a telephone device according to the present invention. 1 is a transformer, 3 is a transmitting transistor, 4 is a receiving transistor, and 9 is an adding means.
Claims (1)
夫々接続されたトランスと、入力側に送信信号が
印加され、出力側より出力される第1の出力信号
が前記トランジスの2次側に印加される送信用ト
ランジスタと、入力側が前記トランスの2次側に
接続され、出力側より電話回線を介して入力され
た受信信号を得る受信用トランジスタと、前記送
信用トランジスタより出力される前記第1の出力
信号とこれと逆相の第2の出力信号とを加算して
前記送信用トランジスタの入力側に印加する加算
手段とよりなる電話装置の送受信回路。 A transformer whose primary side is connected to a telephone line side and whose secondary side is connected to a telephone device side, a transmission signal is applied to the input side, and a first output signal outputted from the output side is connected to the secondary side of the transformer. a receiving transistor whose input side is connected to the secondary side of the transformer and obtains a received signal input from the output side via the telephone line; 1. A transmitting/receiving circuit for a telephone device, comprising an adding means for adding a first output signal and a second output signal having an opposite phase thereto and applying the resultant to the input side of the transmitting transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2138785U JPS61139041U (en) | 1985-02-18 | 1985-02-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2138785U JPS61139041U (en) | 1985-02-18 | 1985-02-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61139041U true JPS61139041U (en) | 1986-08-28 |
Family
ID=30512733
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2138785U Pending JPS61139041U (en) | 1985-02-18 | 1985-02-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61139041U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012138680A (en) * | 2010-12-24 | 2012-07-19 | Sony Corp | Full duplex transmission circuit and electronic apparatus |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5168708A (en) * | 1974-12-11 | 1976-06-14 | Ricoh Kk |
-
1985
- 1985-02-18 JP JP2138785U patent/JPS61139041U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5168708A (en) * | 1974-12-11 | 1976-06-14 | Ricoh Kk |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012138680A (en) * | 2010-12-24 | 2012-07-19 | Sony Corp | Full duplex transmission circuit and electronic apparatus |
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