JPS61138055U - - Google Patents
Info
- Publication number
- JPS61138055U JPS61138055U JP2036485U JP2036485U JPS61138055U JP S61138055 U JPS61138055 U JP S61138055U JP 2036485 U JP2036485 U JP 2036485U JP 2036485 U JP2036485 U JP 2036485U JP S61138055 U JPS61138055 U JP S61138055U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- timer
- cpu
- protection circuit
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004913 activation Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
- Safety Devices In Control Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2036485U JPS61138055U (bs) | 1985-02-15 | 1985-02-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2036485U JPS61138055U (bs) | 1985-02-15 | 1985-02-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61138055U true JPS61138055U (bs) | 1986-08-27 |
Family
ID=30510781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2036485U Pending JPS61138055U (bs) | 1985-02-15 | 1985-02-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61138055U (bs) |
-
1985
- 1985-02-15 JP JP2036485U patent/JPS61138055U/ja active Pending