JPS61137365A - Phototrigger photoquench static induction thyristor - Google Patents

Abstract

PURPOSE:To efficiently DC/AC-convert a large power at a high speed while reducing the number of parts by forming a phototrigger photoquenching SI thyristor, an MISFET for controlling the thyristor and a bipolar transistor. CONSTITUTION:An N<-> type layer 102 is epitaxially grown on a P<+> type anode region 101 having an anode electrode 131 on the back surface, a plurality of P<+> type gate regions 105 are buried at one end of the layer 102, an N<+> type cathode region is diffused on the surface of the layer 103, and cathode electrodes 132 are mounted at both ends to use the regions as a thyristor. A recess is formed in the layer 102 adjacent thereto, all of the inner wall in coated by a dielectric film 110, an N<-> type layer 111 is buried here, an N type region 113 and a P<+> type region 112, 114 are formed here to form a photoquenching MISFET. Further, the region 114 is commonly used, and a bipolar transistor is composed of the region 114, an N type region 116, and a P<+> type region 115.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a static induction thyristor (5tatic ind. thyristor).
The present invention relates to an integrated structure of a photo-triggerable/photo-quenchable thyristor by the ucLion Thyristor (hereinafter abbreviated as SI Psi-Sk). High power can be orthogonally converted at high speed and with high efficiency using only a rrRIu bias circuit, a trigger frequency optical pulse, and a quenching optical pulse.The control circuit and the high power section can be completely separated, and furthermore, it can be easily performed using conventional semiconductor manufacturing processes. Since it can be manufactured in a number of minutes, it is used in large power converters, etc.

[Conventional technology]

The on/off operation of an SI thyristor by light has already been proposed by the inventor of the present invention, and is disclosed in Japanese Patent Application No. 8-36079 (Japanese Unexamined Patent Publication No. 55-12870), "Electrostatic Induction Thyristor and Semiconductor Device", Japanese Patent Application No. 59 No. 54937 “Light-quenchable thyristor device j, filed August 22, 1980”
"Light-triggered/light-quenched electrostatic induction thyristor" and 1930
It is disclosed in the application "Light-triggered/light-quenched electrostatic induction thyristor" filed on August 25, 1999. An example of an integrated structure is a vertical electric induction bottom transistor (5tatic induction phototransistor) as a photosensitive element
Ansistor, hereinafter abbreviated as SI phototransistor. ) integrated direct optical trigger and optical quench Sl
A thyristor is proposed in the above-mentioned Japanese Patent Application No. 59-54937 entitled "Light Quenchable Thyristor Device". Also,
As a trigger photosensitive element, a vertical Sl phototransistor or a vertical electrostatic induction photothyristor (5tatic I
duction Photo Thyristor
, hereinafter abbreviated as sr photothyristor. ),
Vertical SI phototransistor, vertical SI photothyristor, vertical SIT and drive S as photosensitive elements for quenching
■Indirect optical trigger/optical quench SI that integrates phototransnostar, vertical SI photothyristor, SI phototransistor for drive, SI phototransistor for quenching, etc.
A thyristor has been proposed in the above-mentioned application filed on August 25, 1982 titled "Light-triggered/light-quenched electrostatic induction thyristor."

FIG. 10 of the present invention is shown in the above-mentioned Japanese Patent Application No. 59-54937.
This is an example of the structure of a direct light trigger/light quench Sl thyristor proposed for "light quenchable thyristor device". A single gate type SI thyristor with an SIT gate structure and a vertical S phototransistor are integrated on the same substrate on the second base, and the sources of the single gate type Sl thyristor and the SI phototransistor are electrically common. It is characterized by (to do).

[Problem that the invention seeks to solve]

Examples of integrated structures proposed in the above-mentioned Japanese Patent Application No. 59-54937 "Light-quenchable thyristor device" and the above-mentioned application "Light-triggered/light-quenched electrostatic induction thyristor device" filed on August 25, 1982 ( The SI phototransistor for photoquenching and the SIT for photoquenching are all vertical planar gate structures.Furthermore, the SIT is used as a surface p+ region drain.

To quickly quench the main SI thyristor, the main 81
Although it is necessary to set the gate of the thyristor to a negative number, it is necessary to apply a negative number to the gate of the thyristor. In the integrated structure proposed for "inductive thyristors", the negative bias voltage applied to the gate of the main 81 thyristor is not the gate-cathode withstand voltage of the main SI thyristor, but the voltage quenching S
It is limited by the characteristics of the phototransistor or SIT for photoquenching. That is, in the vertical planar gate structure shown in FIG. 10, the S
In IT, the withstand voltage between the source and the drain and between the gate and the drain cannot be made very large, so a negative voltage comparable to the withstand voltage between the gate and the cathode of the main 81 thyristor cannot be applied to the gate of the main SI thyristor. This limits the quench speed.

In addition, the integrated structure examples proposed in the above-mentioned Japanese Patent Application No. 59-54937 "Light-quenchable thyristor device" and the above-mentioned application filed on August 25, 1989 (Light-triggered/light-quenched electrostatic induction thyristor) are as follows: All are composed of junction type SIT or Sl thyristors. Therefore, the operating speed of the SIT for optical quenching or the Sl phototranostar for optical quenching is limited due to the accumulation effect of carriers.

Further, when operating the light quenching SIT with the gate biased in the forward direction, a large current must be supplied to the gate of the SIT.

In particular, when driving SIT with light, the current supplied is much smaller than that which can be supplied electrically.
This becomes a problem.

[Means for solving problems]

In order to solve the above problems, the present invention uses an insulated gate field effect transistor (hereinafter referred to as M) as a light quenching element.
ISFET) or insulated gate static induction transistor (hereinafter MISSIT) and MISF
We propose a circuit format and an integrated structure using bipolar phototransistors (hereinafter abbreviated as BPT) or S-phototransistors/transistors for driving ETs or MISSITs.

Integration of bipolar type semiconductor devices and insulated gate type semiconductor devices has been carried out for a long time and can be manufactured relatively easily.

Furthermore, by using an insulated gate type semiconductor element as a light quenching element, it can be driven with a smaller current than a junction type, and furthermore, there is no minority carrier accumulation effect, so high-speed operation can be realized.

Furthermore, the breakdown voltage between the gate and the source, between the gate electrode and the drain can be increased.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a phototrigger/photoquench St thyristor according to the present invention, in which an insulated gate field effect transistor (hereinafter abbreviated as MISFET) is used as a photosensitive element for photoquenching.
An embodiment using a piebola phototransistor (hereinafter abbreviated as BPT) for driving a MISFET and a MISFET will be described.

In FIG. 1, the main Sl thyristor includes an l'' anode region 101, an n-low impurity density region 102, 103, and an n
It is composed of a +cando region 104 and a p+ agate region 105. p+ anode region 101 and one gate region 1
05 has an anode electrode 131. A gate electrode 133 is provided respectively. In addition, a cando electrode 132 is provided in a part of the surface-electrode region of the Yakado region.
is provided. A part of the surface-electrode portion of the n+ cathode region has no electrode, which prevents the trigger light from penetrating into the main Sl thyristor.

MISFET and its M as a photosensitive element for light quenching
The BPT for driving the ISFET has the first dielectric region
High resistance n-region 11 electrically isolated from surroundings at 0
It is located inside. The MOS transistor includes a 12th source region, a 13th IJ region, an 11th n-region, and a 13th n-region.
+ A gate electrode 135 provided on the 14th drain region and the 13th n region via a gate oxide film, a source electrode 136 connected to the gate electrode of the main 31 thyristor, and the drain electrode 134 and the electrode of the n region. 137. The BPT for driving the MISFET is p
+ emitter region 15th, n base region 16th, p+ collector region 1st which is common to the "region and the drain of MISFET"
4, an emitter electrode 138 connected to the gate electrode 135 of the MISFET, a collector electrode 134 common to the drain electrode of the MISFET, and a base electrode 139.

The area between the gate and cathode of the main Sl thyristor is etched into a bevel shape to improve the withstand voltage.

In practice, for example, the impurity density is 1 to 2X IQ"z-3,
A door gate area (
Impurity density 1.5~2 x 10"clR-', thickness 1
In this method, a spacing of 3.5 μm between the anode and the p+ gate is provided, and a low impurity density region of approximately 10 μm is created between the gate and the cathode by epitaxial growth.
A cathode-to-cathode element voltage of 2500V and a gate-to-cando breakdown voltage of 180V were obtained.

Further, the insulating film 171 on the surface is generally made of oxide, but may be an insulating film such as a nitride film.

Next, the operation of the optical trigger/optical quench+SI thyristor shown in FIG. 1 will be explained. Usually, the cathode of the main Sl thyristor is grounded, and the anode A is connected to an anode bias voltage Vat via a load. MISFE
The drain of T (collector of BPT) has a negative voltage VD
153' biased. The value of the negative voltage vD153 is determined by the main Sl
The gate bias of the thyristor is set such that the condition is such that the main Sl thyristor blocks the anode bias voltage VAK. Furthermore, there is also a bias circuit that applies VD 153 to the gate of the main Sl thyristor via a resistor, especially when the main Sl thyristor has a normally-on characteristic in which the gate is zero bias and current flows between the anode and the cathode.

Furthermore, there is also a circuit that biases or grounds the 13th n-region of the MISFET and the 16th n-base region of the BPT via a load.

Under the above bias conditions, the main Sl thyristor is irradiated with a trigger light pulse L T 161 while the main Sl thyristor is turned off. The light entering the main Sl thyristor causes n-low impurity density regions 102, 10
3, an electron-hole pair is generated. The holes of the generated electron-hole pairs are accumulated in the p+ agate region 105, and as a result, the potential for electrons in the p+ gate region and the channel region sandwiched between the p+ agate regions becomes low.

n-10 cando region 104 to n- low impurity density region 10
The amount of electrons injected into 2 increases. Further, among electron-hole pairs generated by light, electrons generated near the n- low impurity density region 102 are generated in the p+γ node region 102.
1 and n- are accumulated in the second base near the junction of the low impurity density region 102, and as a result, the potential for holes in the second base is low, and the amount of holes injected from the anode region 101 increases. . In addition to photogenerated electron-hole pairs.

Electrons injected from the p+ anode region 104 and holes injected from the p+ anode region 101 further reduce the potential of the channel and the second base, increasing the injection of electrons and holes, and the main Sl thyristor turns.・Turn on. Once turned off, the trigger light pulse L T
Even if 161 is cut off, the main Sl thyristor remains on, and then the quenching light pulse LQ 162 is turned on to MISFE.
The BPT for T drive is irradiated. Electrons of the electron-hole pairs generated by the light incident on the BPT are accumulated in the 16th n base region, and the BPT is turned on.

As a result, Vo, which is the collector bias of the BPT, is applied to the gate of the MISFET, and the MISFET is also turned on.

By this, main SI thyristano p÷gate area 1
The holes accumulated in the p+ gate region 105 are extracted through the MISFET, and the potential for electrons in the p+ gate region 105 becomes high, blocking the injection of electrons from the cathode.
The potential for holes in the second base is also high (and the injection of holes from the main anode region 101 is also blocked, and the main S
l thyristor is turned off. Once turned off, the main Sl thyristor remains off even if the quench light pulse LQ162 is cut off and the BPT is turned off and the MOS transistor is turned off. The above process realizes on/off operation using only light.

Figure 2 shows a photo-trigger/photo-quench SI thyristor according to the present invention, which uses a BPT for driving a MISFET and an MfSFET as a photo-sensitive element for photo-quenching, and the main Sl thyristor is a planar gate type S■ thyristor. An example of the configuration is shown below.

In FIG. 2, the main Sl thyristor is composed of a p+ anode region 201, an n"" low impurity density region 202, an n+ cathode region 204, a p+ gate region 205, and a p+ anode region 201. n+cando area 204
An anode electrode 231, a cathode electrode 232, and a gate electrode 233 are provided on the surface electrode portion of the p+ gate region 205, respectively.

MISFET and its M as a photosensitive element for light quenching
The BPT for driving the ISFET has a similar structure to the embodiment shown in FIG.

L T 261 is a trigger light pulse, and L Q 262 is a quench light pulse. Further, the operation is the same as the embodiment shown in FIG.

Integrating the planar gate type 51 thyristor and MISFET is structurally relatively simple.

Of course, there is also a structure in which the main Sl thyristor is in the form of a notched gate.

FIG. 3 shows a photo-trigger/photo-quenching Sl thyristor according to the present invention, in which a MISFET is used as a photosensitive element for photo-quenching.
An embodiment is shown in which the main Sl thyristor is a buried gate type SI thyristor in a circuit type using an Sl phototransistor for driving a MISFET.

In FIG. 3, the main Sl thyristor is of similar construction to the embodiment shown in FIG.

The MISFET is provided in a region electrically isolated from the surroundings by a dielectric region 310, and an r source region 31
2, n region 313, n- region 3, first p+ drain region 314, n÷ region 317, gate electrode 335 provided on n region 313 via a gate oxide film, and gate electrode 333 of the main Sl thyristor. It is composed of a connected source electrode 336, a drain electrode 334, an n-region electrode 337, and a busy-region electrode 338. MISFET
The Sl phototransistor for driving has a p+ source region, a p-<n-> high resistance region 322, a p+ drain region 323, an n+ agate region 324, and a source electrode connected to the gate electrode 335 of the MISFET. 343, a drain electrode 341, and a gate electrode 342. The drain electrode 341 and the upper electrode 342 are
It is effective to use a material that transmits light.

L T 361 is a trigger light pulse, L Q 362
is a quenching optical pulse.

High speed and photosensitive element for driving MISFET.
By using a high photosensitivity Sl phototransistor,
Faster light quenching can be achieved with weaker light energy.

41st! ! ! I is a light trigger/light quench SI thyristor according to the present invention, and MI is used as a light sensitive element for light quenching.
This circuit type uses Sl phototransistors to drive SFETs and MISFETs, and the main Sl thyristor is composed of a buried gate type SI thyristor.
An embodiment is shown in which the FET and the Sl phototransistor are provided in a region provided within the semiconductor substrate that is electrically isolated from the surroundings.

In Figure 4, the main Sl thyristor and MISFET are
The structure is similar to the embodiment shown in FIG.

The phototransistor 31 is provided in a region electrically isolated from the surroundings of the dielectric region 4, and is connected to a p+ source region 421, a p″″(n−) high resistance region 422, and a p
+ drain region 423, gate electrode 442, and MISF
Source electrode 4 connected to gate electrode 435 of ET
43 and a drain electrode 441. It is effective to choose a material that transmits light for the electrode.

L T 461 is a trigger light pulse, and L Q 462 is a quench light pulse.

FIG. 5 shows a photo-trigger/photo-quench SI thyristor according to the present invention, in which a MISFET is used as a photo-sensitive element for photo-quenching.
The main Sl thyristor is composed of 51 buried gate type thyristors, and the MISFET and Sl phototransistor are connected to a surrounding area provided in an epitaxial growth layer on a semiconductor substrate. An embodiment is provided in an area electrically isolated from the.

In Figure 5, the main Sl thyristor, MISFET and S
The structure of each of the phototransistors is similar to the embodiment shown in FIG.

The feature of the embodiment shown in FIG.
03'.

LT561 is a trigger light pulse, LQ562 is
This is a light pulse for quenching.

FIG. 6 shows a photo-trigger/photo-quench SI thyristor according to the present invention, in which rMIssIT is used as a photosensitive element for photo-quenching.
Also ltMIsFET and MlSS IT*tltMI
The circuit type uses 51 phototransistors to drive 5FETs, and the main Sl thyristor is composed of a notch type MOS gate s thyristor, and the MISSIT or MISFET is a vertical notched gate type MrssI thyristor.
An embodiment is shown in which the first Ml5FET with T* is constructed, and the Sl phototransistor is constructed with a vertical notch gate Sl phototransistor.

In FIG. 6, the main Sl thyristor includes a p+ anode region 601, an n- low impurity density region 502, and a p shadow region 60.
7.608. ! :rl” can-1/region 6o4 top p+ region 606, MOS gate electrode 633, and anode electrode 63
1 and a cathode electrode 632.

It is effective to use a material that transmits light for each electrode. MISFET Mari it M r S F E T f
i, r source region 651 and p region 652,653 and p"
It is composed of a region 654, a -drain region 655, an n+ region 656, a MOS gate electrode 635, a source electrode 636 connected to the gate electrode 633 of the main Sl thyristor and an electrode 639 of the r region 606, and a drain electrode 634. and is electrically isolated from the surroundings by a dielectric region 610. The Sr phototransistor includes a p+ soso region 621, a p-(n-) region 622, a p+ drain region 623, an n+ agate region 624, and a drain electrode 421.
and gate electrode 642, MISLIT or MISFE
Source electrode 64 connected to gate electrode 635 of T
3, and is electrically isolated from the periphery by a dielectric region 6 first. There is a region where a source electrode is not provided in the surface exposed and mountainous portions of the p+ soso region 621, so that light can easily penetrate.

It is also effective to select a transparent material for the electrode.

L T 661 is a trigger light pulse, and LQ is a quench light pulse.

The main thyristors of the embodiments shown in FIGS. 1 to □FIG. 6 include a buried gate type 51 thyristor and a planar gate type
A thyristor notched gate type SI thyristor may also be used.

It may also be a gate turn off thyristor (GTO). Furthermore, it is also effective to improve photosensitivity by periodically providing n medium regions in the second base region formed at the junction surface of the p+ anode region and the n- low impurity density region to create an SIT structure. be.

The embodiment shown in FIGS. 1 to 6 is a direct trigger type in which the main thyristor is directly triggered. There is also a structure that accumulates a.

7 and 8 show an example of an integrated structure using an S (thyristor) having a horizontal configuration. The Sl thyristor portion is formed in a high-resistance semiconductor region 802 formed in a polygonal layer 800 with an insulating layer 801 interposed therebetween. 810 and 81
2 are an n+ cando region and a p+7)-do region, respectively, and a p+ region 809 is the first gate of the thyristor 31 and an n
The first + region 8 serves as the second gate. In the embodiment of FIG. 7, the second gate region 8 first is in a floating state.

813 is the first gate electrode, 814 is the power gate electrode 8
15 indicates an anode electrode. The quenching photosensitive element is formed in another island-shaped high-resistance semiconductor layer region 803.

It is composed of a p-channel MOSFET or MO3SiT and a bipolar phototransistor number ζ that drives its gate. p+ region 808 is a MOS
The source region of the transistor portion, p+ region 806, also serves as a drain region. N region 807 is a channel portion of a MOS transistor, and electrode 819 is a gate electrode. The source electrode 820 is shared with the gate electrode 813 of the Sl thyristor. Reference numeral 821 indicates an electrode to the n region 807. 818 is a drain electrode.

Furthermore, the p medium region 805 is the emitter region of the bipolar phototransistor, the n region 804 is the base region, and the p+ region 806 is the collector region. Further, 817 indicates an emitter electrode, and 816 indicates a pace electrode. The emitter electrode 817 and gate electrode 819 are commonly used. optical fiber 8
Electron-hole pairs are generated in the high-resistance layer 803 by the optical quench pulse LQ825 introduced by 24 and 1.

When the bipolar phototransistor is made conductive by this optical pulse LQ 825, the potential of the collector (and at the same time drain) terminal biased to the @ sign appears on the gate electrode 819. In other words, it acts to make the MOS transistor conductive. Therefore, the holes accumulated in the p+ agate region 809 of the Sl thyristor when the thyristor is on are discharged to the drain electrode 81B through the p-channel MOS transistor.In other words, they are quenched by light. Of the electron-hole pairs generated in the high resistance layer 802 by the trigger light pulse L T 823 introduced by the optical fiber 822Iζ, the electrons are accumulated in the n'gate region 8 first, and the holes are accumulated in the p+ agate region. 809. That is, both electron-hole pairs generated by light are
Since it works to make the thyristor conductive, the double gate type Sl thyristor shown in the embodiment of FIG. 7 has extremely high optical trigger sensitivity. n medium region 8 first and p+ anode 8
Hole injection from the door anode 812 is also controlled by the SIT gate structure formed by 12, and at the same time, the cathode side is also
Electron injection from the n-cando 810 is controlled by the SIT gate structure formed by.

In the example of FIG. 7, the first n+ gate region 8 is a floating cap. Naturally, when the light pulse LT823 is not irradiated, the Sl thyristor must be in an off state, so the first H+ gate 8 is set to be a NO7 reoff gate.

FIG. 8 shows another embodiment of a horizontal integrated structure with double gate Sl thyristors. In FIG. 7, an example is shown in which the first n+ gate 8 is in a floating state and only the p+ gate 809 is used as a gate, but in the embodiment shown in FIG. 8, the first p+ gate 809 is normally off. The n+ gate 8 of the second gate is configured to be in a floating state.
An example is shown in which the gate is the gate of an Sl thyristor. Areas common to those in FIG. 7 are indicated by the same numbers. In FIG. 8, the polysilicon region 80
An n-channel MOSFET or MO3SIT and a bipolar phototransistor for driving the gate thereof are formed in another high-resistance semiconductor layer 803 formed in the semiconductor layer 801 with an insulating layer 801 interposed therebetween.

n'' GJi region 8.i4 is the source region of the MOS transistor, p region 843 is a channel-free region, n+ region 84
2 is a drain electrode. The n+ region 841 is the emitter region of the bipolar phototransistor, the p region 840 is the base region, and the n middle region 842 is the collector region.

The electrode 849 for the n+ region 844 is common to the first electrode 830 of the n+ gate 8 of the Sl thyristor. 8
50 is the electrode of the p channel 843, 848 is the gate electrode of the MOS transistor, and at the same time is the n0 emitter 84.
It is common to the electrode 846 of No. 1. 845 is a base electrode, and 847 is a collector and drain electrode, which are biased to the (+) sign.

When irradiated with the optical quench pulse L Q 825 introduced by the optical fiber 824Iζ, the bipolar phototransistor becomes conductive, and a (+) collector bias voltage is applied to the gate electrode 848. Therefore, M of n-channel
Since the OS transistor becomes conductive, the electrons accumulated in the n+ gate 8 first of the thyristor 51 are discharged through the MOS transistor and photoquenched.

The Sl thyristor shown in FIGS. 7 and 8 was shown as an example in which only one of the double gates is used with a gate electrode, but it goes without saying that both gates have electrodes and are used literally as C. Gate 8 1st, p+ gate 8
It is also possible to use 09 together. In this case, the structure becomes more complicated because wiring and another optical quenching element are added, but the operation becomes faster.

Further, in the embodiments shown in FIGS. 7 and 8, an S■ thyristor with a planar gate structure is shown, but other buried gate #I thyristors are shown.
It goes without saying that an Sl thyristor with a 11-channel structure, a cut gate structure, or an MO5/Mis gate structure may be used.

Further, although a method-Iζ in which the Sl thyristor is directly triggered by light is shown, a method in which the gate of the Sl thyristor is indirectly driven as an amplification gate via a photosensitive element is also possible. It is also clear that the embodiment shown in FIGS. 7 and 8 is extremely easy to manufacture and can also be made as a trier configuration.

In addition, in the embodiment shown in FIGS. 7 and 8, a semiconductor region is formed in a polycondensate substrate via an insulating layer, but the structure is not limited to this, and It goes without saying that it may be formed using pn junction isolation, V-groove isolation, U-groove isolation technology, or SO technology.

〔Effect of the invention〕

Among the embodiments of the present invention described above, the experimental results of the most basic part shown in FIGS. 3, 4, and 5 will be explained.

FIG. 9 shows measurement results and a circuit diagram of the dependence of the turn-off delay time Tdoff on the optical pulse intensities P+ and o for quenching. In the circuit diagram, S I Thy is the main Sl thyristor, M
OS indicates a quench MO3FET, and 5IPT indicates an Sl phototransistor for driving a MOS transistor. When the resistance Ra = 100 Ω, the bias voltage is Va (SIT) = 5.4V, VD (SIT), respectively.
= -27V, V'o(Mos) = -25V. LT is a trigger light pulse, LQ is a quench light pulse, wavelength 880 r&m, rise time 12 n
s LED was used as a light source. Anode voltage VAI
I Ha, 100.200.300.400 V.

The anode current ■^ was measured with IA. 400V.

With LA operation, quenching optical pulse intensity PLo = 17
．． 5m w/- to kir Tdoff = 5501
8 results were obtained.

By using the optically triggered and optically quenched Sl thyristor according to the present invention, high power can be orthogonally converted at high speed and with high efficiency using only a simple bias circuit and optical pulses for triggering and quenching. The light-trigger/light-quench Sl thyristor according to the present invention has dramatically improved reliability and safety because the high-power part and the control circuit can be completely separated electrically and the number of parts can be extremely reduced. It has high industrial utility value not only as a switching device for large electric power, but also in the small and medium power sector.

[Brief explanation of the drawing]

1 to 8 are cross-sectional structural diagrams of an optically triggered optical quenching Sl thyristor according to the present invention, FIG. 9 is a circuit diagram and αj determination result of the dependence of the turn-off delay time on the quenching optical pulse intensity, and FIG. Figure 10 shows the conventional optical trigger and optical quench S.
■It is a cross-sectional structural diagram of a thyristor. 101, 201.301.401.501.601.
812...p+ad/- area of main Sl thyristor, 102.103, 202.302.303.4
02.403,502.503.602.802-=-
Main SI thyristor n-low impurity density region, 104.2
04,304,404゜504.604,810--
- the main Sl thyristoranode region, 105.
205.305.405.505.809... Main Sl thyristor p+ agate region, 131.231.3
31.431,531, 631.815...
Anode electrode of main Sl thyristor, 132, 232.
332.432.532.632.814...
Cathode electrode of main Sl thyristor, 133.233.3
33.433.533.633.813...
First gate electrode of main Sl thyristor, 607, 608.
...P region of main Sl thyristor, 606...
...P+ region 639 of main Sl thyristor... Electrodes of p+ region 606 of main Sl thyristor, 10th and 21st
0,310,410.4 1.510, 5 1,610
．． 6th 1.801... Dielectric separation layer, 11th.
2 No. 1.3 No. 1.4 No. 1.5 No. 1.803 -・・・・−
MISFET or MISFET+7)ff
Low impurity density region or high resistance region, No. 12.212.
312.412.512.808.844...
Source region of MISFET or MISSIT, 13th
．． 2゛13.313.413,513.807...
... MISFET or MISSIT n region, 14th
, 214, 314.414.514.806...
・MISFET or MISSIT p+ drain region, No. 15,215.805 ... BPT's p+ emifter region, No. 16.216.804 ==-
B P T non he-x area, 317°417.51
7 ・・・・・・MISFET or MXSSIT n
+ Territory area 321.421.521.621 ...-8I
P+ soso region of phototransistor, 322°422
, 522, 622... N-low impurity density region of Sl phototransistor, 323.423.5
23.623...p+ drain region of Sl phototransistor, 324.424.524.624...
... n+ agate region of Sl phototransistor, 6
51 ・・・ Vertical MISSIT or MIS
Source region of FET, 652.653 ...P region of vertical MISSIT or MISFET, 654
・・・・・・p of vertical MISSIT or MISFET
"" region, 655... Vertical Mass (T or M [5FET p+ drain region, 134.234
,334,434.534...MI 5FE
T or MISSIT drain electrode, 135°235.
335.435.535 ... MISFET
or MISSIT gate electrode, 136,236.3
36.436.536 ... Source electrode of MISFET or MISSIT, 137.237.337.
437.537 ... MISFET or Ml
551T n-region electrode, 138.238.817.
846...BPT emitter electrode, 139,2
39,816.845 ... BPT base electrode, 338,438°538 --- M I S
FET or MISSIT n+ region electrode, 34
1,441.541.641 ... Source electrode of Sl phototransistor, 342.442542.6
42... Gate electrode of Sl phototransistor, 343.443.543.643...
Source electrode of Sl phototransistor, 634...
...Drain electrode of vertical MISSIT or MISFET, 635 ... Vertical MISSIT or MI
SFET gate electrode, 636...vertical MISS
Source electrode of IT or MISFET, 638...
・Vertical MISSIT or ltMIsFET+7)n+
Territory area electrode, 171.271, 371.471, 5
71,671,801...Insulating film such as oxide film, 1
61.261361.461 , 561 , 661
, 823 ...... Trigger light/reless, 162,262,362.462.5
62.662.825 ...... Optical pulse for quenching, 822.824 ...... - Optical fiber, 800 ...... Polysilicon substrate, 8
First... second gate region of the Sl thyristor,
830... Second gate electrode of Sl thyristor, 807... = Mo3FET or Mo3SIT
n-type channel layer, 821... Electrode of n-type channel layer, 843...M, 05FE
TbL<+tMO3S I T p-type channel layer, 8
50...P-type channel/layer electrode, 842...
...N+ drain region of n-channel MoS transistor, 847...N+ drain electrode, 8
19.848...Mo3) Gate electrode of transistor, 820, 849... Source electrode of MOS transistor. 8 ri Ishi4FMt)+attmata-/Jt)jl Ply
(xu//(,!!]s5;'Fig.

Claims (7)

[Claims] (1) an anode region of a first conductivity type; a first low impurity density region of a second conductivity type that is adjacent to the anode region and forms a first pn junction between the anode region; a second conductivity type cathode region adjacent to the first low impurity density region and having a higher impurity density than the first low impurity density region; A gate region of a first conductivity type that forms a second pn junction with a low impurity density region, and a pair of main electrodes formed on exposed surface portions of the anode region and the cathode region are connected to the gate region. a buried gate type static induction thyristor having a first gate electrode provided on an exposed surface portion of the thyristor; a source region of a first conductivity type; a second conductivity type region adjacent to the source region; a second low impurity density region of a second conductivity type surrounded by an insulating layer adjacent to the first low impurity density region of the buried gate electrostatic induction thyristor; and a second low impurity density region adjacent to the second low impurity density region. a drain region of a first conductivity type; a source electrode provided on an exposed surface portion of the source region and connected to the first gate electrode; a drain electrode provided on an exposed surface portion of the drain region; An insulated gate field effect transistor or an insulated gate electrode having a second gate electrode provided on a second conductivity type region via an insulating film, and an electrode provided on a surface exposed portion of the second conductivity type region. a gated static induction transistor; an emitter region of a first conductivity type; a base region of a second conductivity type adjacent to the emitter region and the second low impurity density region; and the second low impurity density region. a collector region formed in a common region with the drain region; an emitter electrode provided on an exposed surface portion of the emitter region and connected to the second gate electrode; and a surface-electrode portion of the base region. a bipolar phototransistor having a base electrode provided on the base electrode and a collector electrode common to the drain electrode; a light source for irradiating the buried gate type electrostatic induction thyristor with a trigger light pulse; an optical transmission medium; and the bipolar phototransistor. A photo-trigger/photo-quench electrostatic induction thyristor comprising a light source and an optical transmission medium for irradiating a phototransistor with a quenching light pulse. (2) an anode region of a first conductivity type; a first low impurity density region of a second conductivity type that is adjacent to the anode region and forms a first pn junction between the anode region; a second conductivity type cathode region adjacent to the first low impurity density region and having a higher impurity density than the first low impurity density region; a first conductivity type gate region forming a second pn junction with a low impurity density region; a pair of main electrodes formed on exposed surface portions of the anode region and the cathode region; and the gate region. a planar gate electrostatic induction thyristor having a first gate electrode provided on an exposed surface portion of the thyristor; a source region of a first conductivity type; a second conductivity type region adjacent to the source region; a second low impurity density region of a second conductivity type surrounded by an insulating layer adjacent to the first low impurity density region of the planar gate electrostatic induction thyristor; and a second low impurity density region adjacent to the second low impurity density region. a drain region of a first conductivity type, a source electrode provided on an exposed surface portion of the source region and connected to the first gate electrode, and a drain electrode provided on an exposed surface portion of the drain region; an insulated gate field effect transistor having a second gate electrode provided on the second conductivity type region with an insulating film interposed therebetween; and an electrode provided on a surface exposed portion of the second conductivity type region; an insulated gate static induction transistor; an emitter region of a first conductivity type;
a base region of a second conductivity type adjacent to the emitter region and the second low impurity density region; a collector region formed of a region common to the second low impurity density region and the drain region; an emitter electrode provided on an exposed surface portion of the emitter region and connected to the second gate electrode; a base electrode provided on an exposed surface portion of the base region; and a collector electrode common to the drain electrode. a bipolar phototransistor; a light source and an optical transmission medium for irradiating the planar gate type electrostatic induction thyristor with a triggering optical pulse; and a light source and an optical transmission medium for irradiating the bipolar phototransistor with a quenching optical pulse. A light-triggered/light-quenched electrostatic induction thyristor comprising: (3) an anode region of a first conductivity type, a first low impurity density region of a second conductivity type that is adjacent to the anode region and forms a first pn junction between the anode region; a second conductivity type cathode region adjacent to the first low impurity density region and having a higher impurity density than the first low impurity density region; and adjacent to the first low impurity density region,
a first gate region of a first conductivity type forming a second pn junction with the first low impurity density region; and a pair of gate regions formed on exposed surface portions of the anode region and the cathode region. A static induction thyristor having a main electrode, a first gate electrode provided on an exposed surface portion of the gate region, a first source region of a first conductivity type, and adjacent to the first source region. a second conductivity type region surrounded by an insulating layer adjacent to the first low impurity density region of the electrostatic induction thyristor; a second low impurity density region of a second conductivity type adjacent to the drain region of the first conductivity type adjacent to the second low impurity density region; a first source electrode connected to the first gate electrode; a first drain electrode provided on the surface exposed portion of the drain region; and a first drain electrode provided on the second conductivity type region via an insulating film. an insulated gate field effect transistor or an insulator having a second gate electrode, an electrode provided on an exposed surface portion of the high impurity density region, and an electrode provided on an exposed surface portion of the second conductivity type region; a gated static induction transistor; a second transistor of a first conductivity type adjacent to the first low impurity density region;
and a first source region adjacent to the second source region.
a third low impurity density region of a conductivity type, a second drain region of a first conductivity type adjacent to the third low impurity density region, and a second low impurity density region adjacent to the third low impurity density region. a second gate region having a conductivity type of , a second drain electrode provided on an exposed surface portion of the second drain region, and a third gate provided on an exposed surface portion of the second gate region. an electrostatic induction phototransistor having an electrode and a second source electrode provided on an exposed surface portion of the second source region and connected to the second gate electrode; and a trigger light for the electrostatic induction thyristor. A photo-trigger/photo-quenching electrostatic device comprising a light source and an optical transmission medium for irradiating a pulse, and a light source and an optical transmission medium for irradiating the electrostatic induction phototransistor with a quenching optical pulse. induction thyristor. (4) an anode region of a first conductivity type; a first low impurity density region of a second conductivity type that is adjacent to the anode region and forms a first pn junction between the anode region;
a second conductivity type cathode region adjacent to the first low impurity density region and having a higher impurity density than the first low impurity density region; a first gate region of a first conductivity type forming a second pn junction with the first low impurity density region; an electrostatic induction thyristor having an electrode, a first gate electrode provided on an exposed surface portion of the gate region, a first source region of a first conductivity type, and a first source region adjacent to the first source region; a second conductivity type region; a second conductivity type high impurity density region surrounded by a first insulating layer adjacent to the first low impurity density region of the electrostatic induction thyristor; a second low impurity density region of a second conductivity type adjacent to the region, a drain region of a first conductivity type adjacent to the second low impurity density region, and a surface exposed portion of the source region. a first source electrode connected to the first gate electrode; a first drain electrode provided on the surface exposed portion of the drain region; and a first drain electrode provided on the second conductivity type region via an insulating film. second
an insulated gate field effect transistor or an insulated gate field effect transistor having a gate electrode, an electrode provided on an exposed surface portion of the high impurity density region, and an electrode provided on an exposed surface portion of the second conductivity type region. a static induction transistor; a second source region of a first conductivity type surrounded by a second insulating layer adjacent to the first low impurity density region;
a third low impurity density region of the first conductivity type adjacent to the second source region; a second drain region of the first conductivity type adjacent to the third low impurity density region; 3
a second gate region of a second conductivity type adjacent to the low impurity density region; a second drain electrode provided on an exposed surface portion of the second drain region; and a surface of the second gate region. a third gate electrode provided on an exposed portion; and a third gate electrode provided on a surface exposed portion of the second source region.
a second source electrode connected to a gate electrode of the electrostatic induction phototransistor; a light source and an optical transmission medium for irradiating the electrostatic induction thyristor with a trigger light pulse; and the electrostatic induction phototransistor. a light source and an optical transmission medium for irradiating a quenching light pulse to the insulated gate transistor and the electrostatic induction phototransistor, the insulated gate transistor and the electrostatic induction phototransistor are arranged in a first gate region between the first gate region and the anode region of the electrostatic induction thyristor. 1. A photo-triggered/photo-quenched electrostatic induction thyristor, characterized in that it is formed in a region partially carved out of the low impurity density region of No. 1. (5) an anode region of a first conductivity type; a first low impurity density region of a second conductivity type that is adjacent to the anode region and forms a first pn junction between the anode region;
a second conductivity type cathode region adjacent to the first low impurity density region and having a higher impurity density than the first low impurity density region; a first gate region of a first conductivity type forming a second pn junction with a low impurity density region; a pair of main electrodes formed on exposed surface portions of the anode region and the cathode region; , a static induction thyristor having a first gate electrode provided on an exposed surface portion of the gate region, a first source region of a first conductivity type, and a second source region adjacent to the first source region. a conductivity type region, a second conductivity type high impurity density region surrounded by an insulating layer adjacent to the first low impurity density region of the electrostatic induction thyristor, and a second conductivity type region adjacent to the high impurity density region. a second low impurity density region of a second conductivity type, a drain region of a first conductivity type adjacent to the second low impurity density region, and the first gate provided in a surface exposed portion of the source region. a first source electrode connected to the electrode, a first drain electrode provided on the surface exposed portion of the drain region, and a second drain electrode provided on the second conductivity type region with an insulating film interposed therebetween. An insulated gate field effect transistor or an insulated gate static transistor having a gate electrode, an electrode provided on an exposed surface portion of the high impurity density region, and an electrode provided on an exposed surface portion of the second conductivity type region. a second source region of a first conductivity type surrounded by a second insulating layer adjacent to the first low impurity density region; and a first source region adjacent to the second source region. a third low impurity density region of conductivity type; and a first low impurity density region adjacent to the third low impurity density region.
a second drain region of a conductivity type, a second gate region of a second conductivity type adjacent to the third low impurity density region, and a second gate region provided on a surface exposed portion of the second drain region. a third gate electrode provided on the exposed surface portion of the second gate region; and a third gate electrode provided on the exposed surface portion of the second source region and connected to the second gate electrode. an electrostatic induction phototransistor having a second source electrode; a light source and an optical transmission medium for irradiating the electrostatic induction thyristor with a trigger light pulse; and a quenching light pulse irradiating the electrostatic induction phototransistor. the insulated gate transistor and the electrostatic induction phototransistor are arranged in a region between the first gate region and the anode region in the first low impurity density region; A light-triggered/light-quenched electrostatic induction thyristor characterized in that it is formed in a region partially carved out of the region located above. (6) an anode region of a first conductivity type; a first low impurity density region of a second conductivity type that is adjacent to the anode region and forms a first pn junction between the anode region; a first first conductivity type region adjacent to the first low impurity density region; and a first conductivity type region adjacent to the first first conductivity type region having a higher impurity density than the first first conductivity type region. 1st to have
a first high impurity density region of conductivity type;
a cathode region of a second conductivity type adjacent to the conductivity type region; a pair of main electrodes formed on exposed surface portions of the anode region and the cathode region; and an exposed surface portion of the first high impurity density region. an electrode provided in the first conductivity type region, a part of the cathode region and the first conductivity type region;
an insulated gate electrostatic induction thyristor having a first gate electrode provided on a part of the low impurity density region via an insulating film; and a first gate electrode adjacent to the first low impurity density region.
a first drain region of a first conductivity type surrounded by an insulator layer; a second low impurity density region of a first conductivity type adjacent to the first drain region; a second high impurity density region of a second conductivity type adjacent to the second first conductivity type region; a second high impurity density region of a second conductivity type adjacent to the second first conductivity type region; a first source region of a first conductivity type adjacent to the first conductivity type region; a first drain electrode provided on an exposed surface portion of the first drain region; and a surface of the first source region. an electrode provided on the exposed surface portion of the first high impurity density region; a first source electrode connected to the first gate electrode; and the second first conductivity type region. and a second gate electrode provided over a portion of the first source region and a portion of the second low impurity density region with an insulating film interposed therebetween;
an insulated gate static induction transistor or an insulated gate field effect transistor having an electrode provided on a surface exposed portion of the second high impurity density region;
a second drain region of the first conductivity type surrounded by a second insulating layer adjacent to the low impurity density region; a third low impurity density region adjacent to the second drain region; a second conductivity type adjacent to a third low impurity density region;
a second conductivity type gate region adjacent to the third low impurity density region, and a second drain electrode provided on an exposed surface portion of the second drain region;
a third gate electrode provided on an exposed surface portion of the gate region; and a second source electrode provided on an exposed surface portion of the second source region and connected to the second gate electrode. An electrostatic conductive phototransistor, a light source and optical transmission medium for irradiating the electrostatic induction thyristor with a triggering optical pulse, and a light source and optical transmission for irradiating the electrostatic induction phototransistor with a quenching optical pulse. A light-triggered/light-quenched electrostatic induction thyristor comprising a medium. (7) A double-gate SI thyristor formed in a first high-resistance semiconductor region formed in a polysilicon substrate via a first insulating layer, and a double-gate SI thyristor formed in a first high-resistance semiconductor region via a second insulating layer MOSFET or MOSSIT formed in the high resistance semiconductor region of No. 2
The MOSFET or MOSSIT is formed of a bipolar phototransistor in which the gate electrode and emitter electrode are common, and the drain region and collector region of the MOSFET or MOSSIT are common, and the first or second gate of the SI thyristor is an electrode. via the MOS
It has a structure connected to a source region of a FET or a MOSSIT, and includes an optical trigger pulse, an optical trigger pulse transmission medium, and an optical quench pulse transmission medium, and irradiates the optical trigger pulse to the first high-resistance semiconductor layer. The SI thyristor is triggered, and by irradiating the second high-resistance semiconductor layer with a light quenching pulse, the bipolar phototransistor and the MOS transistor are brought into conduction, and the SI thyristor is turned off. Light-triggered/light-quenched electrostatic induction thyristor.