JPS6113641B2 - - Google Patents

Info

Publication number
JPS6113641B2
JPS6113641B2 JP2150376A JP2150376A JPS6113641B2 JP S6113641 B2 JPS6113641 B2 JP S6113641B2 JP 2150376 A JP2150376 A JP 2150376A JP 2150376 A JP2150376 A JP 2150376A JP S6113641 B2 JPS6113641 B2 JP S6113641B2
Authority
JP
Japan
Prior art keywords
dielectric substrate
circuit
resonant
capacitor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2150376A
Other languages
Japanese (ja)
Other versions
JPS52104034A (en
Inventor
Mitsuo Makimoto
Sadahiko Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2150376A priority Critical patent/JPS52104034A/en
Priority to US05/771,987 priority patent/US4121182A/en
Priority to CA272,748A priority patent/CA1097755A/en
Publication of JPS52104034A publication Critical patent/JPS52104034A/en
Publication of JPS6113641B2 publication Critical patent/JPS6113641B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P7/00Resonators of the waveguide type
    • H01P7/08Strip line resonators
    • H01P7/082Microstripline resonators

Landscapes

  • Control Of Motors That Do Not Use Commutators (AREA)

Description

【発明の詳細な説明】 本発明は、特にUHF帯の電子同調チユーナに
好適な超高周波帯の電子同調回路に関するもので
ある。さらに詳しくは、電子同調チユーナの平面
回路構成に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultra-high frequency band electronic tuning circuit particularly suitable for a UHF band electronic tuning tuner. More specifically, the present invention relates to a planar circuit configuration of an electronically tuned tuner.

従来高周波増幅段付きの電子同調チユーナは、
第1図に示す様に、4つの共振回路部から構成さ
れている。第1図は、高周波増幅付きの場合の原
理的な構成図であり、各共振回路部は同軸線路で
構成し、それぞれの片端又は両端にコンデンサを
接続し、それぞれの段間には遮蔽板10を設け結
合孔を設けて結合されている。
Conventional electronically tuned tuners with high-frequency amplification stages are
As shown in FIG. 1, it is composed of four resonant circuit sections. Fig. 1 is a basic configuration diagram of a case with high frequency amplification. Each resonant circuit section is composed of a coaxial line, a capacitor is connected to one end or both ends of each, and a shielding plate 10 is installed between each stage. are provided and are coupled by providing a coupling hole.

第1図において、まず入力端子21からの入力
信号は、結合ループ11を通して共振回路12に
結合される。
In FIG. 1, an input signal from an input terminal 21 is first coupled to a resonant circuit 12 through a coupling loop 11.

当該信号は次にバイポーラトランジスタ又は電
界効果トランジスタによる高周波増幅段24を通
して、共振回路13,14をもつ複同調回路を経
て、混合部20に入る。他方、共振回路15は局
部発振器部25の共振部でその出力は上記と同様
に混合部20に入り、混合ダイオードによつて高
周波入力側と局部発振器側とが混合され、その中
間周波数を出力端子22から取り出す。バラクタ
ダイオード16,17,18,19は外部印加電
圧端子23から、直流電圧を印加することにより
その容量が変化する。そして各共振回路の同調周
波数が変えられる。
The signal then passes through a high-frequency amplification stage 24 with bipolar transistors or field effect transistors, passes through a double-tuned circuit with resonant circuits 13 and 14, and enters a mixing section 20. On the other hand, the resonant circuit 15 is the resonant part of the local oscillator section 25, and its output enters the mixing section 20 in the same way as above, where the high frequency input side and the local oscillator side are mixed by the mixing diode, and the intermediate frequency is sent to the output terminal. Take it out from 22. The varactor diodes 16, 17, 18, and 19 have their capacitances changed by applying a DC voltage from an externally applied voltage terminal 23. The tuning frequency of each resonant circuit can then be changed.

しかしながら上記のような構成では電磁界の漏
洩が大きく、回路の性能を著しく低下させてい
る。
However, with the above configuration, electromagnetic field leakage is large, significantly degrading the performance of the circuit.

本発明は上記欠点に鑑み、電磁界の漏洩が小さ
く、組立によるバラツキの少ない電子同調回路を
提供するものである。
In view of the above-mentioned drawbacks, the present invention provides an electronic tuning circuit in which electromagnetic field leakage is small and variations due to assembly are small.

以下図面を参照しながら、本発明の一実施例に
ついて説明する。
An embodiment of the present invention will be described below with reference to the drawings.

第2図は本発明の電子同調回路の原理を説明す
る平面図で、同図Aは円形ループ型、同図Bは矩
形ループ型であり、それぞれ形状は異なるが全く
同一原理である。
FIG. 2 is a plan view illustrating the principle of the electronic tuning circuit of the present invention. FIG. 2A shows a circular loop type circuit, and FIG. 2B shows a rectangular loop type circuit.Although their shapes are different, they are based on exactly the same principle.

共振線路部28,29は第2図の様に環状と
し、その両端に、バラクタダイオード30とコン
デンサ31を装架する。コンデンサ31は、バラ
クタに印加する直流電圧端子32からの直流を阻
止することも兼ねている。チヨークコイル33は
直流電圧の帰路である。
The resonant line sections 28 and 29 are ring-shaped as shown in FIG. 2, and a varactor diode 30 and a capacitor 31 are mounted at both ends thereof. The capacitor 31 also serves to block direct current from the direct current voltage terminal 32 applied to the varactor. The choke coil 33 is a return path for DC voltage.

第2図Cは第2図A,Bの等価回路を示すもの
であり、共振条件は下式で得られる。
FIG. 2C shows an equivalent circuit of FIGS. 2A and 2B, and the resonance condition is obtained by the following formula.

(1/ω=C/C+C(Ztan
β/ω+LS) 〔但し、 ωr:共振角周波数 CS:コンデンサ31の容量値 CV:バラクタダイオード30の容量値 Z0:共振線路部28,29の特性インピーダン
ス β :共振線路部28,29の位相定数 T:共振線路部28,29の全長 LS:CV,CSの有する直列インダクタンス
値〕 以上の第2図の構成によれば、 (i) 同調回路にRFの接地がなく低損失であり、
さらにパタン化可能であるために、組立による
バラツキが少ない。
(1/ω r ) 2 = C V C S / C V + C S (Z 0 tan
β Tr +L S ) [However, ω r : Resonant angular frequency C S : Capacitance value of capacitor 31 C V : Capacitance value of varactor diode 30 Z 0 : Characteristic impedance of resonant line sections 28 and 29 β : Resonant line Phase constant T of the sections 28 and 29: Total length of the resonant line sections 28 and 29 L S : Series inductance value of C V and C S ] According to the configuration shown in Fig. 2 above, (i) RF in the tuned circuit No grounding, low loss,
Furthermore, since it can be patterned, there is little variation due to assembly.

(ii) 回路が閉ループとなるために電磁界の漏洩が
少ない。
(ii) Since the circuit is a closed loop, there is little leakage of electromagnetic fields.

等の効果を有する。It has the following effects.

具体的にバラクタダイオード30にシリコンバ
ラクタダイオードを用い、上式のZ0=65Ω、T
=40mm、CS=15pFとし、450〜800MHz帯で可変
同調を設計した場合、同調電圧と共振周波数の関
係は第2図Dに示すようなものとなる。
Specifically, a silicon varactor diode is used as the varactor diode 30, and Z 0 = 65Ω in the above formula, T
= 40 mm, C S = 15 pF, and when variable tuning is designed in the 450 to 800 MHz band, the relationship between the tuning voltage and the resonant frequency is as shown in FIG. 2D.

また第2図Eに共振器の無負荷Q(Q0)の周波
数特性を示す。無負荷Qはバラクタ・ダイオード
30の直列抵抗RSでほぼ決定され、バラクタ・
ダイオード30の代りに低損失の固定キヤパシタ
を用いた場合は、無負荷Qは250程度となり、こ
の帯域内での変化も少ない。なおプリント基板と
しては、エポキシ・ガラスを用い、共振器はパタ
ン化して測定している。
Furthermore, FIG. 2E shows the frequency characteristics of the no-load Q (Q 0 ) of the resonator. The no-load Q is approximately determined by the series resistance R S of the varactor diode 30;
When a low-loss fixed capacitor is used instead of the diode 30, the no-load Q is about 250, and there is little change within this band. Note that epoxy glass was used as the printed circuit board, and the resonator was patterned and measured.

また第2図Fに3dB帯域巾と挿入損失の測定値
を示す。挿入損失は通常の短縮λg/2共振器
(エポキシ・ガラス基板を用いたサスペンデツド
構造)のBPFと比較し、第2図Bの構成によれば
高域ではほぼ同等、低域では約1.5dBの改善がみ
られた。
Figure 2F shows the measured values of the 3 dB bandwidth and insertion loss. Compared to the BPF of a normal shortened λg/2 resonator (suspended structure using an epoxy glass substrate), the insertion loss is almost the same in the high frequency range and about 1.5 dB in the low frequency range according to the configuration shown in Figure 2B. Improvement was seen.

次に本発明の一実施例について説明する。 Next, one embodiment of the present invention will be described.

第2図の回路のQ値を更に向上させ、さらに製
造上の工数削減による低価格を目的として、第2
図のコンデンサ31を集積化構造とし、共振線路
部28及び29と一体化して平面化回路で構成す
る。
In order to further improve the Q value of the circuit shown in Figure 2 and to reduce the cost by reducing the number of manufacturing steps, the second
The capacitor 31 shown in the figure has an integrated structure, and is integrated with the resonant line sections 28 and 29 to form a planar circuit.

第3図は、その共振線路の具体的実施例を示す
ものである。第3図A,B,Cは誘電体基板上に
構成するパターンで、第3図DはA―A′におけ
るその断面図である。第3図A,B,Cはいずれ
も原理的に同一であり共振線路28,29を作
り、コンデンサ34の部分は、誘電体基板35を
はさんで容量を構成する。第3図Bに示す矩形ル
ープ型共振回路の場合は、共振線路28及び29
の外殻が直線であるので、外部線路との結合が容
易に出来る利点がある。また大容量が必要な時
は、第3図Cの様な構造が適する。すなわち第3
図Dにおいて、共振線路28は他の共振線路29
と接触しいように途中で誘電体基板35を貫通し
て基板35の反対側に接続され、誘電体基板35
をはさんで、上,下線路28及び29でコンデン
サ34を構成する。第3図A,B,Cの斜線部分
がその集積化したコンデンサ部分となる。
FIG. 3 shows a specific example of the resonant line. 3A, B, and C are patterns formed on a dielectric substrate, and FIG. 3D is a sectional view taken along line A-A'. 3A, B, and C are all the same in principle, and make resonant lines 28 and 29, and a capacitor 34 forms a capacitance with a dielectric substrate 35 sandwiched therebetween. In the case of the rectangular loop type resonant circuit shown in FIG. 3B, the resonant lines 28 and 29
Since the outer shell is straight, it has the advantage that it can be easily connected to an external line. Further, when a large capacity is required, a structure as shown in FIG. 3C is suitable. That is, the third
In Figure D, the resonant line 28 is connected to the other resonant line 29.
The dielectric substrate 35 is connected to the opposite side of the substrate 35 by penetrating the dielectric substrate 35 in the middle so as to be in contact with the dielectric substrate 35.
A capacitor 34 is constituted by the upper and lower lines 28 and 29 sandwiching the upper and lower lines 28 and 29. The shaded areas in FIGS. 3A, B, and C are the integrated capacitor parts.

可変容量ダイオード30は共振線路28及び2
9の間に接続する。また大容量の場合には他の実
施例としてこのコンデンサ部分を共振線路全域に
拡張する方法がある。
The variable capacitance diode 30 connects the resonant lines 28 and 2
Connect between 9 and 9. In addition, in the case of a large capacitance, another embodiment is to extend this capacitor portion to the entire area of the resonant line.

第4図はこの考えに基づく構成例である。同図
から明らかな様に本実施例は表側の共振線路28
の全領域と裏側の共振線路29との間でコンデン
サを構成し、その間に可変容量ダイオード30を
固定したものである。この取付部分において共振
線路28と29がお互いに短絡しない様に、共振
線路29を一部表側に取出して可変容量ダイオー
ド30を固定している。
FIG. 4 shows an example of a configuration based on this idea. As is clear from the figure, in this embodiment, the resonant line 28 on the front side
A capacitor is constructed between the entire region of the wafer and the resonant line 29 on the back side, and a variable capacitance diode 30 is fixed between the capacitor and the resonant line 29 on the back side. In order to prevent the resonant lines 28 and 29 from being short-circuited to each other at this attachment part, a part of the resonant line 29 is taken out to the front side and a variable capacitance diode 30 is fixed thereto.

いずれの方法でも、この誘電体基板35の表裏
に構成した共振線路を超高周波特にUHF帯で高
性能化するために、パターン化した基板を金属筐
体内にサスペンデツド構造で保持して電子同調回
路を形成する。第5図において、金属筐体51の
中に、誘電体基板35を支持台52で固定する。
誘電体基板35は、容器内で中空に浮いているた
め、共振線路28及び29を上,下に形成するこ
とにより、集積化コンデンサの形成が容易であ
る。
In either method, in order to improve the performance of the resonant lines formed on the front and back surfaces of the dielectric substrate 35 at ultra-high frequencies, especially in the UHF band, the patterned substrate is held in a suspended structure within a metal casing to form an electronic tuning circuit. Form. In FIG. 5, a dielectric substrate 35 is fixed in a metal casing 51 with a support 52. As shown in FIG.
Since the dielectric substrate 35 is floating in the air within the container, an integrated capacitor can be easily formed by forming the resonant lines 28 and 29 on the upper and lower sides.

なお、上記実施例において可変同調周波数の微
調整は、上下の共振線路により誘電体基板をはさ
む面積をトリミングすることにより可能である。
又、コンデンサを形成するに、所望の容量を得る
には、誘電体基板は一定値の厚さと大きさが必要
である。厚さが薄い程容量値は得やすいので材料
面からは低価格化出来るし、又、用いる誘電体材
料の誘電損失(tanδ)の小さいものの方が回路
の特性上よい。
In the above embodiment, fine adjustment of the variable tuning frequency is possible by trimming the area between the dielectric substrates between the upper and lower resonant lines.
Furthermore, in order to form a capacitor and obtain a desired capacitance, the dielectric substrate must have a certain thickness and size. The thinner the thickness, the easier it is to obtain a capacitance value, so the cost can be reduced from a material standpoint, and the dielectric material used has a smaller dielectric loss (tan δ), which is better in terms of circuit characteristics.

実施例として、第3図Cの共振線路をサスペン
デツド構造で保持し誘電体基板35として厚さ
0.4mmのテフロンガラス樹脂基板を用いて、容量
部の面積15mm2(約11pF)で、可変容量ダイオー
ド30の容量変化が1:7.6の範囲のものを使用
し、金属ケース内高さ15mmに保持した結果同調周
波数範囲は470MHzから920MHzまで網羅すること
が出来た。
As an example, the resonant line shown in FIG. 3C is held in a suspended structure and the dielectric substrate 35 is
A 0.4 mm Teflon glass resin substrate is used, the capacitor area is 15 mm 2 (approximately 11 pF), the capacitance change of the variable capacitance diode 30 is in the range of 1:7.6, and the height inside the metal case is kept at 15 mm. As a result, we were able to cover the tuning frequency range from 470MHz to 920MHz.

第6図は、第3図Cの共振回路を用いた平面化
電子チユーナの一構成例であり、原理的な高周波
回路部分のみを記した。又、高周波増幅部につい
ては、第1図と同様に、更に共振回路を附加すれ
ばよいので省略した。以下図を用いて説明する。
UHF帯の高周波入力信号は入力端子61から入
り、結合ループ62を通して、複同調回路63,
64に入り、混合回路73に入る。一方、局部発
振器部67は、同調共振部66を通して混合回路
73に入り、混合ダイオード65で入力信号と混
合され端子70より中間周波信号が取出される。
可変容量ダイオード68は、端子71より直流電
圧が印加され、チヨークコイル69がその帰路に
なる。基板上には接地導体72も含めて平面化の
共振線路で構成し、Bの断面図に示す様に、共振
線路の形成された基板75を金属筐体74に保持
する。
FIG. 6 shows a configuration example of a planar electronic tuner using the resonant circuit shown in FIG. 3C, and only the principle high-frequency circuit portion is shown. Further, the high frequency amplification section is omitted because it is sufficient to add a resonant circuit as in FIG. 1. This will be explained below using figures.
A high frequency input signal in the UHF band enters from the input terminal 61 and passes through the coupling loop 62 to the double tuning circuit 63,
64 and enters the mixing circuit 73. On the other hand, the local oscillator section 67 enters the mixing circuit 73 through the tuned resonance section 66, is mixed with the input signal by the mixing diode 65, and an intermediate frequency signal is taken out from the terminal 70.
A DC voltage is applied to the variable capacitance diode 68 from the terminal 71, and the chiyoke coil 69 serves as its return path. A planar resonant line including a ground conductor 72 is formed on the substrate, and as shown in the cross-sectional view B, a substrate 75 on which the resonant line is formed is held in a metal casing 74.

誘電体基板74は、外側の接地兼遮蔽板となる
筐体75に上,下非対称の位置に設ける。この様
に非対称にする事により、電磁界の広がりを小さ
く出来て、従来の様な段間遮蔽板を用いる必要が
なくなる。
The dielectric substrate 74 is provided at an asymmetrical position upwardly and downwardly on the casing 75 which serves as an outer grounding and shielding plate. By making it asymmetrical in this way, the spread of the electromagnetic field can be reduced, and there is no need to use a conventional interstage shielding plate.

以上のように本発明は、略U字状、あるいは半
円形状の第1、第2の導体を互いに対向させ、誘
電体基板の一主面上に設けたリング状の共振器
と、前記第1、第2の導体が互いに対向する一端
部に設けられた前記第1、第2の導体間の容量部
と、またその他端部に設けられた可変容量ダイオ
ードとを設け、前記容量部は、誘電体基板の一主
面上に設けた第1の導体の一端部を、前記誘電体
基板を貫通させ前記誘電体基板の他主面まで延伸
させて設け、前記第2の導体の一端部と前記誘電
体基板を介して対向するように構成することによ
り、 (i) 同調回路にRFの接地がなく低損失であり、
さらにパタン化可能であるために、組立による
バラツキが少ない。
As described above, the present invention includes a ring-shaped resonator in which substantially U-shaped or semicircular first and second conductors are opposed to each other and provided on one principal surface of a dielectric substrate; 1. A capacitance section between the first and second conductors provided at one end where the second conductor faces each other, and a variable capacitance diode provided at the other end, the capacitance section comprising: One end of a first conductor provided on one main surface of the dielectric substrate is provided by penetrating the dielectric substrate and extending to the other main surface of the dielectric substrate, and one end of the second conductor is provided so as to penetrate the dielectric substrate and extend to the other main surface of the dielectric substrate. By configuring them to face each other via the dielectric substrate, (i) there is no RF grounding in the tuning circuit, resulting in low loss;
Furthermore, since it can be patterned, there is little variation due to assembly.

(ii) 回路が閉ループとなるために電磁界の漏洩が
少ない。
(ii) Since the circuit is a closed loop, there is little leakage of electromagnetic fields.

(iii) サスペンデツド構造とすると、基板の誘電体
損失を低減でき同時に温度特性の改善が期待で
きる。逆に基板としては誘電体損失が多少悪く
ても問題とならないため、低コストの基板(た
とえばエポキシ・ガラス等)を用いることがで
きる。
(iii) A suspended structure can reduce the dielectric loss of the substrate and at the same time can be expected to improve the temperature characteristics. On the other hand, a low-cost substrate (for example, epoxy glass, etc.) can be used as a substrate because it does not cause any problem even if the dielectric loss is a little bad.

等の効果を有し、その工業的価値は大なるものが
ある。
It has the following effects and has great industrial value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の電子同調チユーナの原理構成
図、第2図A,Bは本発明の電子同調回路の原理
を説明する平面図、第2図Cは第2図A,Bの等
価回路図、第2図Dは同電子同調回路の同調電圧
と共振周波数との関係を示す特性図、第2図Eは
同電子同調回路の無負荷Q周波数の特性図、第2
図Fは同電子同調回路の2段構成におけるBPFの
特性図、第3図A,B,Cは本発明の一実施例に
おける電子同調回路の要部である共振回路部の平
面図、第3図Dは同断面図、第4図Aは他の実施
例の平面図、同Bは同断面図、第5図は同電子同
調回路の構成例を示す断面図、第6図Aは同電子
同調回路の平面図、同Bは同断面図である。 28,29……共振線路部、30……可変容量
ダイオード、32……直流電圧端子、33……チ
ヨークコイル、34……コンデンサ、35……誘
電体基板、51……金属筐体。
Fig. 1 is a basic configuration diagram of a conventional electronic tuning tuner, Fig. 2 A and B are plan views explaining the principle of the electronic tuning circuit of the present invention, and Fig. 2 C is an equivalent circuit diagram of Fig. 2 A and B. , Figure 2D is a characteristic diagram showing the relationship between the tuning voltage and resonant frequency of the electronic tuning circuit, Figure 2E is a characteristic diagram of the no-load Q frequency of the electronic tuning circuit,
FIG. Figure D is a cross-sectional view of the same, Figure 4A is a plan view of another embodiment, Figure B is a cross-sectional view of the same, Figure 5 is a cross-sectional view showing an example of the configuration of the electronic tuning circuit, and Figure 6A is a plan view of another embodiment. A plan view of the tuning circuit, and B is a sectional view thereof. 28, 29... Resonance line section, 30... Variable capacitance diode, 32... DC voltage terminal, 33... Chiyoke coil, 34... Capacitor, 35... Dielectric substrate, 51... Metal casing.

Claims (1)

【特許請求の範囲】[Claims] 1 略U字状、あるいは半円形状の第1,第2の
導体を互いに対向させることにより形成したリン
グ状の共振線路を誘電体基板の一主面上に設ける
とともに、前記第1,第2の導体が互いに対向す
る一端部に前記第1,第2の導体間の容量部を設
け、また他端部に可変容量ダイオードを設け、前
記容量部は、前記誘電体基板の一主面上に設けた
前記第1の導体の一端部を、前記誘電体基板を貫
通させ前記誘電体基板の他主面まで延伸させて設
け、前記第2の導体の一端部と前記誘電体基板を
介して対向するように構成した電子同調回路。
1. A ring-shaped resonant line formed by substantially U-shaped or semicircular first and second conductors facing each other is provided on one main surface of the dielectric substrate, and the first and second A capacitance section between the first and second conductors is provided at one end where the conductors face each other, and a variable capacitance diode is provided at the other end, and the capacitance section is located on one main surface of the dielectric substrate. One end of the first conductor provided extends through the dielectric substrate to the other main surface of the dielectric substrate, and is opposed to one end of the second conductor via the dielectric substrate. An electronic tuning circuit configured to
JP2150376A 1976-02-26 1976-02-26 Electronic tuning circuit Granted JPS52104034A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2150376A JPS52104034A (en) 1976-02-26 1976-02-26 Electronic tuning circuit
US05/771,987 US4121182A (en) 1976-02-26 1977-02-25 Electrical tuning circuit
CA272,748A CA1097755A (en) 1976-02-26 1977-02-25 Electrical tuning circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2150376A JPS52104034A (en) 1976-02-26 1976-02-26 Electronic tuning circuit

Publications (2)

Publication Number Publication Date
JPS52104034A JPS52104034A (en) 1977-09-01
JPS6113641B2 true JPS6113641B2 (en) 1986-04-15

Family

ID=12056762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2150376A Granted JPS52104034A (en) 1976-02-26 1976-02-26 Electronic tuning circuit

Country Status (1)

Country Link
JP (1) JPS52104034A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62281908A (en) * 1986-05-30 1987-12-07 白木金属工業株式会社 Reclining apparatus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2510325B1 (en) * 1981-07-24 1987-09-04 Thomson Csf SMALL DIMENSIONAL MICROWAVE FILTER WITH LINEAR RESONATORS

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62281908A (en) * 1986-05-30 1987-12-07 白木金属工業株式会社 Reclining apparatus

Also Published As

Publication number Publication date
JPS52104034A (en) 1977-09-01

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