JPS61134169A - Color picture reader - Google Patents

Abstract

PURPOSE:To read a color picture with a high resolution at a high speed by equipping plural processing means for applying the prescribed processing to read-out outputs of plural line sensors for dividing and reading a color picture and forming a color picture signal of one continuous line with the aid of each processing signal. CONSTITUTION:Five CCD chips 21-25 are installed in a staggered pattern on an adhesive-type color CCD sensor unit 11. In terms of the sensor signal processing part of the CCD chip, an output signal from the CCD chip 21 is separated by a color by a multiplexer 132 through a buffer circuit part 131, and a real output according to light can be obtained in a dark level removing part 133. A color converting part 134 outputs an primary color signal from each color output from the dark level removing part 133. After said signal is converted into a digital signal in an A/D converting part 135, it is stored in a memory part 139. The sensor signal processing parts are independently provided with respect to five CCD chips, and act in parallel. Accordingly the time necessary for processing a picture of one line can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color image reading device for inputting color image data in devices that electrically handle image information, such as digital copying machines, facsimiles, and electronic files.

2. Description of the Related Art Line sensors are known in which a plurality of light receiving elements are arranged in a line in order to photoelectrically read the shading of a color original image. I am currently using an A4 size black and white document in the short direction (approximately 2 L).
0mm) at a resolution of 16 pixels/mm, one line sensor having approximately 3,500 light receiving elements is required. However, it is difficult to form such a large number of light-receiving elements on the same substrate without missing parts and with approximately uniform sensitivity, and therefore, it is not practical in terms of cost unless yields are improved. Furthermore, when reading a color image, three times as many light receiving elements are required in order to read the same resolution, which is of course not practical.

Therefore, by arranging multiple line sensors in the scanning direction,
It is conceivable that one line of image is divided and read by each line sensor. In this way, since the number of light receiving elements to be formed on the same substrate is not so large, the yield can be improved and the above-mentioned cost problem associated with it can be solved to some extent.

Furthermore, when reading a color image, the color image must be separated into a plurality of colors (for example, three colors) and read, so the amount of information is approximately three times that of black and white reading.

Therefore, in order to process this color image information at high speed, each element making up the processing circuit needs to operate at high speed, which poses a cost problem and the reading speed is at the limit of the processing speed of each element. The speed may be suppressed, which may prevent speeding up.

The present invention has been made in view of the above points, and an object of the present invention is to provide a color image reading device that can read high-resolution color images at high speed.

That is, a plurality of line sensors that divide and read a color image, a plurality of processing means that perform predetermined processing on the read output of each of the plurality of line sensors, and a processing signal of each of the plurality of processing means to form one line. The present invention provides a color image reading device having means for forming continuous color image signals.

According to this, since one line of image data is divided and processed, the processing circuit does not need to operate at high speed, and it is also cost effective.

Next, an embodiment of the present invention will be described with reference to the drawings. In this embodiment, a color contact sensor is used to read the original. FIGS. 1(a) and 1(b) show the configuration of a reading section using this color contact sensor. Figure 1 (
As shown in a), a senna unit 11 equipped with a plurality of CCD chips, a focusing rod lens array 12 disposed on this senna unit 11, and a focusing rod lens annoy 12 are provided near the side surfaces of the senna unit 11 equipped with a plurality of CCD chips. The linear light source 13 forms an integral structure. However, in Figure 41(a),
Although only one linear light source is shown, one more linear light source is actually provided so as to sandwich the rod lens array 12. With this configuration, the convergent rod lens array 12 is connected to the light source 13.
The light reflected from the document irradiated by the light beam is coupled onto a plurality of CCD chips in a one-to-one relationship without being reduced equally.

In addition, the sensor unit 11, the focusing rod lens array 12, and the light source 13 are connected to the signal processing board 16, the sensor unit 11, and the signal processing board 16, as shown in Fig. s1 (b).
It is mounted on the movable body 14 together with the flexible electric wire 15 connecting the movable body (original scanning unit) 1.
7 lexiple electric wire 17 is used for connection between 4 and the main body.

The optical image formed on the CCD chip of the senna unit 11 as described above is converted into electric charge by the photoelectric conversion capability of the CCD.

This charge is sequentially transferred by the charge transfer ability of the CCD and becomes an image signal.

Each part will be explained in detail. As shown in FIG. 2, the contact type color CD sensor unit 11 includes a ceramic substrate 26 on which five CCD chips 21 to 25 arranged in a staggered manner are provided, and a cover 27 that covers the ceramic substrate 26. , flexible electric wires 28a to 28f for connection. The CCD chips 21 to 25 each have a light receiving section consisting of a p-n photodiode, and the size of the light receiving section is 62.5 μm.
As shown in FIG. 4, the photosensitive pixels are 24-pit light-shielded pixels DI3-D36. 36-bit dummy pixels D37 to D72, 3072-bit effective signal pixels S1 to 83072, 24-bit rear end dummy pixel D73
- D76, a total of 3168 bits of light receiving sections.

Further, the CCD chips 21 to 25 as described above are arranged in two rows in a staggered manner as shown in FIG. In this case, adjacent CCD chips, for example, CCD chips 22 and 23, are provided with a distance l between the centers of their light receiving sections in the sub-scanning direction, as shown in FIG. Also, these C
The CD chips 21 to 25 are arranged so as to overlap each other along the arrangement direction (main scanning direction).

In this embodiment, the center distance l is a distance of four pixels.

As described above, the light receiving parts of the CCD chips 21 to 25 are arranged in the empty feed areas D1 to D12 and the light shield area DI3 from the left end.
~D36, dummy area D37~D72, effective pixel 15
1i area S1~83072, rear end dummy area D73~D9
It consists of 6.

Of these, 3072 bits of effective pixel area S1 to 8307
They are arranged in such a way that they overlap each other using the areas except for 2. As a result, the effective reading area is 29 mm wide on the short side of A3 size paper.
It will be 320al, slightly longer than 7m.

Light receiving part (photodiode) of COD chips 21 to 25
A color filter must be placed above to receive the color signal. This method includes a method of bonding a color filter and a Si element, which is a photodiode, with adhesive;
There is a method of laminating color filters directly on the Si element.

In the former case, the color filter can be manufactured on a glass substrate, but requires an extra step of adhesion when combined with the Si element, and is likely to cause alignment errors. It is difficult to suppress this adhesion error to less than a few μm, and color reproducibility and
This may cause deterioration of shading characteristics. On the other hand, in the latter case, the color element is completed by simply manufacturing color filters in accordance with the pixels of the SL element, so the process is extremely simple and the accuracy of one alignment can be greatly improved. Therefore, the latter color filter is used for the CCD chip used in this embodiment.

Next, a specific filter array will be explained.

In this embodiment, three color filters of yellow (Ye), green (G), and cyan (Cy) are arranged in this order as shown in
C, repeated arrangement, 1 when reading with 3 adjacent bits
It constitutes a pixel. The outside of the filter is already more shielded.

The spectral characteristics of these color filters are shown in FIG. 46
As is clear from the figure, the transmittance of the Ye filter is curve 6.
As shown in 1, it increases rapidly from around 500 nm.

The transmittance of the Cy filter is 5Q as shown by curve 62.
A peak is shown near Qnm. In this example, the G filter is obtained by superimposing a Cy filter and a Ye filter, so the transmittance is so as shown by curve 63.
A peak is shown near onm. The important point in the spectral characteristics of these filters is that
The point is that the transmittance does not become zero even for wavelengths on the order of QQnm.

Here, the color filters and COD chips 21 to 25 must perform a function similar to that of the human eye in order to achieve faithful color reproduction. As shown in FIG. 7, the spectral characteristics of the light receiving sections of the COD chips 21 to 25 reach a maximum at a wavelength of about 55 Q nm, and have a finite relative sensitivity up to 10001 m or more.

Finally, the light receiving section of the CCD chip provided with the color filter in this embodiment responds even to light having a wavelength of 7QQnm or more. On the other hand, the visibility of the human eye is zero for wavelengths of 7QQnm or more. Therefore, simply combining a CCD chip and Cy, G, and YeO color filters cannot perform the same functions as the human eye. Therefore, in this embodiment, the light source is specified as described later.

Next, the convergent rod lens array 12 will be explained.

As shown in FIG. 8, the convergent rod lens array 12 in this embodiment has a document surface 81 at the focal length on the light incident side, and two CCD chip rows 82 at the focal length on the exit side. By setting in this way, the original surface 81 and the CCD
The chip row 82 is in the imaging relationship. That is, the image on the original surface 81 is formed on the CCD chip array 82 as a 1:1 erect image. However, since the CCD chips are arranged in a staggered manner as described above, and there is only one focusing rod lens array 21, the erect images formed on the adjacent chips of the CCD chip row 82 in this embodiment are The resulting image is spaced apart by four lines on the surface 81. In order to solve this problem and obtain one line of continuous image signals, this embodiment uses a dedicated memory, as will be described later.

Next, the light source 13 will be explained. In this example, the light source]3
uses fluorescent lights. As mentioned above, the function required of a contact sensor as a color reading device is the ability to read colors in the same way as the human eye.

FIG. 9 is the basic curve of Thomson-Wright.

This curve shows the visibility characteristics of the human eye according to color, that is, the relationship between brightness perception for colored light and the wavelength of light. As is clear from the Pl, Pl, and P3 curves, the human eye does not sense light with long wavelengths of 700 nm or more.

On the other hand, as mentioned above, the spectral characteristics of the light receiving parts and color filters of the CCD chips 21 to 25 have a finite sensitivity value even to light with a long wavelength of 700 nm or more. When white light is made incident on the light receiving section 25, it will be perceived as light with a long wavelength of 700 nm or more.

Therefore, in this embodiment, a daylight-colored fluorescent lamp is used, which has almost no spectral characteristics in the long wavelength region of 700 nm or more. FIG. 10 shows the spectral characteristics of the above-mentioned fluorescent lamp. Furthermore, although a fluorescent lamp is a type of linear light source, the brightness is uneven in the length direction of the tube due to the influence of the filament, so the length of the tube is shown in Figure 11 in order to obtain uniform illuminance across the width of the A3 version. (for example, 3901!It)A
Illuminance non-uniformity within the 3rd edition width direction (297rm) is ±
It is set to be within 5%. Furthermore, in order to increase the amount of light, fluorescent lamps are equipped with reflective coatings on the inside and 3cm on the outer walls.
It has an aperture of 0°.

Now, FIG. 12 is a block diagram of a color digital copying apparatus using the above-mentioned contact type color COD sensor. The copying device 120 includes a color image reading device 121 and a color image printing device 122. Reference numeral 14 denotes a document scanning unit shown in the first diagram, which moves and scans (sub-scans) in the direction of arrow A in order to read the image of the document 123 on the document table. During this movement scanning, the exposure lamp 13 in the document scanning unit 14 is turned on, and the light reflected from the document is focused by the focusing rod/zu array 12 onto the CCD chip of the color COD nanosa unit 11.

As mentioned above, the contact type color CCD sensor unit 11 has 102
CC with 4 pixels (3072 bits) of effective signal pixels
Five D chips are arranged in a staggered pattern, and each pixel is divided into three parts of 15.5 μm x 62.5 μm, each with Cy
, G, and Ye color filters are attached.

Next, the electrical system related to the operation of the color CCD sensor 22) 11CD will be explained. The electrical system consists of an image sensor drive circuit that operates the CCD, an analog processing circuit that converts the output signal of the CCD into a form suitable for image information, and an analog processing section that converts the signal from the analog processing section into a signal suitable for the recording format. It consists of a digital processing circuit. Further, the analog processing circuit and the digital processing circuit are collectively referred to as a sensor signal processing section.

First, the image sensor drive circuit will be explained. However, in the following explanation, a driving circuit for the CCD chip 21 will be taken as an example. This drive circuit is connected to the CCD chip 21 as shown in FIG.
Two-phase clock for driving 01. Me. , scanning synchronization signal S
H, reset signals R, S and output signal O8 of CCD21
handle.

An inverter 141 is connected to the input terminal of the clock signal 1, and a resistor 142 and a speed-up capacitor 143 are connected in parallel to the output of the inverter 141.
Furthermore, it is connected to an input terminal of a MOS clock driver 144.

The output terminal of this MOS clock driver 144 is a CCD
Connected to the y11 terminal of the chip 21. Clock signal DA2 is also similar to clock signal G1. Also, an inverter 141, a resistor 142, a capacitor 143, and a MOS clock driver 144 are connected to the scan synchronization terminal SH and the reset signal R8, similarly to the clock signals *1 and *2.

An emitter follower consisting of an npn transistor 145, a collector resistor 146, and an emitter resistor 147 is connected to the output signal O8 terminal. In addition, the power supply voltage +V of the CCD chip 21 is applied to the CCD through capacitors 148 and 149.
It is supplied to the OD terminal of the chip 21.

The two-phase clock lL+12 is a signal necessary for bit-serially transferring the charges generated in each bit of the CCD chip 21.

The scan synchronization signal SH is a signal that distinguishes one scan in the charge transfer of the CCD chip 21, and the reset signal R8 is a signal that erases the bit (charge) after the charge of each pixel has been transferred. In addition, the signal O8 is a two-phase clock 1. This is the output signal from the CCD chip 21 that is output in synchronization with the image sensor 2. As shown in FIG. Outputs a black level signal. The bit positions of these signals are accurately defined, and the reference black level signal is a dark signal of the light receiving section, and is used to obtain a true output corresponding to the color.

Next, the Senna signal processing section is shown in FIG. This senna signal processing section is provided independently for each CCD chip 21-25. Here, a circuit for the CCD 21 will be explained as a representative.

As shown in FIG. 13, the output signal O8 from the CCD chip 21 is passed through the buffer circuit section 131 and converted into cyan (Cy), green (G), yellow (Ye),
The signals are input to a multiplexer 132 that separates the signals for each color of black (BK).

Then, in the dark level removing section 133, the output signals of each color (Cy, G
, Ye)? The difference from the reference black level signal (BK) from the /lzl gutter 132d is taken to obtain a true output corresponding to the light, which is further amplified to a voltage to be input to the next stage color conversion section 134.

The color conversion unit 134 outputs primary color signals of blue (B), green (G), and red (R) from the outputs of each color (Cy, G, Ye) from the dark level removal unit 133, and
This primary color signal (
R, G, B) is amplified and output. The AD converter 135 converts the signal from the color converter 134 into a digital signal,
This signal from the human/D conversion section 135 is stored in the memory section 139.

The multiplexer 132 is connected to the buffer circuit section 13 as described above.
It consists of four sample and hold (S/H) circuits 132a to 132d that separate the output signals from 1 for each color. Further, the dark level removing section 133 includes three differential amplifiers 133.
It consists of a to 133c. The color conversion unit 134 receives the signal Cy
, G, Ye f: Consists of three differential amplifiers 134a to 134C that convert the G signal into signals B, G, and R as a reference. A/D converter 135 is three A/D converters 135 that convert the amplified signal for each color into a digital signal.
a to 135C, and three latch circuits 136a to 136C that double-check their digital outputs. In this embodiment, an analog processing circuit system including A/D converters 135a to 135C is mounted on the signal processing board 16 of the document scanning unit 14, as well as a contact type color CD sensor unit 11, and a latch circuit 136a. ~136C is connected to a main body board 124 including a memory section 139, a digital signal processing section, etc. to be described later, and a flexible electric wire 17. In this way, a digital signal is transmitted from the scanning unit 14 to the main body substrate 124, which is less susceptible to noise and the like, thereby making it possible to reproduce a good image.

The memory section 139 consists of storage areas 139a to 139C provided for each of R, G, and B.

The above is the main configuration of the senna signal processing section provided corresponding to the CCD chip 21, but in addition to these elements,
Several control elements are provided. These will be explained together with the circuit operation using the detailed drawings below.

FIG. 15(a) shows a detailed circuit configuration of the signal processing board 16 on the original scanning unit 14. In FIG. 15(a), reference numeral 17-1 refers to a document scanner unit 14 that includes a moving part such as an image sensor, an illumination lamp, an analog processing circuit of the senna signal processing section, an image senna drive circuit, and an optical lens system. Multiple types of clock pulses for driving the Senna (CCD) and Senna signal processing section,
And it is a flexible electric wire that supplies power. on the other hand,
1.7-2 is a flexible electric wire for sending the digital color signal from the senna signal processing section to the main body.

153 is a clock buffer receiver that receives a plurality of clock pulses sent through the flexible electric wire 17-1; and 151-j is an image sensor clock driver that boosts the signal from the clock buffer receiver to a voltage at which the image sensor can operate. , 21 is an image sensor (CCD) that reads the original image on the original table glass;
156 is an image signal VID output by the image sensor 21
A sample hold circuit for capturing and holding time-series color pixel signals of BK, C, G, and Y during EO is provided with sample pulses corresponding to each color:, SMPC, SMPG, SMPY
and a sample hold driver driven by SMPKK; 157 is a BK output from the image sensor 21;
C,G.

A buffer transistor 158 receives and receives the Y time-series color pixel signal, and 158 is a demultiplexer buffer for transmitting the BK, C, G, and Y time-series color pixel signals output from the buffer transistor 157 to the sample-hold circuit for each color. It is a transistor.

1509 to 1512 are 77 C, G, Y, and BK time-series color pixel signals output by the image sensor 21, respectively.
C transistor switch, C transistor switch, Y
Transistor switch, BK transistor switch, 1
514 to 1517 are the above transistor switches 1509
~1512 output voltages respectively as cyan signal voltage VC'
*Green signal voltage VG', yellow signal voltage ■7 and black level signal voltage "C hold capacitor, C hold capacitor, Y hold capacitor %BK hold capacitor that holds at BK. 1518~15
Reference numerals 20 denote a C high input differential FET, a C high input differential FET, and a Y high input differential FET, which remove and amplify the vBK component contained in the above v'CI ``G + ''l.

1521~]523 is the above C, o, Y can high input differential F
ET 1518 to 1520, the Vnx component is removed and the color pixel signals are amplified by α, β, and r times, that is, α
Vc, βvG, ray K C level shifter transistor that removes the included DC component, G level shift transistor, Y level thick transistor, 1524-1
526 is the level shift transistor 1521 to 15 mentioned above.
They are a C emitter follower transistor, a C emitter follower transistor, and a Y emitter follower transistor, respectively, which convert the output of 23 into a low output resistance.

1527 receives the output from the C emitter follower transistor 1524 and the C emitter follower transistor 1525, extracts the difference component of both signals, and amplifies it by 1/I, that is, produces a color difference signal of I/H・■8. A differential amplifier buffer 1528 is a G differential amplifier buffer 152 which receives the output from the C emitter follower transistor 1525 and amplifies it by a factor of 1/J, that is, 1/J-vG.
9 receives the output from the C emitter follower transistor 1525 and the output from the Y emitter follower transistor 1526, extracts the difference component between both signals, and amplifies it by a factor of 1/I, that is, a color difference signal of 1/I·vR. R to produce crops
It is a differential differential amplifier buffer. 1530 is a BA/D converter that converts the analog pixel signal output from the B differential amplifier 1527 into a digital pixel signal according to A/D clock B, and 1531 converts the analog pixel signal output from the G differential amplifier buffer 1528 into an A/D converter. GA/D converter 1532 converts the analog pixel signal output from the R differential amplifier buffer 1529 into a digital pixel signal according to the A/D clock R; It is.

1533 is a line driver for receiving the blue, green, and red digital pixel signals respectively output from the A/D converters 1530 to 1532, and transmitting each color digital pixel signal to the main body via the flexible electric wire 17-2; A voltage reference 1534 supplies a reference voltage for digital conversion to each A/D converter 1530 to 1532.

The operation of the image sensor drive circuit and sensor signal processing section will be explained below with reference to FIGS. 15(a) and 15(b). As mentioned above, the senna unit 11 of this embodiment is composed of five COD chips 21 to 25, and each of the five COD chips is provided with a circuit described below independently and operates in parallel. Therefore, the time required for image processing for one line is shortened, and each element such as an A/D converter does not need to operate at such high speed.

To operate the image sensor 21, see Figure 15(b).
■SH pulse, ■5!11 pulse, ■Da2 shown in
Pulse, ■RS pulse is required.

The role of these pulses is as described above, but due to the nature of the image sensor, these drive pulses require a higher pulse voltage than the pulse voltage on the main body side. Therefore, each sensor and driving pulse generated by the CCD pulse generator 137 shown in FIG. Further, the image sensor clock driver 154 forms the above-mentioned high pulse voltage and then applies it to the image sensors 21 to 25.

The image sensor receives this pulse voltage and generates cyan, green, and yellow color separation signals v, s'' according to the human power light.
G + ``'Y and the aforementioned light shield pixel signal ``BK'' are outputted in time series as shown in FIG. 15(b) ``.

The image sensor driven by the above-mentioned image sensor drive circuit is exactly VBK + "C + Vc,
Vy , v ; analog signal processing and digitization of analog quantities must be performed. One of these analog processes is color conversion. This converts the cyan, green, and yellow color pixel signals output by the Senna into blue, green, and red by performing mutual calculations on a pixel-by-pixel basis. This is directly blue as a characteristic of 7/su.

Higher signal levels (higher contrast signals) can be obtained by outputting cyan, green, and yellow signals than by outputting green and red signals; on the other hand, the characteristics of the digital color image processing section are that blue, green, The sensor outputs cyan due to mutual discrepancies, such as the circuit being simpler when receiving a red signal.

It takes the trouble to convert green and yellow signals into blue, green, and red signals. Another analog process is to remove floating voltage components uniformly contained in the cyan, green, and yellow color separation signals output by the image sensor. This floating voltage component is as follows ■BK
However, this is caused by the dark voltage fluctuation of the photodiode inside the image sensor and the charge fluctuation of the CCD channel, etc., and the output voltage of the image sensor Vc', ■6'
, VY' are considered to exist at the same level. Therefore, before performing the above color conversion, this floating voltage component VBK is removed from each color component to extract a pure color signal voltage component. Another analog processing step is to match the color converted blue, green and red analog quantity color signals to the input levels of the A/D odor transformer to convert them to digital quantities. Furthermore, other analog processing is performed in order to perform the above-mentioned color conversion, that is, between color pixel signals sent in time series in the order of cyan → green → yellow, VC-V, or VY-v is used.
This is a process of parallelizing the time series in order to perform the G subtraction process.

The operation related to the color conversion process of the Senna signal processing section will be explained with reference to FIGS. 15(a) and 15(b). First, considering that the above-mentioned floating voltage component VBK is included in the time-series color signal output from the image sensor, this time-series color signal is expressed as Vc'=(VC+VBK).

Vc' = (Vc + Vax) - vy' = (VY + VB
K ) Toruko (!: K. The image sensor time-series color signal applied to the base of the buffer transistor 157 and the floating voltage components, Vc', VC', v
Y'l VBK is input to the multiplexer buffer transistor 158. This transistor 1
58 emitters have 15 transistor switches for each color.
09 to 1512 are connected in a reverse bias state. When the sample pulse from the sample and hold drive transistor 156 does not come, the resistance between the emitter and collector of each transistor switch becomes high, and the sample and hold capacitors 1514 to 1 connected to the converter become high resistance.
517 high input and differential F]] T1518-1520 become disconnected from the emitter of demultiplexer buffer transistor 158. This is a signal hold operation.

On the other hand, ■, ■, and ■ in FIG. 15(b) are sent from the main body by the flexible electric wire 1.7-1.

Sample pulses SMPK, SMPC, and SMPG of black, cyan, green, and yellow shown in (2).

When S = vf P Y is applied to the sample-and-hold drive transistor group 156 at the appropriate timing shown, each sample pulse is given error ref'C order K
, f Sub (E) Time series VBK , Vc', V
The emitter voltages of the transistor 158, c' and Vy', are transferred to the sample-and-hold capacitor in the order of 1517°, 1514.1515.1516. Here, each time series color signal voltage and floating component voltage are divided into parallel respective vB K + "c' * VG' - Vy',
That is, it is demultiplexed. As each temple passes, each transistor switch immediately becomes high voltage LQK fx ReV8K, Vc'
, Va', Vy' null voltages remain held in their respective sample and hold capacitors 1514-1517.

Sample hold condenser? The drain output voltage of three high-input differential FETs 1518 to 1520, in which one differential input is connected to each of 1514 to 1516 and the other input is connected to a hold capacitor 1517 for floating voltage components, is based on the characteristics of a differential amplifier. It generates an output voltage as shown below.

O differential FET output 1518 cc (VC' VoK) Fα (Vc+#ox-Vox
) = αVc - (1) where α is the voltage gain of the FET circuit with O differential FET output 1519 β (Vc' VDK) = β (VC + VDK
) = βVG - (2) However, β is the voltage gain of this FET circuit, O differential FET output 1520 r (Vy' Vox) = r (Vy + Vox - Vox)
= rVy =... (3) However, γ is the voltage gain of this FET circuit, as shown in the above formula (1), (21, (3))
At the output, color pixel signals αVc, βVG, and rvY from which the floating component voltage VDK is removed and multiplied by a constant gain appear (FIG. 15(b) [phase], @, @).

The gain coefficients α, β, and γ shown here are matrix constants necessary for color conversion. That is, the following calculations are required to create signals VB and V corresponding to blue and red from cyan, green, and yellow signals.

H0VB=α, ■c−βvG However, H is a constant...
・・・・・・(4) J, vo=β■G However, J is a constant ・・・・・・・・・(5) ■, VR=γ, ■Knee β■G However, I is a constant...・・・・・・(6)
The outputs of the high power differential FETs 1518 to 1520 are applied to level thick transistors 1521 to 1523, and after the DC offset voltage superimposed on each color pixel signal αvO9βvG, γvY is removed in parallel, the outputs are applied to emitter follower transistors 1524 to 1523. 1526. αV□ rβv0 . Each color pixel signal of .gamma..D is applied to color difference detection differential amplifier circuits 1527-1529.

The differential amplifier buffer 1527 has α given to its input.
, VO+β・■G by performing the arithmetic operation shown in equation (4) based on the characteristics of the differential amplifier, and by removing the H term in equation (4) using its amplification ability, pure VB (Figure 15 (bl)
o). In addition, the differential amplifier buffer 1529 similarly receives each color signal voltage of γ・vY and βvG manually applied (
6) Perform the arithmetic operation shown in the formula and generate a pure or R color conversion output with one term removed by the amplification effect (
Figure 15 (blo). Furthermore, the differential amplifier buffer 152
8 operates as a normal amplifier buffer, and amplifies the color signal β■G sent from the previous stage, canceling the 5th term in equation 5), so that it has a 1:1 ratio with respect to the above-mentioned VB + "R +.
A vG color signal is output. The above-described operations of the differential amplifier buffers 1527 to 1529 do not need to be performed at the same timing, but are performed using each color signal while maintaining the phase difference from the previous stage.

The color pixel signal converted into VB + "G + vR in this way is given to each A/D converter 1530 to 1532, and is outputted from the A/D' pulse generator on the main body side.
After analog-to-digital conversion according to the D conversion clock A/D CLKB, G, and R, the line buffer 153
The image is sent to the digital color processing section of the main body through a flexible forming line 17-2 driven by 3.

Here, the A/D converters 1530 to 1532 perform an A/D conversion operation based on one function that takes density correction (γ correction) into consideration for the image signal.

That is, it is a function conversion expressed by the formula: D=-1ogR D: optical reflection density 几: reflectance. For this conversion operation, the A/D converters 1530 to 1532 are configured to supply reference voltages necessary for quantization from outside, but the voltages applied between the multiple reference voltage setting terminals are equalized. A non-linear voltage 1534 is supplied without differentiation, and a polygonal function approximation is achieved.

In this way, the analog color pixel signal VB + ” which is the reflectance data that has undergone logarithmic A/D conversion and has its polarity inverted.
When G and vR exit the A/D converters 1530 to 1532, they are converted into 8-bit digital measurements and sent to the main body as concentration data lDG+DB. In this manner, the A/D converters 1530 to 1532 perform γ correction of the image signal at the same time as A/D conversion of the input analog color signal.

FIG. 24 shows the human output characteristics of the A/D converters 1530 to 1532 described above. As shown in the figure, there are three points of contact, and by connecting these points, the exponential function is approximated by a polygonal line. still,
This human output characteristic is set to be suitable for the characteristics of a sensor including a filter, a printer, etc.

As described above, the A/D converters 1530 to 1532 convert the 8-bit 256-gradation digital signals to -1.
, R. Concentration data DB corresponding to R.

DG r DB are provided on the main body side, and their phases are aligned by latch circuits 136 a - 136 c that perform a latch operation using a latch clock (CLK) output from an A/D pulse generator 138 . .

Here, the number of signals of this digital signal is evaluated. In this embodiment, the signals from the continuous CCD chips 21 are separated into three colors bit by bit by the multiplexer 132 as described above. Therefore, the number of signals for each color taken into the latch circuit 136 is as shown in FIG.
This is 1/3 of the number of signals from.

For example, the effective reading area in the CCD chip 21 is 3072.
Since it is a bit, the output signal corresponding to one color of R, G, and B is 1/3 of that, which is 1024 bits.

The above signals are stored in the memory section 139 according to the clock CLKI. The memory section 139 includes each CCD chip 2
1 to 25, and storage areas are set according to each color (R, G, B). For the CCD chip 21, storage areas 139a, 139b and 13 are provided in B, G and R.
9C is set respectively. Further, as will be described later, the capacity of this storage area varies depending on the arrangement of the CCD chips 21 to 25. In other words, as mentioned above, in this embodiment, 1
Since the image is focused by the book focusing rod lens array 12 onto the CCD chips 21 to 25 with a spatial distance of 4 lines, the first row of CCD chips 21, 23, 25
The images read by the CCD chips 22 and 24 in the second row at the same time are always viewed at positions shifted by four lines. Therefore, in this case, the image shift of four lines is corrected, and continuous signals of the same line are formed by the memory section.

Here, the memory sections 139a to 139c are static R
A M (Random Access Memory
), and the memory capacity for one line is 1 as mentioned above.
Since the signal is 8 bits per pixel, it is 1024×8 bits. Therefore, addresses are set in 8-bit units from 0 to 1023.

The writing and reading of information into and from the memo IJ 139a to 139C will be explained below, but particular attention should be paid to the arrangement of the CCD chips 21 to 25 and the removal of signal overlap in the main scanning direction by the focusing rod lens array 12. This is the connection between the signals in the sub-scanning direction.

FIG. 16 shows a memory control unit 140 that controls the memory unit 139 described above and a memo 'J139a corresponding to blue density data in the memory unit 139. The memory control unit 140 includes a write address counter 161, a read address counter 162, a memory block selector 163,
ゞC8 control unit 164.165.166, magnification selector 1
67.171 Consists of R/W control section 168.169.170.

The memory 139a includes a memory block 172 corresponding to the CCD 21, a memory block 173 corresponding to the CCD chip 22, and a memory block 1 corresponding to the CCD chip 23.
74, a memory block 175 corresponding to the CCD chip 24, and a memory block 176 corresponding to the CCD chip 25. Each of the memory blocks 172 to 176 is composed of a plurality of small memory blocks, and each of the small memory blocks has one memory block.
Color information for a line (8 x 1024 bits) is stored.

Next, each memory block 172~ of Memo'J 139a
The capacity of 176 will be explained. As shown in FIG. 3 and described above, the CCD chips 21, 23.25 and the CCD chip 22.
24 has a spatial distance of 4 lines. Considering that each COD chip normally has a two-line small memory block as a switching buffer, the data in which the images of each COD chip outputted from the small memory block are connected in the main scanning direction is stored in the CCD chip 21, 23°25 and CCD
This results in image data that is shifted by 4 lines in the area of chips 22 and 24. Therefore, in this embodiment, the image data of the CCD chips 22 and 24 that read images in advance in sub-scanning is stored line by line in a small memory block.
The trailing CCD chip 21, 23, 25 is the leading CCD chip.
When the CD chips 22.24 read the same line of image data, the CCD chips 22.2 were stored synchronously.
The image data of No. 4 is read out together with the CCD chips 21, 23, and 25. By doing this, the same line of data is always output from each CCD chip 121-25.

Let us now consider the number of small memory blocks that constitute each memory block. For example, adjacent C
Considering the relationship between the CD chip 21 and the CCD chip 22, when reading at the same magnification, there is a time difference of 4 lines before the CCD chip 21 scans the same line as the position currently being scanned by the preceding CCD chip 22. , after all, the preceding C
The difference in the number of small memory blocks between the CD chip 22 and the following CCD chip 21 is 4 lines. Since the following CCD 21 requires two lines for reading and writing, the preceding CCD 22 requires at least a small memory block of six lines in total.

Next, let us consider the case where variable-magnification reading is performed by varying the sub-scanning speed. Incidentally, the scaling in the main scanning direction is electrically performed by thinning out or padding the image signal. In this case as well, the timing of writing and reading is as described above, between the leading CCD chip 22 and the trailing CCD chip 22 and 24.
Since ゜23.25 is when scanning the same line, 4
If there is a spatial distance between lines, the magnification ratio will be set to a multiple of 1/4. Considering the above, the required number of memory blocks for each COD at each magnification is determined as follows.

CCD21, 23, 25: CCD22, 24 x 0.5x = 24 Xo, 75x: 25 x 1x = 26 N lines, number of leading CCD chips a1 number of trailing CCD chips, magnification unit B, maximum magnification L1 number of required memory lines for the leading COD chip M1 total number of lines A for the entire sensor has the following relationship roars.

B2l/NM2, N+1 A = a (L-N+2) +2b Therefore, in this example, the magnification of the variable magnification is Xo, 75. Xi.

Since the number of types is XL25, the memory block 17
2,174,176 are 2 lines, memory block 173
, 175 has a small memory block of 6 lines, and a total of 18 lines of small memory blocks per color.

Next, FIG. 18 shows a configuration diagram of a small memory block. Each of the small memory blocks consists of static RAM 182 (8
data selector 1 that switches between the static RAM 182 write address (W-ADDRESS) and read address (R, -ADDRESS)
81, a bus driver (BUSS driver) 183 that controls input and output of image data signals from the COD chip.

184, an OR circuit 185, and an inverter 186'.

Here, regarding the above control, the circuit diagrams in FIGS. 16 and 18 and the timing chart in FIG. 17 are used.

This will be explained with reference to FIGS. 19, 20, and 21.

In addition, FIG. 17 is a timing chart of the sensor signal processing section mentioned above, and FIG. 19 is a chip select signal C corresponding to each small memory block when reading Xo and 75x magnification.
FIG. 20 is a timing chart of the chip select signal C8 and the read/write signal R/W corresponding to each memory block during x1 magnification reading. Figure 21 is
Chip select signal C8 and read/write signal R corresponding to each small memory block during variable magnification reading of 81.25 times
/W timing chart.

First, we will explain the image reading control at the same magnification (×1) representing the three magnifications mentioned above. The operations of 23, 24, and 25 are representative.

In FIG. 16, the static R of each memory block
A write address counter 161 performs address control for writing data to AM by counting the clock CLKI, and a read address counter 162 performs address control for reading from the static RAM of each memory block by counting CLK2. At this time, the number of data written to each small memory block is 1024 pixels as described above, and when reading this, data (297 x 16 = 4752 pixels) must be read out at once. Therefore, the read address counter 16
The clock CLK2 applied to the write address counter 161 is 4.5 times the clock CLKI applied to the write address counter 161, and the clock CLK2 applied to the write address counter 161 is equal to the clock φ1. A frequency 1.5 times that of φ2 is required. Further, the read counter 162 is a 13-bit counter, and the lower 10 bits are outputted as a read address, and the upper 3 bits are outputted to the memory block selector 163.

The memory block selector 163 decodes the upper three bits of the above-mentioned address counter and determines the data width of each memory block 172-176.

In other words, since the data amount required to be output is 4752 for the total data amount 5120 (1024×5) in which the data of each memory block is connected to one line, it is necessary to remove the difference of 368 pits. Therefore, by specifying the initial value of the address output by the read address counter 162 and deleting the data before and after each COD chip, the total amount of data is set to 4752.

As mentioned above, 164, 165, and 166 are C8 control units, which include line counter 1 (1641) and line counter 1 (1) that count H3 and NC2 synchronized with printer line synchronization signal H8 and NC from the digital data processing unit.
line counter 2 (1642) operated by the LD signal from 641-), line counter 1 (1641) and line counter 2 (1642), and CS matrix circuit 1 that synthesizes the signals of memory block selector 163;
It consists of 643.

The C8 control section], 64, 165, and 166 are provided corresponding to the number of stages of the magnification ratio, and in this embodiment, Xi,
There are three sets corresponding to Xo, 75, and X 1.25, respectively.

168.169.170 are the above-mentioned R, /W control units, and C8 control units 164.165.170 corresponding to each magnification.
166 line counters 1 (1641) and 2 (164
The outputs of 2) are combined to create an R/W signal for each memory block. In addition, R/W control units 168, 169, 17
Similarly to the C8 control units 164 to 166, 0 is also provided for the number of steps of the magnification ratio.

The above-mentioned CS control units 164 to 166 and R/W control unit 1
C corresponding to each magnification made by 68-170
S, R/W signals are magnification selectors 167, 1'7
1, it is selected in accordance with the magnification and input into the static RAM of each memory block.

Now, Fig. 20 shows the C S when reading an image magnified by ×1.
, is a timing chart of R/W signals. The numbers 11.12 attached to C8 and R/W are small memory pads 17
2a, b, 21 to 27 are small memory blocks 173a
~173g, 31°32 is a small memory drive A7 174a
, b, 41 to 47 are the small memory block 175aNg, and 51.52 is the small memory block 176a.

It shows that each signal corresponds to b. When the preceding CCD chip 22 performs the first scan, the small memory block 17 of the memory block 173 corresponding to the CCD chip 22
Set C821 corresponding to 3a to “0” and set R/W21 to “
0''. In this state, the data selector 18 in FIG.
In other words, the write address (W-ADRESS) from the write address counter 161 is selected, and the path driver 183 is activated, and the data from the CccD chip is input to the static R and AM 182 via the path driver 183. be done. At the same time OR circuit 1
85, when R/W is "0"', write pulse W-C
LK (Figures 16 and 18) is static RAM
It is input to the WE terminal of I82. By doing the above, the scanning data of the first line of the CCD chip 22 is transferred to the small memory block 173a of the memory block 173.
The data is stored in the static RAM 182 of. At the same time, the data of the first line scan of the CCD chip 24 is stored in the small memory block 175a of the memory block 175.

Similarly, in the second line scan, C822 and R/W2
2 is selected, and the data of the second line is stored in static R and AM of the small memory block 173b of the memory block 173 corresponding to the CCD chip 22. In this way, images of 3° and 4 lines are stored, and when the fifth line is scanned, the following CCD chip 21 scans the same line as the CCD chip 22 scanned the first time. , the data obtained by this scanning is sent to the CCD chip 21.
Small memory block 1 of memory block 172 corresponding to
72a. Here, the data on the same line, that is, the data in the small memory block 172a and the data in the small memory block 173a are now complete.

When scanning the next 6th line, first, C811 is “0”.
", R/W 11 becomes "1", data selector 181
When S is “1”, B is selected and read address counter 1
The read address (R-ADRESS) from 62 is CC
It is input to the static RAM 182 of the small memory block 172a of the memory block 172 corresponding to the D chip 21, the master and WE are "1", and the C8 is "QM".

Since the bus driver 184 is set to "0" and selected by the inverter 186, data in the static RAM is outputted via the bus driver 184 in synchronization with the read address. Next, when C811 becomes 1", °C821
becomes "0", and the data in the static RAM of the small memory block 173a is output consecutively to the data in the small memory block 173a.

Thereafter, according to the timing chart of FIG. 20, the CS and R/W of each memory block are sequentially selected, input and output data, and output data connected to one line. This is done simultaneously for the three colors JG and B, as shown in FIG.

(A/D output B, G, R) Figure 19 is a timing chart of C8 and R/W signals when reading an image at XO, 75 times, and Figure 21 is Xl, 25 times. Control similar to the control is performed according to a timing chart.

As described above, the 8-bit color-separated image data signal DRe_DG_tDB with the same phase for the same pixel is read out from the memory 139 and subjected to the processing shown in FIG. 22 and thereafter. That is, the color correction circuit 221 performs the processing shown in (1) below, which is usually called masking, to form yellow W, Y, magenta M, and cyan C signals, and also generates a black plate.
The undercolor removal circuit 222 performs the process shown in (2) below.

(1) Masking... Input 9 pixel data p
DR + DG tDB is subjected to the matrix operation shown by the following formula to absorb unnecessary color components of printing toner, and Y
Forms IM and C signals.

Here, coefficient a1. bl, c1 (+=1 to 3) are masking coefficients that should be set to appropriate values.

(2) Darkening plate generation/undercolor removal...Y, M,
When the minimum value of the C signal, that is, MIN(Y, M, C)=, Y'=Y-ak, M'=M-β, c'20-γ
Each color signal Y' indicates the amount of toner to be printed.

M' and C' are determined, and BK=δk is used as a black printing plate for black printing. (α, β, γ, δ are set to appropriate values) Each image data Y', 'M' obtained in this way.

C' and BK (black) become the basic data of the toner image finally printed by the printer.As will be explained later, the color printer in this system uses the toner image 2M (magenta) of Ye (yellow). toner image,
The Cy (cyan) toner image and the BK (black) toner image are not printed out at the same time, but each image is transferred to transfer paper one after another, and the four colors are overlaid one after another to create the final color print image. We use the method of obtaining

Therefore, each color data Y', M' obtained here.

It is necessary to select C' and BK in accordance with the operation of the color printer, and the selector 223 selects y/ which is output from the blackout generation and undercolor removal circuit 222.

Select one color from M', C', and BK (black). Therefore, in this system, a single color image is read and printed out. This requires four document exposure operations and four toner image forming processes.

Now, the color separation image selected in response to the operation of the color printer 122 is separated into a character area such as characters, symbols, lines, etc. and a halftone image area such as a photograph by the image area separation circuit 224, and a halftone image is generated. For text areas, the multi-value processing circuit 225 performs multi-value processing (usually referred to as dither processing), and for the text area, the binarization processing circuit 226 performs 2-value processing using a single threshold value.
The image data that has been converted into a value and transferred at 256 gradations (8 pixels) is converted into a dot image of "IJ, 11QM" for each pixel.

FIG. 12 122 is a sectional view of the printer, and this color printer is an electrophotographic laser beam color printer and has a photosensitive drum 125. Further, FIG. 23 shows a detailed diagram of the latent image forming section. The image creation process will be explained. The color separation image read by the color reader 121 mentioned above is the second
The dot data is developed into a dot image through each block shown in FIG. 2, and the dot data corresponding to the color image finally modulates the semiconductor laser 231 shown in FIG.

The laser beam modulated in accordance with the image is scanned at high speed from A to B in FIG. 23 by a polygon mirror 126 rotating at high speed, reflected by a mirror 129, and uniformly charged by a charger 1211. Dot exposure corresponding to the image is performed on the surface of the photosensitive drum 125.

One horizontal scan of the laser beam corresponds to one horizontal scan of the image, and in this example, the width is 1/16 mm.

- Since the force photosensitive drum 125 is rotating at a constant speed in the direction of the arrow, the above-mentioned laser beam scans in the main scanning direction, and the constant rotation of the photosensitive drum 125 in the sub-scanning direction causes the photosensitive drum 125 to be rotated at a constant speed. A planar image is exposed to light.

An electrostatic latent image is formed on the photosensitive drum 125 by such laser exposure, and by developing this latent image with the developing sleeve 1218, a toner image corresponding to the input image data is formed on the photosensitive drum 125. For example, considering the first exposure scan of a document in a color reader, first, a dot image of the yellow component of the document is exposed on the photosensitive drum 125 by the laser 231 and developed by the yellow developer 1221 . Next, this yellow image is transferred onto the sheet of paper 232 wound around the transfer drum 1210 by a transfer charger 1221 provided at the contact point between the photosensitive drum 125 and the transfer drum 1210. This same process is M (magenta).

By repeatedly overlapping Cy (cyan) and BK (black) on the paper sheet 232, a color image using four-color toners is formed.

In this way, the paper sheet 232 on which the four-color image has been transferred is peeled off from the transfer drum 1210 by the peeling claw 1222 in FIG. Roller 1225.1226
The color toner image is fused and fixed onto the paper sheet to obtain a printed image.

In Fig. 12, 1229 and 1230 are cassettes for storing paper sheets, 1231 and 1232 are paper feed rollers, and 1233 to 12
Reference numeral 35 denotes a timing roller that takes the timing of paper feeding and conveyance, and the paper sheet fed and conveyed via these rollers is guided to a paper guide 1236, and as shown in FIG. The transfer drum 1 is carried by the gripper 23'3.
210 and proceed to the image forming process. On the other hand, the first
FIG. 2 1240 shows the photosensitive drum 1 formed by the laser exposure described above.
This is a developing device unit for each color for developing the electrostatic latent image formed on the surface of 25, and rotates 90 degrees around P.

1218Y, 1218M, 1218C, and 12188 are development sleeves 1220Y and 1220M that contact the photosensitive drum 125 and perform direct development of each color.

1220C and 12208 are toner hoppers for holding spare toner, and 1219 is a screw for transporting developer.

In such a configuration, for example, when forming an M (magenta) toner image, the developing device Snit rotates around P in FIG. is placed. As a result, the electrostatic latent image formed on the photosensitive drum 125 is developed with magenta toner.

Incidentally, development of Cy (cyan) and BK (black) is operated in the same manner.

As described above, it is possible to faithfully read a document image and form good image data for image reproduction. Further, it is possible to provide an image reading device capable of reading a document image at variable magnification and reading a color document image.

[Brief explanation of the drawing]

1(a), (BL is a diagram showing an example of the configuration of the reading section, FIG. 2 is a diagram showing an example of the configuration of the color CD sensor unit, FIG. 3 is an explanatory diagram of the arrangement of adjacent CCD chips,
Figure 4 shows each area of the CCD chip, Figure 5 shows the CC
FIG. 6 is a diagram showing the spectral characteristics of each color filter. FIG. 7 is a diagram showing the spectral characteristics of the light receiving section. FIG. 8 is a diagram showing the configuration of a part of the reading section. , FIG. 9 shows Thoms on -Write
FIG. 10 is a diagram showing the spectral characteristics of a fluorescent lamp. FIG. 11 is a diagram showing the relative brightness of a fluorescent lamp. FIG. 12 is a diagram showing an example of the configuration of a color digital copying machine. Figure 13 is a block diagram of the sensor signal processing section, Figure 14 is a configuration diagram of the image sensor drive circuit, Figure 15 (al is a diagram showing the circuit configuration of the signal processing board, Figure 15 (bl is Figure 15) (A timing chart diagram showing the operation of each part of the signal processing circuit of al. FIG. 16 is a block diagram showing the configuration of the memory section and memory control section. FIG. 17 is a timing chart diagram showing the operation of each part of the signal processing section. The figure is a configuration diagram of a small memory block, FIGS. 19, 20, and 21 are timing charts showing memory read and write operations, and FIG.
The figure is a block diagram showing the configuration of a digital color signal processing circuit. 12 is a focusing rod lens array, 13 is a light source, 16 is a signal processing board, 17 is a flexible electric wire, 2
1 to 25 are CCD chips, 132 is a multiplexer, 1
33 is a dark level removal section, 134 is a color conversion section, 135
139 is an A/D conversion section, and 139 is a memory section. Zero arrival Lord electric power θ O [phase] ■ ■ @ ■ [stock] ■O■O■ ■
OO■ Figure 24 VD*I device output output data

Claims (1)

[Claims] A plurality of line sensors that divide and read a color image, a plurality of processing means that perform predetermined processing on the read output of each of the plurality of line sensors, and one continuous line using processing signals of each of the plurality of processing means. 1. A color image reading device comprising means for forming a color image signal.