JPS61133779A - Vertical line warp correction circuit - Google Patents

Vertical line warp correction circuit

Info

Publication number
JPS61133779A
JPS61133779A JP25524284A JP25524284A JPS61133779A JP S61133779 A JPS61133779 A JP S61133779A JP 25524284 A JP25524284 A JP 25524284A JP 25524284 A JP25524284 A JP 25524284A JP S61133779 A JPS61133779 A JP S61133779A
Authority
JP
Japan
Prior art keywords
circuit
phase
pulse
horizontal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25524284A
Other languages
Japanese (ja)
Inventor
Masaharu Ishibashi
石橋 正晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP25524284A priority Critical patent/JPS61133779A/en
Publication of JPS61133779A publication Critical patent/JPS61133779A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To display original vertical line image to the extent that the warp cannot deteced by human eye, by adjusting and feeding back the phase, etc. output signal of the frequency division circuit which divides the output pulse of the horizontal oscillation circuit to the output terminal of the horizontal oscillating circuit. CONSTITUTION:An attenuator 21 adjusts the level of the input pulse and sends it to a phase adjuster 22 where phase is adjusted. The output pulse of the phase adjuster 22 is added to the output pulse of horizontal oscillating circuit 4 by an adder 23. When the division ratio of a division circuit is 1/2, the output pulse of the horizontal oscillating circuit 4 deviates its phase by alpha for every 2H as shown in the diagram A, but as the pulse of cycle 2H as shown in the diagram B picked up by a phase adjusting circuit 22 is added to horizontal oscillating pulse as shown in the diagram B at the adding point 23, the pulse which has constant 1H phase as shown in the diagram C is supplied to the input terminal of a horizontal drive circuit 5.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は縦線曲がり補正回路に係り、特に高圧出力回路
やスイッチング電源回路等の、水平発振回路の出力信号
周波数を分周回路により整数分の一に分周して得た信号
により動作する回路を有するラスタースキャン方式の表
示装置において、画面上の縦線の曲がりを補正する縦線
曲がり補正回路に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a vertical line bending correction circuit, and in particular to a circuit that divides the output signal frequency of a horizontal oscillation circuit, such as a high-voltage output circuit or a switching power supply circuit, into an integer by a frequency dividing circuit. The present invention relates to a vertical line curvature correction circuit for correcting the curvature of vertical lines on a screen in a raster scan type display device having a circuit operated by a signal obtained by dividing the frequency of the vertical line.

従来の技術 第4図はテレビジョン受像機、モニターテレビ。Conventional technology Figure 4 shows a television receiver and monitor television.

コンピューター用ディスプレイ等の一般的なラスタース
キャン方式の表示装置の要部の一例のブロック系統図を
示す。同図中、入力端子1に入来した水平同期パルスは
パルス整形回路2を通して水平AFC回路3に供給され
、ここで雑音による水平同期の乱れを除去するために、
入力水平同期パルスの所定の数の周期の平均の周期で取
り出された信号は水平発振回路4に供給され、その発振
周波数を可変制御する。これにより、水平発振回路4か
ら取り出された水平同期パルスの平均周期に同期した、
水平走査周波数r+のパルスは水平ドライブ回路5によ
り、増幅及び波形整形された後水平出力回路6に供給さ
れる。水平出力回路6により水平偏平コイル7に水平走
査周波数fHののこぎり波尾流が流される。また、水平
出力回路6の出力信号は、分周回路8により1/n (
ただし、nは2以上の整数)に分周されて周期n−H(
ただし、Hは水平走査周期)のパルスに変換された後、
高圧又は電源ドライブ回路9と高圧又は電源出力回路1
0を夫々経てスイッチングトランス11に供給される。
1 shows a block system diagram of an example of a main part of a general raster scan type display device such as a computer display. In the figure, the horizontal synchronization pulse that enters the input terminal 1 is supplied to the horizontal AFC circuit 3 through the pulse shaping circuit 2, and here, in order to remove disturbances in horizontal synchronization due to noise,
A signal taken out at the average period of a predetermined number of periods of the input horizontal synchronizing pulse is supplied to the horizontal oscillation circuit 4, and its oscillation frequency is variably controlled. As a result, synchronized with the average period of the horizontal synchronization pulse taken out from the horizontal oscillation circuit 4,
The pulses at the horizontal scanning frequency r+ are amplified and waveform-shaped by the horizontal drive circuit 5 and then supplied to the horizontal output circuit 6 . A sawtooth wave tail flow having a horizontal scanning frequency fH is caused to flow through the horizontal flattened coil 7 by the horizontal output circuit 6. Further, the output signal of the horizontal output circuit 6 is divided into 1/n (
However, the frequency is divided into periods n-H (where n is an integer greater than or equal to 2).
However, after being converted to a pulse with H = horizontal scanning period),
High voltage or power supply drive circuit 9 and high voltage or power supply output circuit 1
0 and then supplied to the switching transformer 11.

スイッチングトランス11と次段の整流・平滑回路12
とは上記周期0・Hの分周パルスを昇圧した後整流・平
滑し、これにより得た高圧又は直流電源電圧を出力端子
13へ出力する。
Switching transformer 11 and next stage rectifier/smoothing circuit 12
This means that the frequency-divided pulse with a period of 0·H is boosted, then rectified and smoothed, and the resulting high voltage or DC power supply voltage is output to the output terminal 13.

発明が解決しようとする問題点 このような高圧出力回路やスイッチング電源回路等の大
きなエネルギーで動作する回路を、水平発振回路4の出
力信号周波数fHの1/n倍の周波数の信号で駆動する
ラスタースキャン方式の表示装置においては、第4図に
破線の矢印で示す如く、高圧又は電源出力回路10.あ
るいはスイッチングトランス11からのノイズ成分が、
パルス整形回路2.水平AFC回路3又は水平発振回路
4に妨害を与えるため、水平発振回路4の出力パルスが
n個毎に位相がずれ、その結果画面の走査線がn木目毎
に左又は右にずれる現象を生じる。
Problems to be Solved by the Invention A raster system that drives circuits that operate with large energy, such as high-voltage output circuits and switching power supply circuits, with a signal having a frequency 1/n times the output signal frequency fH of the horizontal oscillation circuit 4. In a scan type display device, a high voltage or power output circuit 10. Or the noise component from the switching transformer 11,
Pulse shaping circuit 2. In order to interfere with the horizontal AFC circuit 3 or the horizontal oscillation circuit 4, the phase of the output pulses of the horizontal oscillation circuit 4 is shifted every n times, resulting in a phenomenon in which the scanning line on the screen shifts to the left or right every n grains. .

従って、例えば上記整数nの値が「2」の場合は水平発
振回路4の出力パルスは第2図(A)に示す如く、2日
毎にαだけ位相がずれ、画面上、例えば2本の縦線は第
5図に15及び16で示す如く、走査線1本毎に左、右
にずれた画像となってしまう。
Therefore, for example, if the value of the integer n is "2", the output pulse of the horizontal oscillation circuit 4 will shift in phase by α every two days, as shown in FIG. As shown by 15 and 16 in FIG. 5, the lines result in an image shifted to the left or right for each scanning line.

このような縦線曲がり現象を防止するには、厳重なシー
ルドを所要の回路に施したり、あるいは水平AFC回路
3の入力側や低圧電源ラインなどに低域フィルタを挿入
するなどの方法が必要となるが、これらの方法を採って
も、縦線曲がりを視覚的に検知できない程に補正するこ
とは困難であった。
In order to prevent this vertical line bending phenomenon, it is necessary to provide strict shielding to the required circuits, or insert a low-pass filter into the input side of the horizontal AFC circuit 3 or the low-voltage power supply line. However, even if these methods are adopted, it is difficult to correct the vertical line bending to such an extent that it cannot be visually detected.

そこで、本発明は水平発振回路の出力パルスを分周する
分周回路の出力信号の位相等を調整して水平発振回路の
出力端にフィードバックすることにより、上記の問題点
を解決した縦線曲がり補正回路を提供することを目的と
する。
Therefore, the present invention solves the above problem by adjusting the phase etc. of the output signal of a frequency dividing circuit that divides the output pulse of the horizontal oscillation circuit and feeding it back to the output terminal of the horizontal oscillation circuit. The purpose is to provide a correction circuit.

問題点を解決するための手段 本発明になる縦線曲がり補正回路は、ラスタースキャン
方式の表示装置において、分周回路より取り出された水
平発掘回路の出力信号周波数の整数分の−の分周信号を
、調整回路に供給し、ここで位相及びレベルのうち少な
くとも位相が調整される。この調整回路の出力信号は合
成手段により水平発振回路の出力信号に加算合成されて
、位相が一定の合成信号とされる。
Means for Solving the Problems The vertical line bending correction circuit according to the present invention uses a frequency-divided signal of an integer fraction of the output signal frequency of a horizontal excavation circuit extracted from a frequency dividing circuit in a raster scan type display device. is supplied to an adjustment circuit, where at least the phase of the phase and level is adjusted. The output signal of this adjustment circuit is added and combined with the output signal of the horizontal oscillation circuit by a combining means to form a composite signal having a constant phase.

作用 前記分周回路の分周比を110とすると、水平発振回路
4の出力信号(パルス)は、前記した如く n本の走査
線毎に位相が1Hからずれるために縦線曲がり現象が発
生するが、前記調整回路の出力信号と水平発掘回路の出
力信号とを前記合成手段で加算合成することにより、上
記のn本の走査線毎の位相のずれが補正され、分周回路
には常に一定の位相のH周期のパルスが供給されること
になる。以下、本発明回路について実施例と共に更に詳
細に説明する。
Effect When the frequency dividing ratio of the frequency dividing circuit is set to 110, the output signal (pulse) of the horizontal oscillation circuit 4 has a vertical line bending phenomenon because the phase deviates from 1H every n scanning lines as described above. However, by adding and synthesizing the output signal of the adjustment circuit and the output signal of the horizontal excavation circuit by the synthesis means, the above-mentioned phase shift for each n scanning line is corrected, and the frequency dividing circuit always has a constant value. A pulse with a phase of H period is supplied. Hereinafter, the circuit of the present invention will be explained in more detail along with examples.

実施例 第1図は本発明になる縦線曲がり補正回路の一実施例の
ブロック系統図を示す。同図中、第4図と同一構成部分
には同一符号を付し、その説明を省略する。第1図にお
いて、スイッチングトランス20は、例えばその−次側
に新たな巻線を付加された構成とされ、その新たに付加
された巻線からn−)1の周期のパルスをアッテネータ
21に供給する。アッテネータ21は入力パルスのレベ
ルを調整して位相調整器22に出力し、ここで位相調整
を行なわせる。アッテネータ21によるレベル調整と位
相調整器22による位相調整とは、例えばモニター表示
装置に縦線を表示させつつ、それが視覚的に本来の縦線
に見えるように、画面を監視しつつ人間によって行なわ
れる。
Embodiment FIG. 1 shows a block diagram of an embodiment of a vertical line bending correction circuit according to the present invention. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals, and the explanation thereof will be omitted. In FIG. 1, the switching transformer 20 has a configuration in which, for example, a new winding is added to its negative side, and a pulse with a period of n-)1 is supplied from the newly added winding to the attenuator 21. do. The attenuator 21 adjusts the level of the input pulse and outputs it to the phase adjuster 22, where phase adjustment is performed. The level adjustment by the attenuator 21 and the phase adjustment by the phase adjuster 22 are performed by a person while monitoring the screen so that, for example, a vertical line is displayed on a monitor display device so that it visually looks like the original vertical line. It will be done.

位相調整器22の出力パルスは加算点23において水平
発掘回路4の出力パルスと加算合成される。いま、分周
回路8の分周比を1/2とすると、前記した如く、水平
発振回路4の出力パルスは第2図(A)に示す如<28
毎に位相がαだけずれるが、位相調整回路22より取り
出された周期2Hの第2図(B)に示す如きパルスが加
偉点23において、同図(A)に示した水平発振パルス
と加算合成されるため、水平ドライブ回路5の入力端に
は、同図(C)に示す姐き、常に位相が一定の1H周期
のパルスが供給されることになる。
The output pulses of the phase adjuster 22 are summed together with the output pulses of the horizontal excavation circuit 4 at a summing point 23. Now, if the frequency division ratio of the frequency dividing circuit 8 is set to 1/2, the output pulse of the horizontal oscillation circuit 4 will be <28 as shown in FIG. 2(A), as described above.
Although the phase is shifted by α every time, the pulse as shown in FIG. 2(B) with a period of 2H extracted from the phase adjustment circuit 22 is added to the horizontal oscillation pulse shown in FIG. 2(A) at the loading point 23. Since the signals are combined, the input terminal of the horizontal drive circuit 5 is supplied with a 1H cycle pulse whose phase is always constant, as shown in FIG.

これにより、画面上、例えば2本の縦線は第3図に25
.26で夫々示す如く、視覚的に縦線曲がりが見えない
、本来の直線の縦線として表示される。
As a result, on the screen, for example, two vertical lines are 25 in Figure 3.
.. As shown at 26, the vertical lines are displayed as original straight vertical lines with no visible bends.

なお、本発明は上記の実施例に限定されるものではなく
、分周パルスの分岐手段としてはスイッチングトランス
20の構成を変更する場合に限らず、例えば高圧又は電
源出力回路1oの出力端とアース間に直列に2個のコン
デンサを接続し、2個のコンデンサの接続中点から取り
出すようにしてもよく、その他種々の方法が考えられる
。また、アッテネータ21と位相調整回路22により、
分周パルスのレベル及び位相を夫々調整しているが、少
なくとも位相を調整することにより、原理的には縦線曲
がりを補正することができる。
It should be noted that the present invention is not limited to the above-described embodiments, and the branching means for frequency-divided pulses is not limited to changing the configuration of the switching transformer 20. For example, the output terminal of the high voltage or power output circuit 1o and the ground Two capacitors may be connected in series between the capacitors and the capacitor may be taken out from the midpoint between the two capacitors, and various other methods may be considered. In addition, by the attenuator 21 and the phase adjustment circuit 22,
Although the level and phase of the frequency-divided pulse are adjusted, it is possible in principle to correct vertical line bending by adjusting at least the phase.

発明の効果 上述の如く、本発明によれば、水平ドライブ回路に常に
一定位相の1H周期のパルスを供給することができるの
で、縦線曲がりが視覚的に殆ど目立たない、本来の縦線
画像を表示させることができる等の特長を有するもので
ある。
Effects of the Invention As described above, according to the present invention, it is possible to always supply a 1H cycle pulse with a constant phase to the horizontal drive circuit, so that it is possible to produce an original vertical line image in which vertical line bending is hardly visually noticeable. It has features such as being able to display images.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明回路の一実施例を示すブロック系統図、
第2図は第1図図示ブロック系統の動作説明用信号波形
図、第3図は本発明回路によ−る画面上の縦線画像の要
部を拡大して示す図、第4図は一般的な表示装置の要部
の一例のブロック系統図、第5図は第4図図示装置によ
る画面上の縦線画像の要部を拡大して示す図である。 1・・・水平同期パルス入力端子、2・・・パルス整形
回路、3・・・水平AFC回路、4・・・水平発振回路
、5・・・水平ドライブ回路、7・・・水平偏向コイル
、8・・・分周回路、11.20・・・スイッチングト
ランス、15.16,25.26・・・縦線、21・・
・アッテネータ、22・・・位相調整回路、23・・・
加算点。
FIG. 1 is a block diagram showing an embodiment of the circuit of the present invention;
FIG. 2 is a signal waveform diagram for explaining the operation of the block system shown in FIG. FIG. 5 is a block diagram showing an example of a main part of a typical display device; FIG. 5 is an enlarged view showing a main part of a vertical line image on a screen by the device shown in FIG. DESCRIPTION OF SYMBOLS 1...Horizontal synchronization pulse input terminal, 2...Pulse shaping circuit, 3...Horizontal AFC circuit, 4...Horizontal oscillation circuit, 5...Horizontal drive circuit, 7...Horizontal deflection coil, 8... Frequency dividing circuit, 11.20... Switching transformer, 15.16, 25.26... Vertical line, 21...
・Attenuator, 22... Phase adjustment circuit, 23...
Additional points.

Claims (1)

【特許請求の範囲】[Claims] 水平発振回路の出力信号周波数を分周回路により整数分
の一に分周して得た信号により動作する回路を有するラ
スタースキャン方式の表示装置において、前記分周回路
の出力信号の位相及びレベルのうち少なくとも位相を調
整する調整回路と、該調整回路の出力信号を前記水平発
振回路の出力信号に加算合成して位相が一定の合成信号
を出力する合成手段とよりなることを特徴とする縦線曲
がり補正回路。
In a raster scan type display device having a circuit that operates using a signal obtained by dividing the output signal frequency of a horizontal oscillation circuit into an integer by a frequency dividing circuit, the phase and level of the output signal of the frequency dividing circuit may be changed. A vertical line comprising at least an adjustment circuit that adjusts the phase, and a synthesizing means that adds and synthesizes the output signal of the adjustment circuit with the output signal of the horizontal oscillation circuit to output a composite signal having a constant phase. Bending correction circuit.
JP25524284A 1984-12-03 1984-12-03 Vertical line warp correction circuit Pending JPS61133779A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25524284A JPS61133779A (en) 1984-12-03 1984-12-03 Vertical line warp correction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25524284A JPS61133779A (en) 1984-12-03 1984-12-03 Vertical line warp correction circuit

Publications (1)

Publication Number Publication Date
JPS61133779A true JPS61133779A (en) 1986-06-21

Family

ID=17276009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25524284A Pending JPS61133779A (en) 1984-12-03 1984-12-03 Vertical line warp correction circuit

Country Status (1)

Country Link
JP (1) JPS61133779A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130163054A1 (en) * 2011-12-26 2013-06-27 Canon Kabushiki Kaisha Method of detecting floating amount of original for image reading apparatus, method of image processing using the same, and image reading apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5269220A (en) * 1975-12-08 1977-06-08 Hitachi Ltd Correction circuit for picture bend
JPS55105477A (en) * 1979-02-06 1980-08-13 Matsushita Electric Ind Co Ltd Horizontal phase control circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5269220A (en) * 1975-12-08 1977-06-08 Hitachi Ltd Correction circuit for picture bend
JPS55105477A (en) * 1979-02-06 1980-08-13 Matsushita Electric Ind Co Ltd Horizontal phase control circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130163054A1 (en) * 2011-12-26 2013-06-27 Canon Kabushiki Kaisha Method of detecting floating amount of original for image reading apparatus, method of image processing using the same, and image reading apparatus
US8885220B2 (en) * 2011-12-26 2014-11-11 Canon Kabushiki Kaisha Method of detecting floating amount of original for image reading apparatus, method of image processing using the same, and image reading apparatus

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