JPS6113260B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD This invention relates to computer systems, and more particularly to improved digital computers in the area of database operations. Computers based on electronics have grown from first generation hardware mainly based on vacuum tubes, to second generation hardware based on transistors, and finally to third generation hardware mainly based on integrated circuits. Along with these different generations of hardware, there are also different generations of software, with the first generation primarily featuring machine language, assemblers, and subroutines, and the second generation featuring high-level languages, monitors, and macro assemblers. It was. Third
The generation of software features operating systems, online real-time systems, multiprogramming systems, and database management systems. The first generation hardware combined with the first generation software and the second generation hardware combined with the second generation software were primarily batch operations in which each job was executed primarily serially. . Furthermore, the hardware/software systems of the Third Generation were also intended for batch processing, but with the advent of multiprogramming, some jobs could be executed in parallel rather than serially as input information for processing occurred. It becomes possible to accept. Fourth generation systems are primarily classified as transmission and control systems capable of a wide variety of processor applications, and are primarily based on transmitted data (i.e. The control of the system is performed mainly by input rather than by operator operation). In the evolution of each generation of computer systems mentioned above, the greatest desire has been the development of an effective method for accessing the databases of computer systems. In the development of system databases, the first milestone was the development of multiple databases for each use. The increase in the number of such databases has resulted in excessive storage requirements and redundant data storage, which can result in redundant data being updated accurately in some areas and inaccurately in others at different points in time. This ended up making the problem worse. Some systems have addressed these problems by merging many databases into a single database. Honeywell's Central Data Storage System (IDS) was an example of a system designed to alleviate these problems. This centralized data storage consisted of one central database that could be used, for example, by inventory management systems, internal audit procedures, wage payment procedures, etc. to access relevant data therein. This centralized database contained a single record description common to the needs of several computing functions. For example, inventory management and internal audit processes will access numerical values in certain parts of the warehouse. Effective techniques for using centralized databases have changed due to continuous improvements in software technology. The ``set concept'' is a technique that allows records to be accessed in a centralized database based on the relationships between each record. A typical relationship is all employees within a particular department, such as a manufacturing department.
This manufacturing department is described by what is called an "owner record," and the employees in the department are described by a "member record."
It is described by what is called. A set that describes a relationship, such as members of a department, can then be accessed by an owner record, which allows the software to retrieve all member records, e.g., type out the names of all employees in that department. let At this stage of development, centralized data storage is limited to those with the pure data problems mentioned above;
That is, the problem of redundant data in different databases and updating of many records copies was solved. This problem is solved by a single record, which therefore makes it possible to reduce the size of the data storage device,
Make a single copy of data. Other issues with using databases remain in the area of computational performance efficiency. This set concept provided a new use for computers, but since then no dedicated hardware instructions existed in modern central processing units to support this new technique. As a result, set operations, such as finding the first member of a set, are organized in software by a series of standard machine instructions such as add, load, store, etc. As a result, the first
Member discovery requires a long execution time for relatively simple set operations such as inserting records into a set and other set operations. What is needed is a database system that solves traditional data problems, such as those already solved with centralized data techniques using set arithmetic, and that is also effective in execution time and other system efficiency parameters. To accomplish this, dedicated hardware/firmware maintained instructions were required to perform auxiliary operations in the set operations. For example, a single instruction that finds a database pointer for a record can execute in significantly less time than a series of 5 to 10 standard hardware instructions required to perform the same operation on a traditional computer. It becomes possible. A primary object of the present invention is to provide an improved general purpose digital computer. Another object of the invention is to provide an improved general purpose digital computer having improved performance for database management operations. Yet another object of the present invention is to provide hardware/firmware instructions for converting a database pointer into a corresponding segmented address and then loading said segmented address into a data register. Yet another object of the invention is to reduce the number of instructions in user programs and operating system programs. Each of the above objectives requires a set of hardware/firmware that retrieves a database pointer from memory, converts this pointer into a segmented address according to its pointer class, and loads this segmented address into a base register. This is achieved by one embodiment of the present invention that provides one of the instructions organized in . If the pointer is part of a database type record, this pointer is also loaded into the index register. The operating environment of the device according to the invention comprises a memory (102 in FIG. 1) consisting of a plurality of segments of addressable space, each segment being identified by a segment number (SEG). Stores a set of one or more records (Figure 15), each set having one owner record and one or more member records, each record having its segment number and the number of records within that segment. Each record in each of the plurality of sets is located within the memory by offset address information (SRA) for locating the record relative to a predetermined storage location. one or more database pointers (point 1 of FIG.
513), wherein each pointer represents a storage location of said point record thereby identified relative to a predetermined record of said set. be. Its purpose is to directly locate a database record using a pointer pointing to the record, which is used in the environment described above.
An apparatus for implementing an XI instruction, the apparatus comprising: (a) extracting information from one record of one of the plurality of sets of database pointers according to the address syllable of the instruction (1922 in FIG. 19b); (FIGS. 15g, 15h) and transfers said pointer to a first temporary register conveniently referred to as "X" in scratch pad storage.
(2005 in Figure 0a); (b) defines the actual structure of a section of said memory holding the desired one of said set, and defines the number of the segment in which said section resides (number 16);
To obtain the page descriptor (Fig. 16b) from the storage location, including the page descriptor (1625 in Fig. b)
a second means (FIG. 17, FIG. 20a) responsive to a "region-page" field (1572, 1573 in FIG. 15h) of the contents of said database pointer in said first temporary register;
07); and (c) from the array table (1602 in Figure 16a) of the row offset elements in said set, determine the relative position or offset within each set of said point records with respect to a predetermined storage location within said set. 1603) in Figure 16a, the first
Another "row" field (first row) of the contents of said database pointer in a temporary register of
5h (1574 in FIG. 16b); and (d) responding to said segment number (1625 in FIG. ) and the relative position or offset of said point record (16 in Figure 16a).
03) into the second temporary register BR (202 in FIG. 20c).
4); and operative to automatically convert the pointer identification information of the identified record into a segmented address indicative of its storage location in memory. 1 Explanation A Scope and Structure of the Disclosure The means used for direct discovery database commands on large scale computers are necessarily complex. Moreover, a thorough understanding of the teachings of the present invention can be obtained by having some knowledge of the field to which such means pertain. Therefore, it would be desirable to have a simplified solution to the general structure of a typical large scale data processing system of the type in which the principles of the present invention may be effectively employed. It is also desirable to first establish and understand the basic concept on which the present invention is based. This database set concept unifies several techniques (tables, lists, chains, rings, files, and field arrays) that have been commonly used throughout much of the history of computer programming in particular. (This concept is a specification of the more general mathematical set concept from which "data structure set" derives many of its names and properties. In this disclosure, the word "set" is always used in data structures. (This is not meant in a mathematical sense.) Many systems have the set concept described above only in software. In the database management area, Honeywell's Intensive Data Storage System (IDS) first pioneered the widespread use of this set of concepts for handling complex manufacturing operations and banking problems. IDS uses a chain (ring) form of set implementation. These basic concepts have been decomposed into hardware/firmware and incorporated into existing computers to provide progressively improved digital computers. A set is one of three complementary concepts (records, fields, and sets) necessary to form and store data structures that closely approximate objects in the natural world. If the natural world is considered in terms of real entities, there are properties that describe these entities and relationships that relate these entities, and the information system concepts equivalent to these are records and fields, respectively. , and set. In the simple case of a school, these entities would be a teacher and a child. Some of the characteristics of teachers are "name", "grade" and "classroom".
It is. Some of the child's characteristics are "name,""age," and "names of parents." A certain relationship exists between teachers and children. In this model of a natural world state information system, two classes of records are formed, one for teachers and the other for children. There are certain fields in each teacher's record, one to store the teacher's name, another to store the grade, and another to store the class room number. Each child's record has a file with the child's name, a file with his age, and a file with the names of his parents. The information system can link each child's record to this teacher's record in one of several ways selected to formulate the set concept. This would be done by physically placing all children's records after their teacher's record array in the file. This is called a table or record array. This embodiment includes a set concept chain (ring) knitting technique. In this form, the owner record contains a pointer to the first member record. Each member record further includes pointers to subsequent member records. The last member record in this set again contains a pointer to the owner record. It is also possible to modify the owner record or the owner record and all member records to provide an additional pointer field that holds the address of the previous record and possibly a pointer to the owner record for the member records. The data structure set concept as described above is an improvement over the mathematical set concept, i.e., in a data structure set, the definition of this set is
Implemented in case of roll. Membership in a set is enforced in the case of the ``member'' role. Each record currently has many roles such as owner and member of different sets. This property allows the creation and manipulation of complex data structures that model the complexity of the real world. In improving this mathematical set concept, the definition of a set can be reorganized from the owner as a definition to each member and from any member to the owner. For data structure sets, the set definition is usually based on the value of some field in the owner record, and the membership of the set is reorganized in the computer by the matched values of the peer fields in the possible member records. The advantage of this event is often exploited by removing this field from member records that hold matching data and relying on the owner record for repopulation. In the school example above, the teacher was assumed to have the role of "owner" of the teacher/child set. To extend this example, set it as follows. That is, in most schools, the relationship between teachers and children is not a simple relationship (1:n), but a complex relationship (m:n) in which children have different teachers for different subjects. shall be. This complex teacher-child relationship is transformed into a new interpersonal entity, the "student," and two simple relationships, "teacher-student" and "child-student." A teacher has many children as students in his class, and children as students have many teachers. This new "student" entity has attributes of "subject" and "time limit" for distinguishing one student from the other. A child may have the same teacher for several subjects. This data structure set concept has four basic characteristics. (1) A set is unique and always has one record in the owner role. (2) A set may have zero, one, or more records in the member roll, and the number may vary over time. (3) Any record can be the owner of zero, one, or more sets at the same time. (4) Any record can be a member in zero, one, or more sets at the same time, and thus can be owned by several owner records at the same time. Each record is created only once as a member of a particular set. Member role does not interfere with owner role. The terms "next" and "previous" are important concepts for the procedural algorithms underlying the solution of problems in storage program computers. In addition to the procedural constraints of handling one record at a time, if the member records in the set are arranged in a predetermined data numeric sequence or in a temporal insertion order sequence (FIFO: first in, first out, or LIFO: last in, first out). An even more important simplification results for some algorithms if it can be transmitted in . "first" and "last"
This description is important for starting and stopping the iterative execution of the algorithm on the data. Like this,
The order of the members in a set is a prerequisite for the rational operations of that set. The first factor in the manipulation of each set of records within a file is the modeling of real-world relationships and the ability to facilitate the recall of selected records within a file that represent certain relationships. be. These are listed in Table 1.

[Table] Access methods Searching each record in the file The first four access methods are mainly used in fluctuation processing and adjustment processing; in this case,
There is a need to accommodate determining or updating the record status of a particular entity and associated group of entities. The file sequence access method is primarily used for periodic file updates and report generation. The same record can be accessed by all five methods if necessary. Similarly, these access methods can be used in combination to achieve specific effects. Using the above example, a teacher's records can be retrieved using the "data key access method" and therefore the records of all of that teacher's students can be retrieved using the "set member access method". For each student's records,
Children's records can be searched using the ``Set Owner Access Method.'' Alternatively, the search could start with "Data Key Access" for the child's records, then retrieve all the child's student records, then retrieve the teacher's records. The basic search opportunities resulting from this set are shown in Table 2 below.

[Table] Each member Set owner Set owner
There is a set of basic operations that apply to each set.
These are even better known records and files.
This is a supplement to the basic operations related to the code. Each section
Collection of basic calculation results related to
Supplementary basic calculations for yield are provided by the user.
Access, modify, and move data to perform operations
Hardware/firmware that performs
It is known as the operational facility where air commands are collected.
constitute what is to be expected. Basics (i.e., hard
This set of hardware/firmware instructions) is
Fields (i.e. data items), records, sets
and various operations related to procedural logic control.
You can divide it. The following hardware/firmware instructions
is used to manipulate data in a field.
Ru. Field description information required for the operation to be performed
(e.g. size, location, recording mode)
as part of the data descriptor associated with the operation.
is retained. Operations included in this group and
For example, move, compare, hash, add
These include calculation, subtraction, multiplication, and division. The following hardware/firmware instructions
Direct and serial access processing of data
Do both. These include the occurrence of data recording,
Search, qualify, test, and destroy after.
Recording firmware/hardware instructions are
Generation of records, destruction of records, discovery of direct records, serial records
is a discovery and recording type test. The following sets of hardware/firmware
A group of instructions includes traditional data processing and previous data processing.
database and message management system
Provides built-in blocks. These are set
occurrence, its access, and its operation and testing.
do the following. This hardware/firmware
Commands include inserting records, retrieving records, and relative records.
Discover record (first, last, next, previous, and i number)
(discovery of eyes), discovery of owner records, discovery of empty sets.
test, test inserted member, owner
This is the start of recording and the start of member recording. Base register hardware/firmware
The following group of instructions perform database access.
Determining the current process state for the process and
Give qualification. This hardware instruction is a
unload base register, base register and
The aforementioned "discovery" instruction that loads the base register
This is the nullification of . Records in the application database
is used to configure and do this.
Similarly, each set also supports a wide variety of systems.
It can be used in the software area of The table below lists the software for your system.
A list of air regions, each of which has a set
Lists certain uses of the concept in the above areas.
It is. This table indicates a clear use and is complete.
This is not a guarantee. 1 Database system a Index configuration (sequence index
and random index) b Data description structure c Shared access control list d Process response structure 2 File system a Catalog structure b Access right control 3 Message system a Mailbox index structure b Queue message c Multi-element message recall 4 Programming system a Program library management b Text editing c Program control structure d Symbol references and symbols for binding
Intermediate program format for compilation 5 Operating system a Job queue b Resource allocation table c Deadlock detection d Event process wait queue (I/O completion
e Dispatching Queue 1 General Theory The present invention
The hardware system described below is associated with
act in the system environment (Environment).
Is Umono. In Figure 1, subsystems and
is a processor subsystem 101, a storage subsystem
system 102 and one or more (up to 32)
This is the side device subsystem 103. processor sub
The system has one central processing unit (CPU) 104
and up to four input/output controllers (IOCs) 105.
I'm reading. Each peripheral subsystem has one peripheral
Side device control unit (PCU) 106 and numerous devices
adapter (DA) 107 and up to 256 peripheral devices.
Includes input/output equipment 108. storage subsystem
102 is 1 to 4 of 32 to 512 kilobytes each
It consists of several semiconductor memory modules. In the processor subsystem 101,
The CPU 104 performs basic processing operations for the system.
Yes, it also interfaces with memory 102.
Ru. The IOC 105 is connected to the storage subsystem 102.
Controls all information exchange between peripheral devices 106. A Central Processing Unit (CPU) The central processing unit (CPU) is the main memory sink.
lonizer 109, buffer storage device 110,
Various elements consisting of calculation unit 111 and options
yon emulation equipment 112. main
The memory synchronizer 109 is a calculation unit.
111, buffer storage device 110, and IOC 109.
resolve main memory usage conflicts between child
Conflicts are resolved in priority order as follows: Immediately
In other words, the IOC is a memory write (from the calculation unit)
followed by memory (to buffer storage)
– has the highest priority followed by reads. main
The CPU also has an address that controls main memory designation.
Control unit ACU131 and the end of main memory
The associative memory used to remember addresses used in
Contains Mori AS132. Batsuhua memory device
The storage 110 is a small high-speed buffer memory.
to reclaim the selected area of main memory and
Computation unit to reduce average memory access time
interface with. each memory read
During this time, both buffer storage and main memory are active.
be accessed. The information to be retrieved is already in a buffer memory.
If it is in the device, the main memory read ends and the information is
The information is retrieved from buffer storage. Otherwise
If so, main memory 102 is read. This is done
Each time the CPU 104 receives 32
Take out the light. This information is used for future memory queries.
remains in buffer storage. This batshua
The storage device is transparent to software.
(transparentto) the program that controls the computer.
The information that the computer processes is overwhelming.
retrieved from firmware storage or from main memory.
It is not possible to determine whether The calculation unit 111 stores all data within the CPU.
Processing and address formation. Inside calculation unit
A typical control storage device 130 (Prentice Hotel)
“MicroProg” written by Sameer S. Hatsen published by Rusha
ramming, its principles and applications) is a system
starts, controls CPU104 and IOC105, and
Contains firmware that decodes two sets of instructions.
Control storage can optionally contain scientific commands, test routines
Emulation package
or the capabilities of the processor subsystem.
It has extended special purpose properties. Optionally, the CPU is installed on a system other than this system.
emulation. Emulator 112
is firmware, software, and
In some cases, it is a hardware component. B Input/output control unit The IOC105 part of the processor subsystem is completely
Peripheral subsystem 103 and storage subsystem
Provides a data path between systems 102. this
The route allows the initiation of peripheral commands and results.
Control the data transmission obtained as follows. one
IOC is generally a control unit with up to 32 channels (Fig.
(not shown) can be handled. C Peripheral Device Subsystem In the peripheral device subsystem 103 of FIG.
, PCU106 is an independent microprogramming
input/output device 1 during input/output operations.
Loading of CPU104 by controlling 08
unlock. This PCU is a channel program
The above operations are performed by executing each instruction included in the RAM.
cormorant. This program uses arithmetic, logical transfers and digits
This causes a shift and branch operations are performed on the PCU.
It will be done. There are several types of PCUs, and
Depending on the type of vessel, unit records and mass (disc)
h) Storage devices, magnetic tapes, communication systems
control etc. The device adapter 107 controls each PCU.
Intervening between devices. Each of them is a specific type of machine.
Determined farm required to communicate with the device
Includes clothing and logic. DA107 is that
Control one or several devices depending on the type of
Ru. Implemented by peripheral subsystem 103
The main functions are as follows. 1. Serial translation of CPU instructions to peripherals 2. Required by the CPU or appropriate peripherals.
Packing and unpacking data into a form 3. Subsystems to the CPU and their control
Maintaining status reports with each piece of equipment 4 Independently opening error and recovery procedures
Initialization and processing 5 Set the equipment sharing capabilities of the related peripheral device processors.
Unobstructed online diagnostics of devices
Allowance for main memory between each device attached to the PCU
The IOC resolves conflicts between PCUs.
resolve the problem. D Storage Subsystem Each memory module 1 to 4 is 4 or 8 bytes.
It is the width of the number of modules, size, and
The width of the data path depends on the size of the computer.
Change. The memory module has four modules.
Quadruple interleaving so that the files are accessed sequentially.
(module 1 is the first 8 bytes)
and module 2 contains the second 8 bytes.
). This interleaving procedure
This reduces the number of contentions for Molly's access.
Reduces average memory access time. memo
Lee can be reconfigured in the event of a failure. That is, one modi
Each block of memory within a block is connected to an adjacent address.
It can be removed without destroying the response specification. The main memory 102 is a metal oxide film semiconductor MOS
It consists of a capacitive storage medium in the form of a chip. this
Refresh media to maintain information
It works on the (refresh) principle. The location of each memory
The system refreshes at least once every 2 milliseconds.
This design reduces the refresh timing.
Guarantees less contention between memory calls and
do. (If a conflict occurs, the refresh operation is
The first area of main memory is for hardware and
Reserved for firmware. Upper limit of this area
is the boundary address visible to the system's software.
response register (BAR, which is described below).
(described below). this
The contents of BAR are set at system startup.
Ru. Memory below the address specified in BAR
- area can contain an IOC table, which is a peripheral sub-area.
Firmware that controls the system and CPU, and
is a microprogram for emulation.
and the structure of the table. stipulated within this BAR
The size of the area below the specified address is the system configuration.
Depends on. Microprogram in main memory
Whether it is in control storage or not depends on the system configuration and
and application execution on the system.
Exists. 2 Basic computer structure Generally, what is used for this hardware
There are three basic data structures. That is, data
Tough format (format), visible from software
registers and instruction format. A. Data format Information is divided into 8 parallel bits between memory and CPU.
transferred in numbers. Each 8-bit unit of information is
It is called ito. Parity or error correction data
is also transferred with the data, but the software
It cannot be influenced more. Therefore, this light
In the specifications, data is defined by the associated parity i.e.
Exclude error correction data. B Bytes Each bit in one byte is from 0 to 7 from left to right.
Numbered. Each byte individually or in groups
Processed in a loop. Two bytes make up a half word,
4 bytes = 1 word, 8 bytes = 2 words, 16 bits
form 4 words. These include instructions
This is the basic format for all data. C. Presentation of data All data is in binary form;
Alternatively, it can be translated into alphanumeric codes. data bits
The numbers are binary encoded decimal data in groups of four.
data, alphanumeric codes for groups of 8, or 16
Up to 64 digits are translated as binary digits.
Ru. The latter is a number with a binary symbol, a fixed point number
Translated as a number or floating point number. 2 words
Any consecutive bits up to the point can also be manipulated as a string.
can. The alphanumeric set is EBCDIC (code).
expressed. ASCII can be used as an alternative code
Ru. D Byte Address The byte location in main memory is zero.
Begin with a sequential number, where each number is the address of a byte.
Ru. Consecutive byte groups are
The address of one byte is 2, 4, 8 or
If it is a multiple of 16, half word, 1 word, 2 words
They are said to be arranged into codes or 4 words. half wa
say one word, two words, or four words
Whenever the unit is aligned in
It can be retrieved from the reply. Main memory data
location is indirectly called during address formation.
specified by the issued data descriptor.
Ru. (February 10, 1972, assigned to the same person as the main application)
Japanese patent's "segmented address formation"
(See U.S. Pat. No. 3,938,096 with a name similar to E.
There is a register that can be used, and its contents reflect the state of the CPU.
comprehensively defined. They come in four forms.
Ru. (See Figure 2) That is, 1 General-purpose register 2 Base register 3 Scientific data register (optional) 4 Various registers F General-purpose register The general-purpose register (GR) 201 in Figure 2 is a fixed small
Used for manipulating numbers and bit strings.
Ru. CPU104 has 16 32-bit general-purpose
There are registers GR0 to GR15. General purpose cash register
The registers GR8 to GR15 are also index registers.
It can also be used as used as an index
When used, they are referred to as X0 to X7 in the main text, and
Decking has 32 bits and is contained in one register.
is implemented using two's complement integers. G Base Register The base register (BR) is the instruction counter IC and
Same format as task registers 202-203
It has The base register is used during address calculation.
Defines the portion of memory that is used. generally 8
There are two 32-bit base registers BR0 to BR7.
Ru. H Scientific data register The scientific data register (SR) is a floating point 2
Optional device for calculations in base numbers.
There are four 8-byte scientific calculation registers,
are called SR0 to SR3. Scientific register is
It has the formats 204 to 205 shown in FIG. I Various registers There are five other types of registers. That is, - an instruction file having formats 202 to 203;
Status register stack register (referred to as T register) with counter format 207 Boundary address register with format 206
hardware system with register and format 208
Control mask register The instruction counter IC is executed using a 32-bit register.
Contains the address of the instruction to be executed. status register
(STR) 207 is an 8-bit register that is currently in use.
Facts about the procedure being carried out, e.g.
– notes whether the flow was caused by the last operation.
Record. The stack register can also be used as a T register.
Also known and currently operating procedures and related push-shots
Contains a pointer to the beginning of the downstack.
nothing. The stack described below consists of a workspace,
and preservation of local variables and protection of procedure entries
and return information. boundary
Address register (BAR) 206 is a 28-bit
Register, accessible by software
Specifies the lowest absolute main memory address.
This register is loaded during system startup and
It can only be read by software. C
Hardware control mask register 208 is 8 bits
Record computer condition information in the register. J Instruction Format Approximately 200 instructions are used at any given time.
Each instruction has one of four different lengths,
Always an even number of bytes long. Each instruction is
is stored in a storage device location. left end
The address of the byte is a multiple of 2, and the address of the byte of this instruction is
It's a dress. The eight most significant bits of an instruction (and
bits 8 to 11 or 12 to 15)
represents the operation code, and the remaining bits are one or more
represents the operand (operational number) of one opera
A command is a register designator, a displacement designator, or an address.
address syllable (logical address), literal
It can be a value, an immediate literal value. Type of operand
and the numerical value are determined by the format of the instruction. 3 System Structure A Job Steps and Tasks The work to be performed by the computer system.
The job is executed through a series of job steps via the job control language.
Defined externally by the The job step is
A unit of work to which hardware resources are allocated
It is. Generally, one job step consists of several steps.
Consists of school. One task can be executed without being parallelized.
A user specification consisting of a series of commands to be executed.
It is the smallest unit of work. B User-side concepts of process tasks and job steps
are defined by one process and a group of processes, respectively.
Shown in hardware. 1 process is
The order in which instructions can be executed asynchronously by the CPU
(i.e. some process
can operate and divide resources, but in reality
Only one process is running at the moment.
). A process group has one job step.
A related set of processes required to perform
Ru. C. Process Control Blocks and System Bases Each process is CPU-controlled at many points during its execution.
Since the control can be stopped, there is a memory in main memory.
The domain is used by processes to store the state of the CPU.
will be available for use. This state information is
the CPU before the process is under CPU control again.
Used for preconditioning. The storage area allocated to a certain process is
In the figure, the process control block (PCB) 400
It is called. The data contained in one PCB is
Address of memory area allocated to the process
(address space) and all associated registries.
contains the contents of the data and the state of the process. this
, PCB is a process without any information loss.
information required to start or restart the device.
Acts as a temporary storage area. Each PCB is
visible to the software and formed during system startup.
A set of hardware that is qualified during system operation.
Operating system according to the table (Figure 5)
You can specify the address by called system-based (Figures 5 and 6)
There is an absolute main memory area. This area is
It is formed by hardware and can be read but not written.
Base address register (BAR) 5
It is accessible via 01. this system
The base 502 has a number of system attributes, which
etc., respectively for the currently running process.
Job step number and process group number (J.
P) is included. This system-based distinction
The attributes of the hardware specification known as J-Table 503
A pointer to a fixed data structure. this table
contains each current job step in the system.
Each entry in J table 503 points to the associated P table 504
However, this is also a hardware-defined data structure.
Ru. This table defines a process group and
Also, for each process in that process group.
Contains entries to. Each P table entry is PCB40
Indicates 0. In FIG. 5, calculation unit 111 (first
According to the J number value via the arithmetic operation unit 506 in the figure)
The indexed J table pointer 505 is
Entry 503 is accessed. this entry
contains the P table pointer, which is the calculation unit 50
When indexed by P number value via 6
The entry 504 of the P table is accessed. This P
The table entry is for the PCB of the currently running process.
It includes a pointer 507. In this way, the operator
The ing system uses the contents of BAR501.
You can access the active PCB and its associated (J.
P) Any other PCB that gives a logic name
can be accessed. D Memory segmentation Under multi-process conditions as described below
There are many processes in memory at any given time.
There is a These processes vary in size,
Memory requests that cause memory allocation problems
do. Operating system in this text
Hardware designed to work with the system (not shown)
The software dynamically allocates memory space.
This problem is solved by Responsible for memory requests
Due to intentionality, memory is divided into segments of various sizes.
This memory allocation is
Can be reconfigured during runtime. In this way, one program
Processes are allocated to many non-contiguous memory segments
Injury is possible. This memory allocation method is
called integration. Segmentation is the process by which memory addresses
When part or all of a process is relocated
raises another issue that always has to be qualified
do. In order to solve this problem, the system described in the main text is
The address used by a process is the absolute master.
A method that is more logical than memory addresses
I will provide a. These logical addresses are absolute addresses.
It is used to form a gas. Also, segmentation is a set of segments
Each process's own or
Each process accesses the associated address segment.
access. A segment descriptor
access, a process can access a certain segment.
You can get the address of the client. segment day
The scripter is contained in main memory and is
maintenance system. Each process has up to 2068 memory segments.
Can be accessed. Usually for this per process
The same number of segment descriptors are required.
Ru. However, since segments can be shared, operators
The coding system uses segment descriptors.
Classify into segment table. This classification consists of one process.
1 process group (job task), 1 process group (job step)
access) or as a whole (system-wide).
based on ability. Each process is associated with this 15
segment table. This method
accessible by the process through the component table
Only one segment date for each segment
It is long enough to require a scripter. In this way,
memory space required for the segment descriptor.
memory updates during relocations are reduced
protection for certain programs. (Prog
The main mechanism for ram protection is the ring system.
Ru. “Multi-program” patented on October 28, 1975
in multiprocessor computer systems.
U.S. Patent No. 3,916,385 titled “Protection of Information”
Reference) The process has access to the segments it can access.
It must be possible to determine. Therefore,
The system creates two segment table words for the process.
Give an array (STWA). These arrays are professional
Address of all segment tables accessible by
Contains responses. Two segment sizes, large and small
Since there are two segment tables for each process,
I have a word array. Large segments have maximum size
2 ^{twenty two} bytes and small segments have maximum support.
IS2 ¹⁶ Have a part-time job. All segments are
That size in increments of 16 bytes up to a large size.
changes. A system typically consists of 28 large
Can store up to 204 small segments.
Ru. The segment table word array is
can be repositioned by the stem, so the process
You must know the absolute address of the STWA associated with
No. The PCB of any process contains two words.
These are the address space words in Figure 4.
Contains this information known as ASW0-1.
Ru. Each word is a word array of one segment table
Instruct STWA. operating system
is executed whenever the associated STWA is relocated.
Update the contents of ASW. chain of pointers
Downward movement and segment descriptor
Decoding is a function of firmware and thus
Once started, the operating system
But I can't see it. Segmentation is available to the process
200 million bytes or more of address space.
Ru. This number exceeds the main memory capacity and therefore
The secondary storage device (magnetic disk or drum) is
Used in connection with Molly. This operation
system is what it is actually available for.
The illusion of having a much larger main memory
give. This concept is called virtual memory. At any point in time, the defined segment is
I don't know whether it is physically in main memory or not.
The contents of the segment descriptor are
Indicates whether the item is in main memory. Her
The software accesses segments that are not in main memory.
detects any attempt by a process to access
and notify the operating system. Operation
The rating system uses the desired segment as a secondary
from the storage device to the main memory. Next
So, the operating system is
is the only place where the absolute address of the client can be found.
Segment memory in segment descriptor
-Stores the address. This operation is performed from the process
This is why the segment is not in main memory.
or need to be relocated to main memory.
I don't know what that might be. (memory segment
For details regarding the station, please refer to
“Segmented address form” patented on April 10th
(See U.S. Pat.
By preventing processes from interfering with each other,
or mutual address space in an unlicensed manner.
(unauthorizedmanner)
data and procedures. This protection
– Addressability via segmentation
It is also possible to implement the ring system by limiting
administered. A segment table is used for each process in the system.
Separate the space. Each process always computes
Using segmented addresses while running
Ru. A segmented address is a segmented address.
Consists of a number and a relative address within the segment
(Before on generating segmented addresses
(see patents mentioned above). The hardware used for the process
The address used is the address assigned to the process.
Check if it is part of the response space. too
Shiko's address is in the scheduled address space
If it is outside, an exception operation occurs. process
data in another process's address space
The reason is that the hardware cannot be referenced.
using the segment table of the referencing process.
It is for the sake of being there. In this way, one process or
A process group references entities belonging to another process group.
There is no possibility of illumination. In general, in the address space within the system
overlaps are shared by all processes.
occurs for these segments that are this
Shared segments such as
Established by a system program that confirms the warranty of
be done. In this way, segmentation
mutually protect users' programs and protect users' programs from each other.
Protecting the operating system against RAM
Ru. Segments shared by several processes
from misuse by one of these programs.
Not protected. To solve this problem, a ring system
system is utilized, which allows procedures and data
Segments are classified into a four-class system. this
The four ring classes are numbered from 0 to 3.
There is. Each ring indicates a system priority and
Bell 0 (innermost ring) has the highest priority.
Bell 3 (outermost ring) indicates the last position.
vinegar. Each procedure in the system is
The minimum or maximum amount assigned to the procedure, indicating whether
It has a large execution ring number. One procedure is a sub
A routine can call other procedures and
Multiple parameters can be sent. That is, the general law of this ring system is as follows.
It's easy. 1 A procedure in one inner ring is a procedure in the outer ring.
access data freely. Conversely, the outer ring
procedure cannot access data in the inner ring.
stomach. 2 Outer ring procedures overlap inner ring procedures.
You can do this, but you cannot do the opposite. 3 Segments containing data are divided into two ring numbers.
assigned to the signal value, one of which is read (RD)
The other one is write (WR). These resources
The processing symbol value is determined by the procedure, whether it is a read or a write.
When accessing data in this mode,
Specify the maximum ring number value that can be used. Each time a procedural instruction is executed, the procedure is restarted.
The addressing number value (effective addressing ring, BAR) is
assigned to the segment containing the referenced data.
is checked against the ring number value. This EAR
is the process ring number value in the instruction counter
is the maximum value of
Emitted base register and data descriptor
are all ring number values in . this data
access is based on comparison of ring number values.
You will be rejected or rejected. For example, if
A system table has a maximum read ring value of 3 and a maximum
those in segments with write ring value 1
Then, the user procedure executed in ring 3 is
reads the table but does not update it. Rings 0 and 1 are operated by pre-configuration.
Reserved for the ring system, ring 2 and
3 is reserved for users. Ring 0 is
Contains segments critical to overall system operations. Rin
Group 1 includes a collection of each segment of the system.
However, the failure is not definitive and is recoverable.
Ru. Users can link against verified programs.
For the program to be debugged using
uses ring 3. F Procedure calls Procedure calls are made in the system described in the main text.
This is an important function. Calling a procedure is one way
from one procedure to another, and the operations performed by the user procedure.
operating system work tolerance and
To achieve modular structure within the tying system
used for. Procedure calls are carried out by each order.
The components recognized by the hardware are
Call the task (Figure 7A). A stack receives LIFO data retrieval.
It is a mechanism for entering, storing, and allowing. Each star
Tsuku is a special segment called stack segment.
Exist in ment. One stack segment is
Stack frame 7 dynamically allocated to each procedure
A number of neighbors called 01 (Figures 7A and 7B)
Consists of touching parts. The first stack frame is
The frame loaded at the top of the segment and following this
The system will be loaded after this part. last row
The loaded frame is considered the top of the stack.
Ru. T-register 702A indicates the currently operating program.
Find the top of the stack for Seth. actual T
The register is used by all other processes in the system.
Present on PCB. Stack frame 701 in Figure 7B has three regions.
Consists of areas. That is, a work area 70 for recording variables.
2, and a storage area 703 for storing register contents.
and a communication area 704 for sending parameters between each procedure.
be. Prior to the procedure call, the user
Specify these registers and add them to the called procedure.
The parameters to be sent must be loaded into the communication area.
Must be. When the call is made, this hardware
Air stores and recalls the contents of the instruction counter IC
base register to facilitate returns from procedures.
Specify the star. Each procedure call is placed in stack segment 701.
Establishes a stack frame for subsequent nested calls.
Open a separate frame for display. these calls
Each exit from one of the procedures
is removed from the stack. In this way, calling
A history of
make it easier. Ensure protection between procedures executed in different rings.
Different stack segments are used to maintain
Ru. One protection ring for each process.
There is a stack segment. One PCB has three
Contains stack base words, these are process
The star for each ring 0, 1 and 2 associated with
Instructs the start of a block segment. ring 3
The tack segment is never determined by the inner call.
Therefore, its stack startup access
No dress is required on the PCB. 4 Process management and synchronized operation The system described in this article consists of software, hardware
Operators using a combination of hardware and firmware
multi-pro
It is used to perform sensing calculations. The software is
Creates and deletes each process in the system.
On the other hand, hardware and firmware
Performs a multiplexer for each process on the CPU
cormorant. In addition, software, hardware and
Armware combination is synchronized operation between each process
I do. Usually, but not always, the process involves
During job handling and operating system
other opportunities for such purposes as may be deemed necessary by the
start and stop at the beginning and end of input/output operations.
I am made to do so. Therefore, enabling related processes
Communicate to start and stop and send information during
A system is needed. Hardware in main text
The system uses internal messages called semaphore.
provide communication links between each process. A Process states A process can be in four states at any time: running, ready.
It can be either standby, standby, or suspended. Her
software recognizes the status of these four processes.
to dispatch and change the state of the process.
maintains data structures based on the state of a process
Perform various firmware procedures to
Ru. The PCB displays the current state of its associated processes.
Contains fields with the specified state. A process runs when this is done under control of the CPU.
is in a state of This condition occurs when an address space
(segment table) and start address to the CPU.
Including supply. The CPU then executes the process's procedural segment.
Execute instructions in the ment. Currently running program
PCB process name J table worksheet for process
The system base (logical address)
(Figure) is held in the execution process word (BAR + 60)
be done. (Note: The system base shown in Figure 5 is
Same as shown in Figure 6, but details are omitted.
). Ready state is when a process is recognized by the CPU.
Except that it does not control the CPU because it was not
Equivalent to running state. A ready process is
The relationship between each process in the ready position and the execution process is
There is a race condition for the CPU. The process of sending messages via semahuao
A standby status that cannot continue until a special event such as
in a state of Waiting processes have contention for the CPU.
is not in the current state, but other standby states are available for the required event.
It is in a competitive relationship with each process. The interrupted process will be recovered by the software.
It is a process that has been stopped for a certain amount of time, and about this
are canceled as follows. Stop the process and start it again
The decision to do so is external to that process. like this
A process suspended in is not in an operational state and therefore
Unable to receive event notifications and unable to use CPU. The process is interrupted under the following conditions: (1) By executing a "stop" command (all functions are completed).
(2) “Suspend” command by the operating system
(3) Due to the occurrence of an exceptional condition, which causes the control to occur.
control is transferred to the operating system. B Dispatching a process A process can be dispatched to any one of its operations during execution.
transition from one state to another, or another process
The state is forcibly shifted to another state by the action of day
CPU firmware known as Spatschia
controls the process's transactions between each state.
control The dispatcher has one set of queues (waiting line).
Ready or Ready column (described below)
operates on each waiting process. interrupted
The process is controlled by software. In figures 6, 8 and 9, the ready or waiting
Machine state process is PCB, process link
is represented by a special queue entry called
Ru. Figure 9 shows the development of the contents of GO segment 802.
Process link 8 showing diagram and process in action
03a to 803b and 803c to 803g,
Free process link 805 for suspended process
a to 805c. Each process link is
Specify the process name (JP) and give priority to that process.
rank and the next process link in the queue.
Specify the pointer to Standby queue 803a~
Various types such as 803b and Ladykyu 803c~g
There is a queue. The J-table (Figures 6 and 8), also known as the G-table,
Similar hardware equipment is available for all general purpose (system
Segment 802 (known to span the entire system)
Contains a pointer to ~802n. G table 801
GO, the first element of
Indicates the segment 802 that includes. G table 8
The G table pointer for 01 is the system base in Figure 5.
found in the Also, the system base includes
Internal process keywords with bird calls
(IPQW), which is in GO segment 802
Heads of ready queues 803c to 803d
803. In this way, the dispatcher is ready
By referring to 03c~803d, all rede
You can consider the process. Currently running process
When the dispatcher changes state, the dispatcher is ready.
Remove process link at queue head
and use the JP name to access the PCB.
Ru. The process defined by the PCB is then renewed.
This results in a new execution process. One or more processes are waiting on the same event
Because it may be possible, queue 803a of the standby process
~803b exists for each event. Also, waiting
process is a process that exists in the GO segment
They are arranged together via a link 804. Wait
The pointer to the head of the machine is a semaphore.
903 (described below). a process
There are many events for which each
Many with associated semaphore 903,904
There is a waiting queue. The number of processes in ready or waiting state is dynamic
Changes to In this way, the ready status or waiting status
The number of process links that require state queues is also
fluctuate. This fact is important for dispatchers.
Causing molly management problems. this question
The titles are called free process link queues 805a-c.
This is resolved by another queue that is revealed. This cue
is used by a ready or standby queue.
a specific queue of ready or waiting processes.
segment GO that can be used to expand
Link all process links together.
Head 902 of free process link queue 805
Pointer 901 to GO segment 80
It exists near the beginning of 2. C Process synchronous operations Process synchronous operations operate on the same task.
necessary to relate the immobility of the two processes
It is. This synchronization operation
Semaf, a data structure that exists in Resspace
This is accomplished using ORs 903-904. Semakh
OR signals the occurrence of an event and sends a message.
- used for handling. Events in this case and
is one process that is of interest to another process.
This is what is observed by people. This event is non-identical
The completion of a period operation or the utilization of a certain resource.
Ru. The process uses two semaphore operations to
signals the occurrence of The operation sends a signal to the semaphore.
and other operations take signals from the semaphore.
(This sending operation is often called the V operation, and the receiving operation
is called P operation. ) This send operation is
the data or the belief that the data has been prepared in the process.
Let me send you the number. A semaphore is a semaphore that another process trusts.
Remember this signal until you are ready to pick up the issue.
Ru. In this way, the sending process sends this data to
Since you sent it, you can proceed freely. Receive operations are
Consider Mahoor and pick up this signal. If you believe
If there is a signal, the receive operation continues execution. but
However, if there is no signal on the semaphore, the receiving process
The device enters a standby state. Next, this semaphore waits
Acts as a pointer to the head of the queue.
Ru. This process is used by another process to
Waits for the semaphore until it sends a signal to the semaphore.
maintain standby status. In this way, semaf
or this signal until a process picks it up
A semaphore can be held or a semaphore is a signal processed
The process will be held until sent to. Messages are also sent from process to process.
Ru. A message is a signal with additional information added to it.
has the same existence or non-existence as some information
is provided by hardware, and some
provided by the procedure of the process that sent the message.
Ru. The message is the process name of the sending process.
has. In this way, many processes are
Information via a single named semaphore
I can send it. Message semaphore is picked up by process
has a queue of messages waiting to be sent.
Ru. Memories, as in signal semaphore
Demand for pace increases and decreases, memory money
The issue of management is raised. Again, this problem is also self-explanatory.
The issue is resolved with the message link queue. this
etc. links supply or absorb message links.
of segments that can be easily discovered when needed to
Exist in a known location. The semaphore and queue configured on these links
Since all sema are shared by different processes, all sema
The fore structure is protected. This is a semaphore
Hardware that restricts access to any segment containing
implemented through hardware and software commitments.
It can be done. Therefore, some of them are G segments (series
Semaphore or day (if stem communication is required)
The semaphore must exist in the script
Hey. However, all G segments (GO
) are semaphore descriptor segments
It is. Each semaphore descriptor corresponds to a semaphore.
Contains a pointer to. Semaphore address
is generated via a semaphore descriptor,
This strengthens the protection for this semaphore.
A semaphore segment has a segment number value and
using the relative location within that segment,
Or use the GD number directly to logically address
Can be specified. D Process control block structure In Figure 4, the process control block
(PCB) format is shown. This program
Process control block 400 maintains the state of the CPU.
Main memory storage available to processes for managing
It is an area. PCB addressing is related to Figure 5
and is carried out as already described. PCB pointer 5
07 (Figure 5) is memory location 0 in Figure 4.
Directs the process control block PCB in the
If you move the memory location downward, you will get 4 bars.
memory location increases from memory location 0 to memory location 0.
It should be noted that as you move upwards, the number increases by 8 bytes.
It is. The lower memory location is positive from 0.
It is considered that the location above from location 0 is
The direction is considered to be in the negative direction. upper location
is optional and is a process control block.
It may or may not be included in the location.
Yons 148-176 are also optional. (Downward
The memory location number of the process control
Byte from 0 reference location of block PCB
used to identify parts of the attached drawings.
Do not confuse with common numbers. ) Byte 0?
Considering the bytes smaller than 16, there are 4
The process main words PMW0 to PMW3 are memorized.
and each process main word PMW is 4 in length.
It's a part-time job. Process main word 0 is byte 0~
It occupies the
priority byte, priority byte, status byte and
and decor from the extended byte DEXT.
Ru. In steps 10a to 10d, the process main work
The details of the code PMW0 are shown, and the capacity byte is 100.
Further details of 1 are shown in FIG. 10b.
In Figure 10b, the first bit 1005
The time account function is about that process
Accounting mode indicating whether
It's Dobitsu. This accounting mode
When bit 1005 is set to binary 0, the
The time accounting function for the process of
Not implemented, but accounting mode 100
Time account when 5 is set to binary 1
is done. Science mode bit 1006 becomes zero
When set, the computer's scientific data register
is not stored, and bytes 148 to 1 in Figure 4
Register storage area for scientific data located in 76
indicates that it is not present on the process control block PCB.
vinegar. Science mode bit 1006 is set to binary 1.
When a scientific calculation function is present during the process
used and optionally for registers for scientific data.
Register storage area for scientific data to store contents
is used. Code mode bit 1007 is
Standard code set or compatible code set
is used in the process and
The standard code set is used for the binary 0 in the
while the third bit position
The binary 1 in 1007 is a compatible code set.
Indicates that is used. Each of this capacity byte
The remaining bits are set to zero. Details of priority byte 1002 are shown in Figure 10c.
shown. In Figure 10c, the priority byte
The first four bits 1008 of 1002 are
Process control block PCB and related
It is used to set the priority of the process. each
Processes are assigned to one of 16 levels of priority
(a) Ranking of competing processes, i.e. (a)
selection of processes to run between processes that are
and (b) put the process into the queue.
used. Priority decreases from 0 to 15
For a given priority, FIEO
The principle of "first out" is given. priority byte
The next four bits 1009 after 1002 are zero. Details of status byte 1003 in Figure 10d
is shown. The state byte is a process control block.
information about PCB400 and related processes.
used to provide. bride field bits
A1010 is 2 when the process is bound.
Set to base 1. Suspension field S10
11 is a binary 1 when the process is suspended
is set to . substate field
SS1012 is a 2-bit field that is used for processing
The following substates of the state are specified. That is, (a)2
When set to base 00, the process is immovable.
(b) When set to binary 01, the process
queue (Q/PR/RDY) of a process in the active state.
(c) when set to binary 10.
Seth is in Semaphore's Q/PR/S
Standby in semaphore, (d) set to binary 11
The process is being executed by the processor when it is invoked.
Ru. Mid-operation field
(MOI) 1013 is a binary 1 when an interrupt occurs.
is set during instruction execution, i.e. at the end of the process.
This will be maintained until the end of the term. extended decor
(decor) Mode bit EXTD1014 is
Extensions where the source is the emulation mode of the computer
Set to 1 when in decor mode. bits
Bits 1015 and 1016 are set to zero. Professional
The fourth byte of main word PMW0 is decoded.
contains the file extension number and the system emulates it.
Used when in mode. The process main word PMW1 is the process control block.
Stored in bytes 4-7 of the PCB. PMW1
The details are shown in Figure 10e. status byte 10
16 is the first byte in PMW1,
Store status register contents. multi-processor server
The MP1018 has a multi-processor structure and is tall.
, otherwise this field is zero.
Ru. 2nd and 4th bytes of process main word
are MBZ fields 1017 and 1019 respectively.
So, in normal operations, it must be zero.
stomach. The process main word PMW2 is the process control block.
It occupies part 8 to 11 of Tsuku, and is updated in Figure 10f.
is shown in detail. In Figure 10f, bit
Fields from bit 4 to bit 31 are semaphore stations.
Contains department name SEG, SRA1021, and for this
when the process is in standby or suspended state
PCBs are linked. exception class and tie
Field 1023 is a class for exceptions similar to interrupts.
contains the process and type, which will be processed after the exception operation.
cause the process to enter the suspended state. Bit 4 to
15 field 1022 indicates that the process is
It becomes meaningless when it is in a state other than the state. The process main word PMW3 is the byte of PCB400.
occupies points 12 to 15 and indicates the decor expansion table.
Ru. In figure 10g for details of PMW3
Therefore, DETSZ field 1024 is the entry in the table.
If this field is zero, then
Decor extension operations on processes are not allowed.
stomach. DETA field 1025 is a unit of 16 bytes
DETSZ is the absolute address of the Decor extension table of
It is only meaningful if it is not 0. this decor
The extended table consists of DETSZ entries. Each
The entry is 1 byte in size. of the table
The DEXT entry specifies the capabilities of the process
and perform operations in Decor expansion mode DEXT.
cormorant. When DEXT byte is 0, decorate
Extended number value DEXT is not allowed, but the DEXTth
If the byte is 1, the Decor extension number value DEXT is
forgiven. DEXT number values other than 0 and 1 are illegal
becomes. (See Figure 10a DEXT number value 1004)
) Bytes 16 to 23 of PCB400 are each address
Each address contains the dress space words ASW0 and ASW1.
ASW is a pointer to the segment table word array
Including data. The partners of ASW0 and ASW1 are respectively
The same format as shown in Figure 10h.
have The size of the segment table word array is 1
specified by the segment table word number in the column,
Mainly 6 for ASW0, and 6 for ASW1
becomes 8. STWSZ field 1026 is segment
Indicates the size of the ment table word array. segment
Field STWA1027 of table word array is
Absolute address STWA of 16-byte unit array
contains, i.e. the absolute address of this array is in bytes.
It is 16 times that of STWA. Bytes 24-27 on the PCB are the 10i
Contains the exception word EXW, which is shown in more detail in the figure.
nothing. This exception word is a pointer to the exception class table.
(SEG, SPA) 1029, and the table above
is stored in the process main word PMW2.
taken following a process exception due to that class
Define the desired action. (See Figure 10f)
The MBZ field 1028 of the code EXW must be 0.
Must be. Stats placed in bytes 28 to 31 of the PCB
The quarter SKW is shown in more detail in Figure 10j.
when the process is not running.
Contains the number at the top of the T register of the stack. 1st
In the 0j diagram, bits 0 and 1 are the TAG file.
A code 1030 is defined. This TAG field is
The content indicates the type of descriptor,
Must be zero for SKW. SKW Wa
Bits 2 and 3 of the code are RING field 1031
This field contains stack segmentation.
address and associated protection ring number
must be zero in this case. bit
4 to 31 are segment numbers SEG and segments
Contains relative address SRA1032, segment
Segments described in the table and their internal segments
This field identifies the target relative address. vinegar
The task word SKW indicates that the process is not running.
It will be updated each time. This is executed by the process
To re-store the contents of the T register each time the state changes.
used for. In this last case, TAG10
30 and RING1031 are tested to be zero.
otherwise an illegal PCB exception operation will occur. Bytes 32 to 35 of PCB400 are often ICC
Contains an instruction counter content word called ICW.
nothing. In Figure 10k, TAG field 10
33 must contain the binary digit 00 (i.e. non-zero)
is illegal in the instruction counter)
The details of the command counter word ICW are shown.
Current RING field 10 occupies bits 2 and 3
34 is used to determine access rights to the main storage device.
Specifies the current ring number of the process
Ru. Bits 4 to 31 are the segment number and
Specifies the client relative address (SES, SRA) 1035.
These specify the address of the next instruction to be executed.
stipulate. The MBZ field of bytes 36 to 39 is zero.
There must be. (The MBZ field is always zero.
) This MBZ indicates the field that must be
The word is called every time the PCB is called from the name JP.
be tested. If this is not zero then it is illegal PCB
An exception occurs. Stack base words SBW0-2 are processes
Bytes 40-51 in control block 400
occupy These words are further detailed in Figure 10l.
It has the same format as shown in detail. this
are used for stack operations, and when used
Its TAG field 1036 and RING field
1037 must be zero or it will be wrong.
A PCB exception to the law occurs. Bits 4 to 31 are
Each stack segment for groups 0, 1, and 2
segmented address of the first bit of the
(SEG, SRA) 1038. Byte 52 to process control block 400
83 is for base register storage area (8 words)
This is a reserved space. Part-time job 84no
to 147 is the number of all general-purpose registers (16 words)
This is a storage area used to store values. Ba
Bits 148 to 179 are registers for scientific data.
Storage area used to store (8 words)
It is. PMW0 word accounting mode bits
PCB for time account when set up
PCB 400 with address above zero has 5 double words.
is given. These words are the PCB addresses.
It is located from PCB address -8 to PCB address -40. each
The word is the one whose bits 52-63 are zero.
Displayed in microseconds in the first 52 bits.
includes the time or time interval that occurs. Remaining time is up twice
Word RTO (first 8 bytes greater than or equal to 0 on the PCB)
is executed before the timeout exception operation occurs.
of a certain amount actually spent by the processor for
Including time. The RTO word is updated in the following way:
It can be done. That is, each time a process exits the running state,
The process timer value is stored in the RTO word.
It can be done. Each time a process enters the running state,
The timer values are loaded from the RTO. Execution time account in bytes 7 to 15
The double word in the ing RUA is a time counter and
This means that the process was in the running state.
Specify the total amount of service time. Accounted time
is actually executed completely by the processor for the process.
is the time spent on. The RUA word is below
updated in a way. That is, the process changes its execution state to
The value of the process timer PT is read every time the machine escapes.
It will be done. The difference between RTO and PT content is added to RUA.
It can be done. (The PT value is then stored in the RTO)
Note that the time the process is interrupted is not calculated.
I want to be understood. The RTO and RUA words are
Counting mode bit is set to 0
will be updated even if However, CET,
RTA, and WTA words (described below)
is the account in process main word PMW0.
when the setting mode bit is set to 1.
is given in the read process control block. these
word is updated in this case. Waiting time account in bytes 17 to 23
Teing WTA Word is a real-time counter and professional
Specifies the total actual time that the process was in standby state.
WTA words are updated in the following ways: That is,
day each time a process exits the waiting state
The time value TOD of the clock (not shown) is read.
Then, the value of TOD minus the value of CET word becomes WTA word.
Added. Ladies placed in bites 24 to 31
Time accounting RTA word is real time accounting
The process is ready when the process is ready.
Specify the total time spent in the event. RTA is the following method
will be updated. In other words, the process leaves the ready state.
The day clock time value TOD is read each time the
Therefore, the TOD contents - CET contents are added to the RTA.
Ru. Current entry time in bytes 32-39
The CET double word indicates that a process is in each of the following states immediately.
Ready, Wait, Execute and Suspend
Including daytime. System base structure In Figure 6, the system base 600
-mat is shown. This system base is absolutely
Located in main memory and generated by firmware
Boundary that can be read but not written
Accessible via address register (BAR)
It is Noh. This boundary address register BAR is
An area of main memory reserved for hardware
area and is reserved for hardware.
Divide the memory area and system base 600
do. Next, in Figure 6, this system base
600 contains a number of system attributes, which are currently
job step number and
Contains the process group number (JP). P
From the logical name of Process JP, the corresponding
The absolute address of the access control block PCB is obtained.
Ru. The size and address of J table is J table word.
(JTW). This word is
Placed at address specified by BAR register
be done. The format of JTW is shown in Figure 11a.
be done. Figure 12 shows the size of J table 1204.
(JTSZ) 1101 is J table 120 up to 255
Specify the entry number in 4. JTSZ11
01 is an 8-bit positive integer, if J is JTSZ
If the value is also large, an exception from table J will occur. J table 1
The absolute address of 204 is the J table pointer 1102.
Obtained by 16x. J table 1204 is J table entry
11b, the format of which is further shown in Figure 11b.
Shown in detail. Each J table entry points to a P table point.
P table 1205 obtained by multiplying data 1104 by 16
Specifies absolute addresses. P table size
(PTSZ) 1103 is the entry number in the P table
stipulates. This PTSZ is an 8-bit positive integer
In order to indicate the entry number of the P table, it generally starts from 0.
Varies up to 255. If P is larger than PTSZ
If so, an exception from the P table will occur. Each of P table 1205
The entry is the process control block pointer 11
Process control block (PCB) by 16 times of 07
1206 absolute address is defined. existence index
Icator P1105 is set to binary 0.
indicates that the PCB is not present, and sets it to a binary 1.
Indicates the presence of a PCB when detected. (Existence I
When the indicator P1105 is 0,
An empty P table entry exception operation occurs. ) P table index
Bits 1 to 7 of the icator (Figure 11c)
(MBZ)1106 must be 0 or
If so, an illegal P-table entry exception operation will occur. System base 600 address BAR+4
In this case, the G table shown in more detail in Figure 11d
There is a word (GTW) format byte.
The size and address of the G segment table 1212 in FIG.
Dress is determined by the contents of G table word (GTW)
be done. G table 1212 size (GTSZ) 110
8 specifies the entry number to the G table, and the G table is a general
up to 255. GTSZ is an 8-bit positive integer
, and if the value of G table is larger than GTSZ
An exception from the G table occurs. Absolute a of G table 1212
The dress is obtained by multiplying the G table pointer 1109 by 16.
It can be done. The format of the G segment table entry is
A G segment script with a size of 2 words.
It is called ta. G segment descriptor frame
The ormat is shown in detail in Figures 11e and 11f.
has been done. All G segment descriptors
is direct, so the indirect bit I, 111, is zero.
Must be otherwise illegal segment
A descriptor exception operation occurs. existence inday
Cater P1110 is a one-process field,
When this is set to a binary 1, it is
main memory for the segment number corresponding to the data.
indicates that the segment is defined in
If is cleared to 0, the segment is unspecified and the segment is
A reference to a component descriptor is missing (missing).
error) causes a segment exception. Available videos
A1112 is a 1-bit field, and this
indicates whether the segment is available,
This segment is defined (i.e. P is a binary number
(equal to 1) is tested to see if the length is
If not, it will be ignored. Used flag field U
1113 indicates whether the segment was accessed
shows. If the U bit is set to binary 0,
If so, the segment has not been accessed.
However, if the U field is set to binary 1,
For example, the segment was accessed. Written flag
Tsugfield W1114 has a segment written to it.
Indicates whether the If W is set to binary 0
If the segment is written, the segment is not written, but
If W is set to binary 1, the segment is
Written. G segment descriptor game
The action indicator GS1115 is set to binary 01.
must be registered, otherwise illegal segmentation
A current scripter exception occurs. The reason for this is that
a semaphore always contains a semaphore (the converse is not true)
but. That is, all semaphores are in the G segment.
), the semaphore command is
This is to require that the code be the binary number 01. Se
The absolute address of the base of statement 1214 is 24
The 11th bit base field 1116
Specified in the G segment descriptor in figure e,
The contents of this field are multiplied by 16 to form the absolute address.
get. G segment disk script in Figure 11f
The second word of the data is the bit in G table 1212.
It occupies positions 32-63. Bit 32
RSU fields 1117 to 39 are software
Reserved for air, as in this case G segment
Generally when used as a ment descriptor
It will be ignored. MBZ field 1118 is 0.
otherwise illegal segment exception
happens. MBZ field 1118 is bit 40
to 51, so the segment size is small.
SIZE field 111, which is the field for
9, all G segments are small
Must be of segment type. segment
SIZE1119 is the bar in that segment.
is a 12-bit positive integer that specifies the bit value,
Consider the size of this segment to be a multiple of 16
It will be done. Therefore, for G segment 1214
Segment size is 2 ¹⁶ I can do more than my part-time job.
(small segment). Again in the system base 600 of FIG.
9 placed between BAR+8 and BAR+4
There is a system exception cell word. this system
The format of the exception cell word EXC is 11th g.
As shown in the figure. Semaphore when system exception occurs
transmits a message to a given process.
for these semaphores.
A pointer can be found in nine locations in memory.
each location is called a system exception cell.
There is one for each class of called system exception handling.
MBZ field 1120 is set to binary 0.
must be checked, otherwise system check
happens. Each exception cell (EXC)
Includes name names GD1121 and 1122. Located at BAR+44 of System Base 600
The channel exception cells that are
It has a format similar to a cell and has a channel exception.
send a message to a given process when
The system name of the semaphore used to
Including GD. Internal processor keyword IPQW is BAR+48
The format is
Details are shown in Figure 11h. This IPQW word
are shown in FIG. 9 with reference numbers 905 and 805.
queue (Q/PR/
RDY) head. Ready professional
Sesquiyou (Q/PR/RDY) is in ready state.
Link all processes that This is a lady
By pointing to the top of the state process queue
IPQW word Q/PR/RDY HEAD file
Referenced by field 1124 (Figure 11h)
Ru. Q/PR/RDY HEAD field 1124
contains a 16-bit positive integer, which is a GO segment
From the base of G segment number 0 called
This is the displacement up to the first byte of Q/PR/RDY.
If this Q/PR/PDY bit field is 0
, the queue in the ready state is considered empty.
Ru. MBZ field 1123 must be 0.
Otherwise, a system check will occur. System Base 600 BAR+52 smell
storage of initial and current retry counts.
location, the format of which is detailed in Figure 11i.
Shown in detail. NFS field 1125 is non-mechanical
functional memory field, system-based
Not used. Initial retry count fill
code 1126 and current retry count field 1
127 controls the number of times, automatic command retry is
Mechanical error is caused to form a mechanical failure exception condition
executed previously. These fields can be reset
The same result is determined by the retry count (not shown in the text).
A few lengths are loaded. Execution process word shown in Figure 11j
(RPW) is system base 600 BAR + 56
is remembered and prioritized in case of monoprocessor structure.
Used to remember the names of running processes.
It will be done. NFS fields 1128 and 1131 are
Each is a non-functional memory field, and can be used on any device.
Can be used for any purpose, but is generally system-based.
Not used for The priority of the running process is
Stored in PRI field 1129. Asynchronous
The lap bit is stored in AB field 1130.
However, asynchronous trapping uses the ARN file.
The information is stored in the file 1132. Monoprocessor structure
The logical name JP of the running process is the JP file.
The data is stored in the field 1133. The absolute value table pointer shown in Figure 11k is
Located at BAR+60 of stem base 600,
Used during initial system load (ISL)
All absolute addresses in the ISL program must be in BAR.
initial system load (ISL) by adding
Initializes the absolute address in . This absolute
The value conversion table pointer 1135 is an absolute value conversion table (not shown).
Specify the location of This absolute value table
The size is indicated by ATSZ field 1134.
Ru. The CPU sequence number word shown in Figure 11l is
A 4-byte word placed in BAR+64,
CPU in CPU sequence number field 1136
Contains consecutive numbers. The main memory upper limit word shown in Figure 11m is
BAR+68, the most
giving the absolute address of a later available word
indicates the main storage upper limit 1139. In BAR+72, initial system load
ISL equipment channel number (CN) 1140 and hardware
hardware equipment channel number (CN) 1141 and
The words shown in Figure 11n are arranged to give
It is placed. Types of equipment used in computer systems
Type and subtype are fields 1143 and 1143, respectively.
Hardware equipment type word in 1144
(Figure 11o), in which case the RSU
Field 1142 is reserved for software.
has been done. This word is in BAR+76
Found within the system base. In figure 11 p.
A format similar to the one shown above
Similar words with
Includes the type and subtype of equipment used in the code.
nothing. This word is placed at BAR+80. Press the restart button on your computer to restart the computer.
A rate V operation is performed for one semaphore,
Enter the ready state. Points to this semaphore
The printer is found in System Base 600 BAR+84.
issued and called the restart cell word, Figure 11q.
It has the format shown in . This format
The exception cell is similar to the system exception cell described above;
G field 1149 and D field 115 respectively
Contains the system name GD of the semaphore in 0.
nothing. MBZ field 1148 must be 0.
No. One or more
If you have a processor, for multiprocessor expansion
word is system base 600 BAR+88
given to. Details of this word are shown in Figure 11r.
shown. System-based and Process Control Block Usage Example In Figure 12, the user segment
component, system segment, or ready status program.
Sesquiyou (Q/PR/RDY) segment ad
How do I configure the system for response specification and access?
System base combined with process control blocks
This is an example of how it can be used. Main memory 12
00 is a section reserved for hardware use.
1203 minutes. boundary address register
BAR1202 uses system base 1215 as hardware.
Memory 1203 reserved for software
Separate from a part. This boundary address register
BAR1202 is system-based.
For the displacement of the desired item in units of 4 bytes
In system base 1215 by adding
Used to address matters. Next
The address of the desired system is based on
indicates the first byte of In Figure 12
BAR1202 indicates J table word (JTW)
are doing. As mentioned above, this J table word is
It has a pointer pointing to 1204. In Figure 5
By indexing the indicated J number,
Table entry 1216 is obtained. J table entry
and specify the absolute address of P table 1205.
There is a P table pointer. P number in P table 1205
(See Figure 5)
The absolute address of the process control block 1206 is obtained.
It will be done. Already installed on process control block PCB 1206.
The two address space words as shown in
There are ASW0 and ASW1. Base register 120
Segment table number field STN in 1
The upper bits are these two address space words.
In this case, it is used to access one of the
In , ASW1 is the segment table word array
Segment table word pointing to STWA1208
Contains a pointer to the array STWA. base regis
8 along with the segment table number STN of data 1201.
One of the segment table words is STWA120
8, this is the 8 segment table 1
210. Base register 120
Segment table entry STE from 1 then
The segment in which a certain segment descriptor is placed
One of the 256 entries in the ment table 1210
used to do this. Next, this segment data
The scripter accesses user segment 1211.
used for accessing. (For further details, please refer to this publication.)
Transferred to the same person as Ming's transferee and included in the text for reference.
It was acted upon. “Segment” patented on February 10, 1975
U.S. Patent No.
(See issue 3938096) System segmentation used to store semaphore
system base to access client 1214.
G table word GTW is used in 1215.
Ru. The address of this G table word is
The displacement of the G table word in the boundary address
By adding to the register BAR1202 (Fig. 6)
can be obtained. This G table word GTW is G table 121
Contains a G table pointer pointing to 2. benefit the system
Use the available G number and index it in the G table.
The system segment 1214 can be accessed by
G segment day used to specify dress
Scripter is accessed. Similarly, Q/PR/RDY segment 1213
Place internal process keyword IPQW to direct
By doing this, the ready state process queue (Q/
PR/RDY)
1215 is used. G Control Unit Details of the control unit are shown in Figures 13a to 13c.
details are shown. This control unit is a central
shown separated from the processing unit (CPU)
is actually part of the CPU and control storage unit.
CSU1301 and control storage interface
What is the adapter CIA1302?
, control storage loader CSL1303, and control and loader
It consists of a host unit CLU 1304. The control storage unit CSU1301 has control and
Load unit CLU1304 and control memory interface
- Control recording via face adapter CIA1302.
Receives microinstructions from memory loader CSL1303
Ru. Under normal computing conditions, the microprogram
is loaded from an external source during system initialization.
is programmed and becomes a permanent control function of the computer. However
However, the control storage unit CSU1301
Perform various calculation modes of the central processing unit CPU104.
It has the ability to be reloaded and initialized as required.
The following calculation modes of the CPU are controlled by the CSU1301.
Available below. That is, (a) native mode
(b) Emulation mode, (c) Native and emulation mode
(d) diagnosis mode. child
The ability of the microinstructions in the CSU to
used to control the calculations of the CPU functional unit.
This is possible because it is a source of microinstructions. Before
The CPU functional unit described below is an emulation
Unit 1316, arithmetic logic unit ALU13
17. Instruction fetch unit IFU1318, address
control unit ACU1319 and data management
management unit DMU1321. Matanaka
What is known within the central processing unit CPU104
is the general-purpose register 1307 mentioned above and the base register.
register 1308 and scientific data register 1309
, T register 1310, and status register 131
1, instruction counter IC1312, and hardware
A control mask register 1313. Generally, the control storage unit CSU 1301 is
9K bipolar integrated circuit with read/write
mixed with random access storage (RAM)
Programmable read-only memory (PROM)
Ru. This is especially true for 150 nanosecond read cycles and 450 nanosecond read cycles.
and nanosecond write cycles. control memory
Each location in the
Memorize the command words (described in more detail below) and
A microinstruction word controls one CPU cycle.
control Control of control storage unit CSU1301
As each storage location is read, its
The contents are decoded by a micro-arithmetic decoder and this
Each decoder handles a special operation that occurs within the CPU.
Micro-operations that cause calculations (described in detail below)
Give control signal. Classifies locations within each microinstruction word
(described in detail below) to configure a specific CPU
a sequence of control memories capable of performing operations or instructions
can be obtained. Each instruction is launched by the CPU
, a bit in the OP code indicates that the control memory activation system
used to determine the Instruction decoding function
Certain flip-flops that are set or reset by
A test of the control memory memory (not shown)
Molly can be further blocked into specific sequences as needed.
Lunch will be served. Control storage interface adapter CIA130
2 is a control storage unit 1301, a data manager
management unit DMU1321, and the 13th
Instructs the calculation of the control memory 1333 in figure b.
Communication with the arithmetic logic unit ALU1317 for
Ru. This CIA1302 is used for control storage address modification.
decoration, testing, error checking, and hardware
Contains logic for dress generation. hardware
Address generation generally triggers an error sequence
Used for address generation and initialization sequence.
used. Data management unit DMU1321
is the CPU 104 and the main memory and main memory shown in Figure 1.
and (or) buffer storage memory.
provide an interface. which unit is the other
Recognize whether the unit has the necessary information
and stores this information in CPU registers at the appropriate time.
This data management method
This is the responsibility of the management unit. Also this data money
The management unit DMU performs maintenance during partial write operations.
Do skinning. The instruction fetch unit IFU1318 is the DMU1
321, ACU1319, ALU1317 and
Interface with CSU1301 and use it as CPU
It is possible to respond by continuing to give commands. Instruction fetch
The unit completes its register prior to completion of the current instruction.
to keep the next instruction available in the
Ru. To provide this ability, the instruction fetch unit
The IFU1318 typically contains 12 instructions containing one or more instructions.
and an instruction register (not shown) for the bit. Furthermore,
The IFU, under control of the CSU, determines whether the instruction is actually needed or not.
requests information (instructions) from main memory before
The 12-byte instruction register is constantly updated.
is maintained. Commands are not normally used like this.
It is pre-fetched by a new memory cycle. Matako
The instruction fetch unit decodes each instruction and sends it to other units.
Indicates the length and format of the instructions
Ru. Address control unit ACU1319 uses CIA
communicates with IFU, ALU, DMU, and CSU through
Ru. ACU1319 generates all addresses in the CPU.
Responsible for development. All including transmission inside and outside ACU
The operation of the ACU is based on the micro operations of the CSU and this module.
Directed by logic within the unit. ACU's
Normal cycle behavior is during instruction rather than instruction type.
depends on the type of address. address tie
Depending on the program, the ACU may
and perform different operations. Also, this ACU has eight
Base address of last used memory segment
memories along with their segment numbers.
It includes an associative memory 1319a. memory request
Each time a segment is created, this segment number is stored in associative memory.
The base of the segment
Determine whether the address has already been generated and memorized.
Ru. If the base address is associative memory 1319
a, this address is an absolute address.
can be used to generate resources, saving considerable time.
Ru. If the base address is associative memory 1319
If it is not contained in a, access the main memory table.
generated by processing. However, this segment
After the base address of the target is generated, it is used for future references.
Associative memory with its segment number for reference operation.
- will be stored within. Interfacing with ACU, IFU, DMU, and CSU
The arithmetic logic unit ALU13 is in front of the
It is 17. Its basic functionality requires the CPU
It consists in performing arithmetic operations and data manipulation. This calculation
The operation of the technical logic unit is completely controlled by the memory unit.
Micro operation control signal from CSU1301
Dependent. Related to ALU1317 and CSU1301
Scratchpad memory unit LSU
1315 (sometimes also called local storage unit)
). This is typically 256 locations
(32 bits per location) solid state
root memory and selective reading of that memory
It consists of write/write logic. This scrub
The built-in memory 1315 stores CPU control information.
used to store information and integrity information. Furthermore
Scratchpad memory 1315 is the working location.
This primarily includes operations during data manipulation.
Used for temporary storage of perrando and partial results
be done. Also, it is related to ALU1317.
is especially used to remember each state of a computer system.
Auxiliary memory consisting of 64 flip-flops for
-1317a. The CPU also has a clock unit 1320.
However, it becomes two clock systems for one clock system.
There is. That is, the first clock system
Timing of Turf Ace adapter CIA1302
The second clock system is located within the central processing unit.
The timing pulse for the operation of the functional unit of
Occur. Next, in FIG. 13c, control storage word 13
25 formats are shown. This control memory
The field is 84 bits wide and consists of 6 main fields.
It is divided into. That is, a sequence type field 1326 (3 bits)
), b branch and/or micro-operation 132
7 (23 bits), c Constant generation and instructions 1328 (14 bits), d Data to bus 1329 (bits), e Micro operations 1330 (32 bits), f Checking 1331 (4 bits). 3-bit E-fee in control storage word 1325
field is used as a sequence control field.
It can be done. This computer system has seven
Different sequence types and one reserved
There is a type. Block 1335 of Figure 13b
, the E field is a binary 0, 1, or 2.
When equal, the branch file of microinstruction 1325
fields A, B, C, D, and L are the following addresses
used to generate. The highest value of KS register 1337
The first 6 bits are B field, C test result, D
used with test results and L fields.
gives the next address of the next microinstruction, and
The microinstruction is written in the next address register KS13.
37. E field is binary 4
(see block 1335), the next
The selected address of the interrupt return register
Extracted from KA1339. Recorded in KA register
The stored address will be updated when a hardware interrupt is generated.
is generated by the following address generation.
be. E field set to binary 5
When a branch operation is used to write a microprogram
A subreturn from a subroutine is set.
Ru. When a branch operation is used, the return register
The contents of star KR1346 are the following control memory address.
used as. This return register 134
6 is loaded by issuing a control store command.
This command is executed by the incrementer 1338.
KS register 13 for KR register 1346
Load the current control memory address of 37 + 1.
Ru. One level of nested subroutine ability is
via KT return branch register 1347
Given. KR register 1346 is loaded
Each time, the original contents of the KR register are changed to the KT register.
transferred to the microprogram retarder 1347.
The contents of the KT register are updated to the KR register each time the command is called.
transferred to register. Third level nested service
Routine capabilities are given by KU register 1348.
The fourth level nested subroutine ability is
Given by KV return branch register 1349
available. The E field of the control storage word is binary.
When set to 6, the next address is specified.
The control storage word that has been
The current address of KS register 1337 in
Equals +1. This E field becomes 7 in binary
When set, the CSU1301 is in diagnostic mode.
The next address will be the current address + 1.
Dew. The next step shown in previously described block 1335
Sequence of branch operations to control storage addresses
In addition to the control, shown in block 1336 of Figure 13b.
The sequence control generated by the hardware
be. (Note: Blocks 1335 and 1336 are actually
When a microinstruction word is written in a hardware register,
)
Branch operations generated by this hardware are
Validation conditions (errors, initial settings, control memory scans)
etc.), and for this reason, the E field is controlled and fixed.
Address control memory address register KS133
Force 7 to send it. This branch operation is
with the lock period length interrupt line (not shown) high.
The address that should have been generated under E field control
Store it in the KA interrupt return register 1339.
This is done by hardware generated address
is stored in the control storage address register. be
Interrupts generated by hardware/firmware
The operation is interrupted by another interrupt in that class.
Interrupt that prevents execution until a condition is met
Overrides flip-flop (not shown)
Has a ranking. The firmware micro operation is
These sequences are under firmware control.
Interrupt-blocking flip-flop reset for
It exists to control. This hardware control
The sequence below automatically
resets the blocking flip-flop.
The following conditions, listed in order of priority, are in this category:
- Enter. That is, (a) control memory load, (b) control memory
Address scanning, (c) hardware error, (d) software
Wear error. The remaining hardware requirements are interrupt prevention.
When generated without setting the stop flip-flop
It is made to act immediately as it occurs. The following terms and conditions
fall into this category in order of priority. (a) Initialization (b) Queer in software (c) Entry in security panel (d) Entry in security channel (e) Termination by hardware Initialization signal addresses binary 0
and clear the hardware resettable error.
and control memory scanning sequence under hardware control.
Blank to perform a control memory load operation followed by a
Have CSU1301 perform the process. Also, this is a system
Perform initial system settings. The soft clear signal is
Hardware reset by addressing binary 0
Clears trippable errors and prevents interrupts from flipping
Brush CSU1301 to reset the flop.
make them hurt. The maintenance panel entry signal is
to the CSU address switch on the channel (not shown).
branch the CSU to reset the address
Ru. The maintenance channel entry signal is the maintenance channel entry signal.
to an address generated via a file (not shown).
Branch CSU. This loaded ad
The response is from the maintenance bus QMB1344, which is a maintenance bus.
Part of the full channel and right-aligned. C
The end signal by the hardware is the binary address 2.
branch CSU. This sequence is
used as a total means. end of this sequence
is an E field with the E field set to binary 4.
Returns are initial by performing a yield branch.
Set. The control memory load signal is set to a binary 0 address.
Branch CSU. This is also a CSU lady
Cycle flip-flop (not shown) and system
Turn off Mukurotsuku 1320 and load CSU
state. In this loading state, the CSU
are control memory loaders CSL1303, IOC1305,
From main memory 102 or maintenance panel 1355
Can be loaded. Automatically when loaded from CSL
A scan occurs at the end of the load operation. Load operation
Scanning is performed by any other means.
The generation of calculation signals also prevents the scanning switch of the maintenance panel.
This can also occur depending on the settings of Tsuchi. control storage
The scan signal brushes the CSU to a binary 0 address.
make them hurt. The control storage scan
Under local hardware control. system during scanning.
Mukurokutsuk 1320 is OFF and therefore the command
No code or test is performed. of the scanning sequence
At the end the hardware interrupt return register
The contents of KA are transferred to address register KS and the system
The stem clock is turned ON and control is performed by the firmware.
It will be returned to A. The hardware error signal is CSU as binary 4.
branch to the address. Normal processing mode
In this case, which CPU functional unit is detected?
Hardware errors that occur are also hardware error times.
Activate the line (not shown). Generated control notes
Storage sequence testing system requirements
Decide what action to take. In diagnostic mode,
Hardware detectable error conditions are microdiagnosed.
It is discovered from the disconnection operation. This micro-diagnostic operation
Control the action to be taken. On the other hand, software
The error signal sets the control memory to the address of a binary 1.
have brunch. This address is micropro
Software error reporting system under program control
This is the start of the test. Again in FIG. 13c, E field 132
6 is a 3-bit file for branch code as mentioned above.
It is a yield. Branch and/or Mike
The arithmetic field 1327 is A, B, C, D and
and L field (block 1335 in Figure 13b).
), in which case the A field is:
The upper 6 bits of the address and the B field are 64 bits.
of the next address of the mask field in the
Middle 4 bits, C field is one of 64 tests
6-bit test field, D field
is another 6-bit test file for one of the 64 tests.
The yield and L fields are the least significant bits.
be. K field 1328 is a 14 bit field.
field, of which 6 bits are constant fields and 4 bits are constant fields.
is a constant or manipulated field, and a 4-bit
is an operation field for constants. to the bus
Data field 1329 is the QMB bus 134
It has 4 bits to control the information to the QA section of 4.
QA field and QB of QMB bus 1344
A QB file with 4 bits that controls information to the
It consists of a field. F field 1330 is 32 bits
Enter the micro operation subcommand in the
Coded to form. P field 133
1 consists of 4 bits reserved for testing. In operation, the microinstruction word is a control memory
Stored in device array 1333. calculation cycle
During this time, the control storage array is KS address register 1.
The address is specified by the contents of 337. this
reads the contents of the addressed location.
The output latch group 1357 is caused to read. reading
Each part of the word content of the output latch corresponds to each function of the CPU.
distributed or transferred to storage registers within the unit.
Ru. Each functional unit has a system clock source
defined by the control storage word under the control of
Decoding logic circuit for generating predetermined subcommands
including. In general, decoding also reduces the time
Also transmits command signals when signals are sent centrally
central section to reduce the number of cables required to
It is performed by each functional unit of the CPU rather than by the CPU.
Ru. Furthermore, the decoding process is
This is done within each unit to avoid timing problems.
It can be done. Furthermore, each unit can be used to execute subcommands.
Necessary for generating subcommand signals by decoding
to express a certain condition that exists within a functional unit.
These signals are returned to CIA unit 1302.
There is no need to Typical decoder unit 135
9 various fields from the microinstruction word
Receives micro operation signals a, b, c, d...
The generation of q, r is shown in Figure 13b. Ma
The microinstruction decoder 1359 is a microinstruction word processor.
Receives commands from the Is it a microinstruction word?
These fields are decoded and decoded into multiple lines s, t,
u...Set one of y and z. matrix
is the s-z line and the points α, β, γ……ψ, ω
A predetermined control line impedance connected with
It is formed by having . Next, the micro
When the fields from the instruction are decoded, the line s-
One of z becomes high. Greek letter α...ω
The darker dots shown in the matrix are two sets of lines.
In order to represent the impedance connecting between
Electrical signals propagating to the opposite line are also connected and impeded.
- Vertical line a where dance connections (dots) are shown -
It is transmitted along r. Then each vertical line a-r
is to each of AND gates 1360 to 1365.
Connected as one input. central timing
Other input signals including the timing signal ts from the control unit
Also connected to AND gates 1360-1365
Ru. Therefore, when each timing signal ts goes high, the other
All gates whose input signal is high are driven,
The microinstruction signal is sent to a predetermined function unit of the CPU.
Give to Tsuto. For example, if read latch 135
Command 1341 is decoded from 7 and horizontal line
When S is high, the vertical direction of a, b, c and q
The control line in the direction becomes high, and the AND gate 136
0, 1361, 1362 and 1364 are ts tone
As time signals are sequentially applied to these gates,
It is driven by In this way, the vertical control line
Water at different points indicated by the letters α to ω
The combination connected to the square control line is
Command signals are provided from control storage array 1333.
Each microinstruction in the central processing unit is
to the central processing unit CPU for controlling functional units.
represents a permanent switching matrix for supplying
In this way, a permanent firmware with switching characteristics
Air is required as a computer system capacity.
Simply specifying a sequence of micro-operations
Therefore, it can be configured within the computer of the present invention. Under normal conditions, data is stored in local registers.
CPU write data also known as yo1343
Write to control storage column 1333 via register
be caught. A control flip-flop (not shown)
Whether the top or bottom half of the storage array is written to
Specify whether the Control and load unit
Data from CLU1304 is transferred to maintenance bus QMB1.
344 to the CIA/CSU and control storage
Before writing to the storage array 1333, the storage local
Buffed by jista yo1343. this
Storage device local registers 1343 can be read and written.
time-shared into both local registers. multiple
Lexa KQM1345 has a maintenance panel 1355 or
is controlled by one of the microdiagnostic programs.
provides a read path connected from each register.
do. Comparison register KP1350 is for non-functional use
established and used for maintenance purposes and comparative logistics.
1352 and decoding logic 1351.
It can be done. H Dispatch arm for process control
Wear This day patch is firmware/hardware.
is a wear unit whose main purpose is to
Management of various queues and switching between each process.
process queues and process control blocks.
PCB, running processes within the system base, and new
Contains register updates for new processes. Also, this
The dispatcher processes the process in the semaphore.
(in an IOC or exception handler)
(after V operation, simulate V operation) to process
Transmit a message. Also, this means that the process
Free link semaphore to transmit the message.
P to release the message link when waiting for the
Queue message on semaphore after operation
Ru. This dispatcher also has native mode.
After the "roll-in" of the process execution in
If the current process runs in native mode
If inside, after the "contest", the native mode
A call is made to the command firmware of the program. Again this
is called with Decor extended firmware in the following manner.
Make a delivery. That is, (a) the process execution log in the Decor extension;
temporary invocation during rollout; (b) locking of process execution in said decall extension;
(c) Temporary invocation during call-in
(d) if the current process
After the contest if you want to keep it running
This is a limited call. In addition, the dispatcher will
Place the system in a dormant loop when it is not present
Ru. Persons coming in and out of the following dispatch stations:
There are several laws. (1) The initial configuration procedure (SIP) is the final step.
(assignee named in the text)
"System initial setup procedure" transferred to the same person as
U.S. patent application filed on December 2, 1970 with the name
(Refer to Application No. 528814) (2) The start and stop commands are
Perform entry. The startup command starts the process,
The command stops the process. (“Start and
The application filed on December 2, 1972 entitled “Suspension Order”
(See U.S. Patent Application No. 529,253) (3) The P and V operations are the entry to the dispatcher.
perform ri. P operation is message from semaphore
If the message is picked up and there is no message, the process is
Enters standby state. (“P and semaphore
Patented on February 15, 1972 entitled “V Operation”.
(See U.S. Pat. No. 4,374,409) Next, briefly, the dispatcher
manages each process and therefore tells which process
The currently running process
(i.e., hardware registration)
Current data included in data, scratchpad memory, etc.
Writes all information about running processes to PCB
) and roll in the new process (i.e.
All the information needed to run a new process
Hardware registers, scratchpad notes
Perform appropriate operations such as writing from the PCB to the
Manage your process control block PCB by
This is the main mechanism for Far arm wear carried out by dispatcher
calculations in the control unit (i.e. in the control unit)
The display is shown in flowchart figures 14a to 14i.
be done. For example, block 1402 of FIG. 14a
is an indication of the calculations performed by the dispatcher.
Yes, in this case the microprogram word is controlled
transmitted by the storage unit and decoder 1359
At the same time, a series of appropriate micro calculation signals are
Application part of CPU via No. 1360, 1361 etc.
The storage subsystem 102 system
Search for IPQW from base and scrub this
Transfer to chipped memory 1315. at the same time,
Dispatcher is a system-based G table word
Segment script directed by GTW
GO segment descriptor (No.
(Fig. 12) is taken out (1404). IPQW word
Bits 16-31 contain a 16-bit positive integer;
This integer is a G segment called GO segment.
Ready process queue from base with port number 0
– Q/PR/RDY head (first byte)
It is displacement. If bits 16-3 of the IPQW word
If 1 is 0 (1403), the ready status queue
- is considered empty. If you are in a ready state
If is empty, currently waiting in Q/PR/RDY
There are no processes in the queue and there is no ready queue.
do not have. Next to be determined in decision block 1405
The question is empty with the display indicator set.
The process is currently
Determine if it is running inside the calculator
It is to be. If the empty display indicator is
(i.e., the currently running process
), ready to use the processor
It has already been determined that there are no processes in the state queue.
The computer enters hibernation mode (140
6). However, if the currently running process
If the computer is in use,
If there are no waiting processes, the current
The process accesses its next instruction (140
7). Again, the decision block in the flowchart of Figure 14a
In block 1403, if the IPQW pointer area
If there is a positive integer in the GO segment
Ready state queue indicated by the IPQW word of
head is removed to scratch pad memory.
It can be done. (Note: To avoid repetition and for clarity, the control unit
Intermediate between the CPU and associated dispatchers
Functions are omitted. However, depending on the case,
Typical examples of intermediate functions such as those described in
It shall be shown more clearly. ) Up to this point, the main text
A queue with a waiting process in the day state
I had decided. before the next operation begins.
Whether there are any processes currently running in the processing unit.
A decision is necessary. Flowchart decision block
This is determined at lock 1410, and if
There are no processes currently running on the central processing unit (immediately
(CJP is not available), the head of the ready state
The command is executed (1412). However, the central processing unit
If a process is running on the
is a list of currently running processes and ready queues.
Decide which of the heads has priority.
Must be. Therefore, the execution program of the system base PCB 400
of the current process (CJP) located in the Seth Ward.
The priority byte is retrieved (1413). Then the current
Process CJP is waiting at the head of a ready queue.
Lower priority than new process NJP on board
A decision is made as to whether
(See Lock 1414). If CIP is lower than NJP
If it is not a priority, the CIP is controlled by the central processing unit.
Contest Indy Case
The data is reset (1415a). (This storyboard
The store indicator is executed for CJP and follows
1 after the start of the last instruction where there is a possibility of conflict.
More than one new process is in the ready queue
(under this condition, the contest index
The icator is set to a binary 1. ) except
Always set to 0. Current process CJP continues
be made to carry out any further orders.
Previously, CJP was run in decole extension mode and
A determination is made (1415). if
If CJP is running in Decor extended mode
The next instruction is in emulation mode (i.e.
(1419a), if
If CJP is not running in decole extension mode,
the next instruction will be executed in native mode.
(1419b). Return to decision block 1414.
However, if NJP, the head of Kyu in the ready state,
has a higher priority than CJP (i.e. its superiority)
The priority number is smaller than the CJP priority number)
If the currently running process CJP is from the calculator
“Lowered out” and new process NJP planned
It is "rolled into" the calculator. Therefore, Farm
The software priority subroutine PRIQ1418 is
Process CJP queue operation based on LIFO ranking
and firmware subroutine RLLO141
The first “low-out” victory by the CJP under the directive of 9
Direct to the queue in the ready state according to the priority number.
Ru. This RLLO subroutine uses general registers,
Base register, scientific data register, T register
stored in the master, status register and instruction counter.
Writes CJP information to main memory.
Return to appropriate storage area on process control block PCB.
to cause an RUA update. Furthermore,
Process main word 0 in PCB400
(PMWO) DEXT number will be updated. (142
0) Here, the new process NJP is
be prepared to be boundary address register
BAR is retrieved (1442) and the running process
RPW is system-based address BAR+56
(see block 1423). this
The name of the new process NJP is the next running process
New process NJP written to word RPW
In the process link PL whose name is Q/PR/RDY
Because the process link PL is written to
The system is therefore placed in the RPW block (142
4). Therefore, NJP from Kyu in ready state is
At this time, it becomes CJP and controls the central processing unit.
, so you can no longer wait for Q/PR/RDY.
Please enter the name in the Q/PR/RDY process link.
It must be removed from the queue by removing it from the PL.
Not (1425). Once this is done, the red
The queue of process Q/PR/RDY in the active state is
firmware subroutine UQLK, 1425a.
will be updated. Therefore, the permit retrieved from the computer
The JP number of the process is no longer controlled by the computer.
Q/
Placed in the process link of PR/RDY (142
6). At this point, the new process
and the transformation operation to give this control to the central processing unit.
and place the original process in a ready queue.
operations are performed and the output is under the control of the central processing unit.
Because there is a process (new CJP), the empty display index
The icator is set to 0 (1427). on the other hand
If there is no CJP under central processing unit control, the empty
The display indicator will be set to 1.
Ru. At this point, the central processing unit allocation
operation is completed and the new process is transferred to the central processing unit.
but the original process is in the ready state queue.
placed. However, the new process is shown in Figure 13a.
The hardware of the central processing unit 1306, for example,
register 1307, base register 1308,
Scientific data register 1309, T register 13
10, status register 1311, and instruction counter
It is not ready for execution against data 1312.
These are process control blocks for new processes.
must be supplied with control information from the
stomach. Therefore, the firmware subroutine 143
0 controls the CPU, first from the PCB (Figure 4)
PMW towards scratchpad memory 1315
Take out 3, then take out PMW0. PMW0
The MBZ field is checked (1433) and if
If this is not a binary 0, an illegal PCB exception will occur.
Ru. However, if the MBZ field of PMW0 is zero,
If so, PMW1 is extracted (1413). again
The MBZ field of PMW1 was tested and this
Determine whether it is a binary 0. If it's 0
If it is 0, an illegal PCB exception will occur, but if it is 0 then the device
Ispatsiya goes to C. Therefore, address space word 0
(ASWO) is taken out from a suitable space on the PCB.
The size of the segment table word STWSZ is
is less than 7. too
But if this is greater than 7, an illegal PCB exception is raised.
and if this is less than or equal to 7 then ASW1
is removed from the PCB (block 1438) and its
STWSZ field is tested to be less than 8 etc.
Deciding whether or not to eat (1439). If this file
If the code is greater than 8, an illegal PCB exception will occur.
But if that STWSZ field is equal to 8?
If it is less than this, the exception word EXW is retrieved.
(1440), that MBZ field is tested.
determines whether it is equal to 0 or not. If that MBZ
If the field is not equal to 0, it is an illegal PCN.
An exception is raised, but if it is equal to 0, the stack
SKT is removed (1442) and its MBZ feed is
is tested (1143) to see if it is equal to 0.
It is decided. If MBZ field is equal to 0
If not, an illegal PCB exception will occur, but if equal to 0
If so, the instruction counter word ICW is removed from the PCB.
It is taken out and placed in the instruction counter IC (144
4), whose TAG field is tested equal to 0
It is determined whether or not it is correct (1445). If TAG fu
If the yield is not equal to 0, then there is an illegal PCB exception.
arise. However, if the TAG field is equal to 0
If so, the MBZ word is retrieved (1446) and its
The MBZ field (bits 0-31) of
and is not equal to 0 (144
7). If this is not equal to 0 then it is an illegal PCB
An exception is raised, but if it is equal to 0, the stack
Base words 0, 1, 2 (SBW0, 1, 2) are
It is retrieved (1448). PCB base register
The contents of the 8-base register in the storage area are retrieved next.
is stored in the machine's base register 1308.
(1449). Next, the general register storage area of the PCB
The contents of the 16 general purpose registers from
is stored in the register 1307 (1450).
However, retrieving the contents of the scientific data register
Previously, the ability of process principal word 0 (PMW0)
The bytes are checked and scientific calculation mode is activated.
It is determined whether it will be used (1451). if
If scientific mode is used, the PCB
Scientific calculation register from scientific calculation register storage area
The contents of the data are retrieved and stored (1452).
Next, firmware progresses to the ability of PMW0.
Bytes are inspected and account mode is used.
(1453). If it's red
If mount mode is used (i.e. ability
Byte's account bit is set to binary 1.
), this account word is present on the PCB and
Day state time account word RTA updated
be done. Next, the firmware progresses to DEXT
Determine whether the number is set to 0 (14
54). If this is not set to 0
If the machine is in emulation mode (immediate
This indicates that the Decor expansion ability is being used.
Therefore, the DEXT number of PMW0 is checked (1
455) DETSZ file of process main word 3
Decide whether it is larger or smaller than the
Illegal if larger than DETSZ field
A PCB exception (1456) occurs. The reason is,
DEXT number is smaller than DETSZ field
is not equal to zero, and if so, the machine is
Implemented in law emulation mode and progressed to F
go Again at decision block 1454,
If the DEXT field is a binary 0, the
– The save mode is executed and the machine takes out the STW.
(1457). PCB remaining timeout warning
The RTO word is retrieved (1458) and CJP is executed.
Process time is limited by the time limit that can be spent in a row state.
is loaded. By this point, (a) the original process CJP is in the machine;
The new process NJP is different from the original process CJP.
New process NJP when given high priority
is "rolled in" to manage the CPU, or
(b) There is no CJP for CPU control and there is a queue in the ready state.
head was executed. Under condition (a), CJP
Pros in Q/PR/RDY taken out from RPW
Located in Sethlink PL, Q/PR/RDY
The process link PL's NJP is placed in the RPW and looks like this:
At this point, control is given to NJP, which becomes CJP, and the original
Position the two processes to remove control from CJP.
Switch the position to valid. Next, the NJP PCB is activated.
information necessary to run NJP (currently CJP).
information is in scratchpad memory or ACU register.
data array. Ready state if there is no CJP under CPU control
The head of the queue is executed, i.e. ready.
from the queue head to the process link PL
Take out NJP and put it in RPW word
Because of Patsutiya, NJP becomes CJP. To do this
Therefore, the process link PL is empty of Q/PR/RDY.
It will be left as is and it will be necessary to remove it. Therefore, starting at decision block 1461, the
The armware determines whether there is a CJP under the control of the CPU.
Determine if there is a free process link
(FPLS), this is accessed and
queued and this CJP is queued to this process resource.
written to the link. However, if the CPU is
If there is no CJP under your command, the state of NJP's PMW0 will be
The state byte is updated (1460) and sent to the machine again.
A determination is made whether the CJP is hot (146
3). If there is no CJP under CPU control, NJP
process link (formerly Q/PR/RDY)
(now under control of the machine) is Q/PR/RDY?
(1466) (i.e. Q/PR/RDY
(removed from queue), free link semaph
or FLSP, and at this time the free process link's
Free to be turned into a queue by Kyu (805 in Figure 9)
Become part of a process link queue (1466
a). The contents of the boundary address register BAR are retrieved.
Re (1464). System-based BAR+56
The executed process work of the deployed NJP (currently CJP)
The code RPW is updated by placing the NJP identification on the RPW.
(block 1465). empty display inday
The indicator is set to 0 if there is no CJP.
Ru. Then the contest indicator is set to 0.
(1467) and an address specification with typical contents.
The segment associator (first
AS132) in the figure is cleared (1471) and then
to enter the process mode (1470). (process
mode is more important than the operating system.
For example, by a process operated in a filter processor.
Indicates that the outside is handled. ) then FARMUE
continues until CAB (1480) and asynchronous trap
Bit AB is examined and set to binary 1.
(1481).
If the AB bit is set to binary 1
The process ring number PRN has been inspected
is greater than the asynchronous trap bit ARN or
Determine whether this is equal or not. (AB and
The ARN is placed in the priority byte of each process's PCB.
is set and is meaningful when the process is in the running state.
Yes, AB and ARN are system-based BAR+
Obtained from RPW placed on 56. ) RPW
AB and ARN in BAR+56 are asynchronous
Set the pbit or sync ring number first.
For an asynchronous trap routine that creates a condition for
is reset to proceed with step 1484.
Ru. If these are not reset,
Firmware allows you to smell the next pass.
It shows that there was an error when in reality there was no error.
For this reason, always synchronous trap routine 1
The process will proceed to 484 and will never be executed.
Next, return to decision blocks 1481 and 1482.
If the AB bit is not set or
Bit is set and PRN is not greater than ARN
If the firmware is progressing and processing equipment is
mode i.e. normal mode or emulation mode
Decide which mode to run. Therefore,
The DEXT number is checked and this is set to 0.
if it is set to 0.
If it is, the normal mode of the machine is executed (1
487). But if the DEXT number is set to 0
If not, emulation mode is running.
(1486) DESCRIPTION OF THE INVENTION A hardware/firmware system is a
Two basic records manipulated in the tutu operation
It recognizes the type of these two
The record of the type is stored in the virtual storage shown in Figure 15A.
location record and the database record shown in Figure 15B.
It is a record. Virtual storage records are generally
Addressing with segmented addresses
Contents of operating system procedures that can be performed
used. Database records are further divided into “regions”
Address the data using “one line per page” number.
used by user programs that specify this
Area refers to the user's file, and page refers to the user's file.
refers to the division in the user's data file,
A line number is a specific line number within the page of the file.
Refers to records. As shown in Figure 15A, the records in the virtual storage device are
It consists of the following fields. i.e. type
Field 1501 is a description of the recording type.
The record descriptor for this record (described below)
obtained from ). D switching of virtual storage recording
The fields describe the state of the record. This record is
The following conditions may exist. i.e. activity (this is a record)
means that it contains currently valid data. ) and
and soft delete (this is when data is no longer valid in the record).
, but it still occupies memory space.
It means to do something. ). length field 15
03 describes the actual number of bytes in the record.
Record 1504 contains the actual data of the record. point
The sequence field 1505 is for this recording body.
In some cases, this record may be used by either the owner or the member.
The next, previous, first, and last item in a given set.
and a pointer to the owner's record. recognized by hardware/firmware.
The second major type of record is described in Figure 15B.
This is a database record that looks like this. type fee
Field 1510 again describes the type of record, and below:
obtained from the record descriptor of the record written in
It can be done. Length field 1511 records in byte
Describe the length of. The recording body 1512 is the actual recording data.
Contains data. The pointer sequence 1513 is this
Points for recording the next, previous, etc. of the set
Including data. It is also recorded separately and described below.
D switch field 1604 for each record also
be. Furthermore, Figures 15C and 15D are of one record.
Describes the format of pointer sequences
(Fields 1505 and 15 in Figure 15A)
Field 1513 in Figure B). Hardware/File
Armwear system has two different pointers
- Sequence format, i.e. member records
The sequence in Figure 15C that is recognized for
Authentication and verification when a record becomes an owner record.
The format of Figure 15D, which is the recognized sequence
Recognize Tsuto. Member record (Figure 15C)
For, the next pointer field 1520 is
Include the addresses of the following members in the set:
nothing. Previous pointer 1521 is the predecessor of the current set.
Contains the member's address. owner point tough
Yield 1524 is the address of the owner of the set.
Including responses. For owner records, hardware
Pointers recognized by air/firmware
- The sequence format is shown in Figure 15D.
Ru. The first pointer field 1532 is
Contains the address of the first member record in the set.
The last pointer field 1533 is
Contains the address of the last member of the list. Each pointer described (next, previous, owner
, first and last) are optional. Of course
However, for a given set, the following combinations
only is legal. That is, Case 1 For owner or member records
The first, last, next, or previous pointer is
do not have. (Member records have owner pointers.
) Case 2 The owner record has the first pointer.
and the member record has the following pointer (mem.
Member records are retained even if they have an owner pointer.
(Optional). Case 3 Owner records are first and last pointers
and the member record has the following pointer
(Member records are held even if owner records are held.)
(Optional). Case 4 Owner records are first and last pointers
and the member records the next and previous points
(member records are owner pointers)
(may or may not have one). Other hardware/firmware systems
Properties can be divided into four different classes, or folios of pointers.
- This is Matsut's understanding. These clusters are not included in the record.
The space is used for virtual memory recording only.
Ru. For class zero and virtual memory recording only
Class 1 used and for database records only
Class 2 used for and database records
referred to as class 3 etc. used for
Ru. For all 4-pointer classes, their first
The two bits have a common meaning. first bit,
That is, the EOS bit is the end of set indicator.
It is. When this bit is set to 1, the point
By definition, the printer points to an owner record. Second
The NINS bit is the non-insert recording index.
It's good. This bit is set to 1
when the record is a member of the currently referenced set.
is not inserted. The class zero pointer format is shown in Figure 15E.
is shown. EOS bit 1540 and non-inserted bit
Bit 1541 occupies the first two bit positions.
SRA field 1542 is a 14-bit offset
, which points to the record placed in said segment.
is the displacement within a given segment.
SRA file obtained from pointer of class zero
The code points to the address of the record via the class zero pointer.
generally obtained from the base register used for
Always combined with segment number. A class 1 pointer is shown in Figure 15F.
EOS bit 1550 and non-insert bit 155
1 is the standard definition. Field SEG, SRA
1552 is defined by SEG and SRA as previously defined.
from standard segmented addresses.
Ru. These pointers can be segmented via pointers.
Address records directly by supplying the reference number directly.
used to define Class 2 used with database records and
For class 3 pointers, firmware/hardware
As mentioned above, the hardware system is
(See Figure 202) Each base register of the system
Promise that there is an index register associated with
recognize. General-purpose register 8-15 (201)
They correspond to index registers 0 to 7, respectively.
This index register number IXR ₁ is base level
Jista BR ₁ It makes me match. For example, the base
register BR ₃ For index register
IXR ₃ (GR ₁₁ ) is the area-consistent line number pointer (first
5H)), and its current
SEG, SRA address is base register BR ₃ included in
It can be done. In this way, users can access SEG and SRA addresses.
base register or index register with
The area-consistent single-line format data included in the register.
his records via any of the database pointers.
Address can be specified. Hardware that operates on database records
The A/F firmware command is a region-consistent single-line pointer.
Automatically convert from data to SEG, SRA address
Realize your abilities. For this reason, database commands
All real memory references made are standard hard
using a wear mechanism, this mechanism can be
Indexing performed automatically by hardware
Changes from an area-consistent line such as that contained in the
memory by segment and SRA number by
address. One page in the user file (area)
and recognized by the hardware/firmware.
There is a temporary one-to-one relationship between each segment.
A correspondence is made. In this way, it is described below.
hardware via a page decryptor mechanism
A/F Armware is which given page number
is also converted to a segment number. The class 2 pointer format is shown in Figure 15G.
shown. EOS and non-inserted bits are field 1
560 and 1561. The page number is
field 1562. line number is field
1563, in one page and area.
Represents the record number. Area-consistent line number pointer
The whole is supposed to be referenced by a database instruction.
Get the area number obtained from the index register.
obtained when using class 2 records by
Ru. The class 3 pointer format is shown in Figure 15H.
shown. EOS and non-inserted bits are field 1
570 and 1571. The area number is fee
1572. This is the user file
Browse numbers. Page number 1573 and line number 1
574 accesses a specific record in the user file.
Specify the dress. Figure 16A shows the database page, which
is determined by the hardware/firmware system.
A part of the user file (area) that is recognized.
be. The database page is already marked in Figure 15B.
Contains database records as described. already mentioned
As in, database pages reside in main memory.
1 between the database page and the segment
A one-to-one correspondence is made. Page header 1601 is the page containing this page header.
Contains certain circumstances regarding the. For example, this page
The header is the length of the page in bytes and the length of the page in bytes.
Describe the number of records (rows) included in the page. or,
This includes information such as write bits, and this
If the main memory contains the page,
It is set at the same time as writing to this register. page
After the header, the next main page of the database page
The important part is the row offset array 1602. this
is a 16-bit element array with a 1:1 ratio of pages.
Corresponds to the number of valid rows for. row offset array
For each element, a 2-bit D switch 16
04 and a 14-bit offset 1603. D
Switches are used to prevent recording inoperation, logical deletion, and physical deletion.
Describe the state of removal or operation. The offset is
to the record which is the relative displacement from the starting position of the page
This is a 14-bit pointer to The hardware is
Concatenated with the segment number corresponding to this page.
to this page by using the offset
addressability of database records.
I understand that How to get the corresponding segment number
The law is described below. What's left of the database?
The following portions are shown in records 1610 and 1612.
It consists of real database records such as these records
can be placed anywhere on the page (segment).
and not necessarily their position in the row offset array.
It won't be in the same order. If the D switch
Describes recording status that is inoperable or physically deleted
, the offset is set to zero and the record is
not exist. The real database page is shown in Figure 16B.
Addressed by a page descriptor such as
It can be done. Segment number of this page descriptor
No. 1625 indicates that it was loaded into main memory.
After this page contains the corresponding segment number.
Area number 1622 is the area number (face number) of this page.
). Page number 1624 is the actual page
page number. Last page indicator 16
26 is the highest page number in the given area
is equal to 1. The shift counter 1623 is
Contains the number of bits in the page number. Hardware/Future
The firmware system uses a single line pointer throughout the area.
When using automatic format, variable length page numbers can be used.
recognize. The “next” descriptor 1620 is
next page in a series of page descriptors
Used for descriptor instructions. "Previous" de
The scripter 1621 is a page scripter.
Points to the previous descriptor in the ane.
Using these page descriptor chains
This is described below. This page scripter chain
isle page is currently the main computer system
used to indicate whether it is located in memory.
This is hardware/firmware. memory
For each page that exists in
Cryptor is a chain that recognizes a single system.
and this chain is integrated as shown in Figure 16C.
Directed by the access control (IAC) pointer
Ru. This unified access control pointer is
Represents a one-word extension to the system base. IAC
The pointer is placed at address BAR+92 and this
The address is one word at the end of the system base.
It's past. IAC pointer format
field 1630, which must be zero,
Contains G number 1631 and displacement 1632.
Ru. This G number is the number of the G segment as described above.
It is. This displacement is the page descriptor's
at the displacement within said G segment where the start begins.
be. All pages of pages contained in main memory
The day scripter then replaces the traditional chain form.
Linked together in Matsuto. next day
Cryptafield and previous Descriptor Fee
form this link. Figure 17 shows page data in main memory.
Hardware to realize base page positioning
Figure 3 shows a flowchart for air/firmware.
This firmware has area one page one line number point
The page is first stored in main memory.
is used to determine whether the
If this is found to be in main memory
delivers the page descriptor for that page.
It is used to This firmware is 1
701. The first firmware operation is shown at 1702.
In this case, the main memory extraction IAC
The pointer is formed at the location of BAR+92
Ru. (The IAC pointer is the system base shown in Figure 6.
). The result of this memory retrieval is
As a result, memory access exception 1703 occurs.
obtain. An example of a memory access exception is physical memory
- or memory read error. Farm
The next step caused by the wear is the MBZ frame.
1704 shows that the yield is zero.
be done. (See Figure 16C) If this field
If it is found that is not zero, system check 17
05 happens. This occurs at the same time that the system check occurs.
The system enters diagnostic state. If the MBZ field is zero, step 17
06 is executed next. G from IAC field
The number is transferred to temporary register G. Displacement
The yield is also transferred to temporary register D.
This displacement is also referred to as the “first class”
It is also transferred to the computer's scratchpad memory.
Ru. Step 1707 is executed next. Main memo
Retrieval of the page is performed at addresses G and D.
Take out the descriptor (see Figure 16B). child
To take out the G and D addresses, as mentioned above,
This is done in batches. G, D access exception 170
8 indicates this memory retrieval (e.g. segment, illegal
G-D segment descriptor)
It can be done. Next, step 1709 is the firmware
Executed by a. firm wear sa louche
Area number of area consistent single line number checked by
and page numbers are page discs for matching.
Lipta area number field 1622 and page number
No. field 1624. Moshiko
If the area and page number match, the step
Step 1720 is executed, in this case firmware
The routine executes a valid page retrieved from main memory.
Scratch pad memory
Load and exit. If the current page descriptor area or
The area where the page number is checked per page per line pointer area
area and page number, the step
1711 is executed. Current page day of the page
Scripter's "next" descriptor field
1620 is temporary scratch patch location
It is checked against the contents of the "first pointer".
If these two numbers are not equal, the step
Step 1713 is executed, in this case temporary register
D is the "next" date of the current page descriptor
Loaded by Crypter Field. Ste
Following step 1713, firmware version
Lunch is a new page descriptor (``Next
)
is then removed and subsequently inspected in step 1.
707. Again in step 1711, if the "next"
The descriptor is temporarily the "first pointer"
If it is equal to the contents of the written location, then this
describes all pages present in memory
All rings of the page descriptor to be
View a page of areas being explored by armwear
Indicates that the event was completed without any release. In this case, pagination
An exception has occurred (1712) and the desired page is
Indicates that it is not located in Molly. Following this execution
Appropriate software operations are performed to achieve this desired
Causes the actual movement of the page into main memory. Hardware/firmware described in the text
Two more important elements of A are Figures 18A and 18B.
is shown. Set descriptor (18th A)
) is used to describe the properties of a given set.
Ru. As shown in FIG. 18A, P field 1
802 indicates the record pointer in this set.
A 2-bit file describing the interclass (mode)
It is a yield. All of the owner and member's partners
all records are at the same point for a given set.
It has a pointer to the class. Set disk
The owner pointer field of Puta 1803 is
If the member record is the owner of the owner record
- If it contains a pointer, it is set to 1 (the first
(See Figure 15C). Other pointer fields 18
04 is the first point for owners and members
, last pointer, next pointer, and previous pointer.
Describes whether it has a pointer. Set edition
The configuration mode field K1805 displays the current set
describes the mode of set organization used for
Ru. Only the ring set mode is detailed in the main text.
described. However, table array or list array
The ability to extend to other modes of set organization such as
have Displacement field 180
6 is the point of the record from the start of the record in memory.
Indicates the offset to the start of the intersequence.
used for (Figures 15A and 15B
reference). SET DAY AS DESCRIBED IN FIG. 18A
The scripter always uses hardware/firmware.
In order to supply a description of the reference set to a
When performing calculations on a
be accessed. The recording descriptor as shown in FIG. 18B is
Used to describe certain characteristics of record. F-Fui
Field 1820 is used to describe the recording format.
be done. The recording format is 15A and
Virtual memory recording and data storage as described in Figure 15B.
database record. Record type
field 1821 indicates the type of record, and finally
Memory as shown in Figures 15A and 15B
is loaded into the type field of the actual record. Record
The record length field 1822 is the main memory of the record.
15A and 15
It is loaded into the main memory record as shown in Figure B. The actual database instructions are shown in Figures 19A to 19F.
This is one of six formats as shown. The GROP format shown in Figure 19A is
Code 1910, file must be zero
code 1911, base register number 1912, and
and complement code 1912. base register
The star contains segmented addresses of records.
I'm here. The complement code is described by the arithmetic code.
used for further discrimination of specific commands
Ru. The XI format shown in Figure 19B is
Arithmetic code 1920, to further differentiate the arithmetic code
Complement code 1921, address syllabary used for
Bull 1922, field that must be zero
1923, logical delete field 1924, point
Intermode field 1925, and BR field
Includes a yield of 1926. base register
contains the segmented address of the record. a
Dress syllable 1922 is used in a certain way.
The set descriptor of the set to be treated as
(Fig. 18A). address syllable
is segmented by the address generation rules described above.
Expands to a commentized address. The DXDX format shown in Figure 19C is
Code 1930, used to further differentiate the instruction.
complement code 1931, one address syllable
AS1 1932, MBZ1 frame that must be zero
Yield 1933, Base Register 1934, No.
MBZ2 field, which must be 2 zeros,
and second address syllable AS2 from 1936
Become. Base register again segmented recording
Contains the address given. first address syllable
AS1 1932 specifies the set descriptor.
Ru. The second address syllable AS2 1936 is 2
Used for addressing base integers. The BRX format shown in Figure 19D is
Opcode 1940, used to further differentiate the instruction.
Type Field 1941, Bass Regis
Toughfield 1942 and Address Syllable
Contains 1943. The base register is
Contains segmented addresses. ad
The resyllable is the address of the set descriptor.
used for designation. The DXGR format shown in Figure 19E is
Code 1950, used to further differentiate instructions.
type field 1951, first base register
Star number BR1 1952, address syllable 19
53, MBZ1 field 1 which must be zero
954, second base register number BR2 195
5, Front-Back-First-Last Field 1956, O
and the second zero MBZ2 file
Contains code 1957. 2 base registers
is the address of two different records placed in memory.
Used to specify responses. address syllable is set
Used for addressing descriptors. Previous-
The after-first-last fields indicate the location of the record within the set.
Describe the desired settings. The OPDD format shown in Figure 19F is
Code 1960, description of specific database operations
Primitive field used in 1961, life
Type field used to further differentiate orders
1962, used to describe pointer fields
P Field 1963, and owners and men.
First - last - describing other pointers of bar records
next-previous pointer field 1965, pointer
– Describes the offset relative to the start of the sequence.
displacement field 1966, and base register
Contains the BR field 1967 containing the number of
There is. The base register is a segment of main memory records.
Contains a commented address. Direct database discovery command is firmware/
A hardware instruction, this is a database point
to an equivalent segmented address and then
add this segmented address to the base register
Load. Class 2 or class 3 typepoi
For records that are part of a set by a
The generated pointer is also stored in the index register.
is also loaded. The direct discovery command is shown in Figure 19B.
It is in XI format. firmware flow for direct discovery commands
The yard is shown in Figures 20A-20E. this
For the firmware, the MBZ field in the command is
Step 2002 (19th
(see figure B). If this field is zero
If not, an illegal format exception will occur (2
003). Otherwise, in step 2004,
P field 19 to determine the recording format.
25 (pointer class) checks are performed. nine
Class 0 or class 1 pointer (virtual memory
Step 2050 (20th D)
A branch to (Figure) is performed. Class 2 or class 3 pointer (database
step 2005 is executed for
It can be done. In this step, address
4 bytes at the location indicated by
The pointer retrieval operation is performed. This extraction
As a result of the operation, a memory access exception 2006 occurs.
can occur. Otherwise, the pointer is called "X".
Temporary scratch patch location revealed
be done. This retrieved pointer is
It is in the form of rows (see Figure 15H). execution
The next step to be taken is shown in 2007, but this
Here, the pointer area per page and line number is the page memo.
is checked to see if it is present in the
Ru. This check is performed to determine the page position shown in Figure 17.
This is done by firmware in the female routine.
If the page is not in memory,
processing exception 2008 occurs. Otherwise, step 2009 is executed;
In this case, the scratch patch location “X”
The line number from the pointer in the arithmetic logic unit
Temporary 16 base register located in port 1317
It is transferred to W (see Figure 13A). This point
The actual number of bits found in the row number of the page
Descriptor shift count 16
23. The page is as shown in Figure 17.
The scripter is a page layout firmware.
Fetched from main memory as part of a subroutine
(For details on page descriptor description, see
(See Figure 16B). The next step to be executed is 2
010, in which case the total number of rows on the page
The number is taken from the page header (see Figure 16A).
(see field 1601). In step 2011, the line number W is checked.
and this is less than the maximum number of rows on the page.
or something equivalent. If this is true
If not, invalid page format exception 201
2 occurs. Otherwise, branch 20B
This is done at 2020 in the figure. next step to be executed
2021, in this case the row offset of the page
The (W+1)th element of the array is retrieved. this
The extraction operation is the number of bits given by 16 x W
The address of the start of the row array indexed by
This is done by specifying the location. Memory access exception 2
022 can result from this memory fetch operation.
Ru. The next step to be executed is 2023, which is
The conjoint offset array (see Figure 16A) is
The record described by No. W has not been assigned.
It will be inspected to see if it is (inoperable). Moshiko
unused row exception 2 if the row is in an inactive state.
024 occurs. Otherwise, described by line W
whether the recorded records have been physically deleted;
Tests will be conducted to see if this is the case. If this is true
If so, a deleted row exception 2026 occurs. difference
If not, 2027 checks are performed and row W is
The records written by the user are logically deleted.
Find out if there is one. If this doesn't work, bra
2033, otherwise the command
logical delete bit 1924 is equal to zero?
An inspection (2028) will be conducted to find out whether
(See Figure 19B). If this bit is set to zero,
If so, a deleted row exception 2029 occurs.
Otherwise, the status register (Figure 2, file
The condition code of code 207) is set to 1, and the
2040. The purpose of the logical delete bit in an instruction is to
is no longer active in memory, but still
physically occupy main memory space as
Allowing the programmer to detect errors.
Ru. "Garbage Collection"
The process removes inactive records from memory.
Compress activity records to greatly simplify the removal of these records.
Do it efficiently. In this way, direct discovery orders are
command the garbage collection routine.
The use of setting the logical delete bit in
Logically delete the
Provides the ability to detect deleted records. In step 2033, the
Proceedings will continue. Status register condition code is zero
The branch is set to 2040.
In this step, row W is segmented.
The address that was created is the segment address from the page descriptor.
Take the client number 1625 and enter it in step 202.
Offset 1 obtained from row offset array element of 1
It is generated by concatenating with 603. This center
A segmented address is an arithmetic logic unit.
Temporary 32-bit register located at 1317
The data is loaded into the computer Y. In step 2042
, this temporary register Y is the instruction format
Described by the base register BR1926 from
transferred to the specified base register. This base level
The register is located in the address control unit 1319.
be done. In step 2043, the step
The pointer introduced in 2005 is an instruction
Index of number BR obtained from format
loaded into the register. In this way, index
base register (IXR) and base register (BR)
are the area per page per line pointer and segment respectively
step 2040
is executed to complete. Regarding the record indicated by pointer "X"
P field 19 in the instruction format
25 directs recording of virtual memory type.
branch to 2050 in Figure 20D.
will be held. In this case, the 4-byte pointer is
given by the address syllable of the instruction format.
retrieved at the address given. This point
The printer is a segmented address (Figure 15F).
) in the form of a scratchpad memory location.
- loaded into section “X”. This memory
As a result, memory access exception 2052 is generated.
It can be done. In step 2053, the location
Record pointed to by recorded pointer "X"
D switch 1502 is removed (Fig. 15A).
reference). As a result of this memory retrieval, the memory
Access exceptions may occur. Step 2053 Smell
checks for the soft-deleted status of records.
is done. If this state did not exist, the branch would
It will take place in 2060. If this condition exists, it can lead to death.
Checks for logically deleted bits in the command.
This is done at 2054. If this bit is zero
If set to , deletion record exception 2055 will occur.
arise. Otherwise, step 2056 executes
In this case, the condition code in the status register is set to 1.
branch is taken at 2070. too
However, the record was not found in the logical delete check step of 2053.
– then it must be active and the branch
is performed at 2060. See Figure 20E. Step 2060 advances to step 2061.
In step 2061, the condition of the status register is
The code is set to zero. Then branch 2
It will be held at 070. Step 2070 is a step
Go to 2071 and scratch patch location
The pointer stored in X is the field of the instruction.
to the base register indicated by BR1926.
loaded. (Figure 19b) Then the command completes
do. One embodiment of the present invention will be shown and described.
However, as will be apparent to those skilled in the art, many changes and modifications may be made.
Variations are possible in the practice of the invention and
It is within the scope of the gist of the clarification. In this way, many steps
This method provides the same result and does not cover the gist of the invention.
modified and replaced by other steps within the range of
You get it. Therefore, the present invention is
Should be limited only to the extent specified by the scope
It is something. Definition of the term ``absolute address'' A hardware byte address in the main memory device.
Physical Address "Address Generation" Refers to a location in the main memory device.
A large number to calculate the absolute address used to
A hardware machine that operates on address elements of
Function ``addressing'' Any of a number of virtual, logical and physical means.
``Address space'' refers to the absolute address of the CPU during the execution of a process.
corresponds to the above process that is allowed to be converted into
A set of logically segmented addresses called an ``address space word.'' A process control that directs the segment table word arrangement.
One or two words in the control block. this
The segment table word array contains the segments associated with the
Specify a statement table. "Address syllable" A logical address recognized by CPU hardware.
An ``analyzer/translator'' that is an operand of an instruction, and that first passes the control language flow through the linker.
Next, if there are no errors in the control language, the
The iser/translator uses static link
Convert to tables and other structures for cars. "Asynchronous processing" Simultaneous operation of one or more processes "Auxiliary memory" 64 files for storing various system states
A “base register” consisting of a lip-flop and placed in the ALU is referenced by the value in each address syllable.
``Boundary address register'' is the primary element in addressing the segment that is to be accessed by firmware/software.
directly readable to define the lowest memory address
Hardware register "call""inwardcall""outwardcall"
``Central processing unit (CPU)'' Includes circuits that control interrupts and execution of instructions.
A part of a computer ``channel'' Process subsystems and peripheral device subsystems
A means of communicating between systems, both physical and logical.
There are two types of channels. The physical channel is
I/O control unit ICO and peripheral device control unit
Logical channel with hardware connection between PCUs
A software module between main memory and a single peripheral device.
``Channel command entry'' which is an air communication path. ``Channel command word'' which is an instruction in a channel program. An element of a channel command entry. two
The channel command word is a single command
"Channel program" that configures the
An auxiliary code is a sequence of instructions that is executed by an operation code.
``Compilation unit (CD)'' code in an instruction A code for a procedure in any high-level language processor
obtained from compilation or assembly
Single target code. CU can be executed until linked
Not capable. ``Concurrency'' Explicit concurrency ``Condition field'' 4-bit field in branch instruction. centre
Each bit of yield corresponds to status register bits 0 and 1.
Corresponds to the condition code setting in . “Contest Indicator” is a hardware structure located in auxiliary memory.
A new entry is placed in the ready queue,
``Data address space'' indicating that priority conflicts may occur.
A set of four accessible logical recording addresses.
elements, i.e. logical fields, logical records, data
Consists of base pages and files. "Data descriptor" Describes data operations in indirect addressing.
``Decor'' is an information structure used as a functional characteristic or structure of a computer system ``Decor extension mode''
"Descriptor" calculation mode that allows calculations Generates the address of any data field
32 or 64 bit field used in some cases. Book
Many pointers in inventive addressing operations
One of the. "Descriptor block" Many data blocks except semaphore descriptor
The data block that contains the declaration of the crypter
data is not allowed. “Equipment Adapter” Adapts a specific device to a peripheral control device.
"Device Adapter Interface" is an electronic device that can be used to control device adapters and their related peripheral device control devices.
``Equipment control unit'' is the interface between the
Responsive firmware ``Dispatching'' Instruction file that provides relative position information within a segment
Fields or data disks in Omatsu
``Displacement Addressing'' base or current location of the immediate segment
Operate the location for any of the counters
``Dynamic addressing'' is a form of direct addressing defined by commands that obtain results within a group of processes during execution.
Addressing “editor” Information obtained from ring operations of a specific procedure
static files that format and print all or any
``Effective address'' part of the static linker For the physical address, the segment table number,
Segment table entries and segment relative
A logical address consisting of physical addresses. These key points
The element is a specific segment that ultimately points to the referenced segment.
The path to the segment descriptor is shown below. "Emulation mode" Starts up another computer and
Computer operations that appear to operate in the environment. “Exceptions” Exceptions are defined as requiring special treatment.
When the hardware detects the existence of a certain condition,
“event” that a process has value for some other process.
Everything found in the system by a field class is a different record in the same record class.
Similar fees used to remember the same characteristics
Set the field value. For example, within the employee record class
All field values for age. “Field value” represents the value of a tangible characteristic represented by a record.
An element of data associated with a wasted record. This value is
Translate as character string, number, boolean or value
with some data that can or indirectly leads to that value.
It is expressed as ``Farmware'' uses a form of microprogrammed control.
"GD name" is the part of the hardware unit organization that
Name used. G or G segment name is
Entries in G table containing segment descriptors
Re number. D is the relative ad in that segment
response. “G-segment” Address can be specified using GD name format, and related
Segment containing semaphore which is related equipment (G table)
ment "G table" When the GD name form is used, the memory pine pin
``Gating'' table used for ``Gating'' (heading of G segment).
Entry for the procedure in the segment
``General-purpose register'' equipment that controls the general storage of binary numbers, that is, bit string data.
32-bit record available to the running process
Jista. Some general-purpose registers are used for indexing.
It is possible to use it (GR8 to GR15). “Index” A data structure maintained and calculated by the system.
Construction. This structure is identified to the user only in key form.
This key allows the user to access specific recording occurrences.
provided to enable and position this
It can be done. ``Indexing'' Adding something to another adds a sign.
"Index register" is a general-purpose register used for indexing.
(GR8 to DR15). "indirection" An addressing method that allows an address to be
to get another address instead of the real data. "Indirection to Base" Data disk containing base register number and displacement
crypter is found at the referenced address
``Indirection to a segment'' A form of indirection that allows you to segment a segment.
Reference the data descriptor containing the ment address.
"Indirect segment descriptor" found at the referenced address A segment descriptor different from the segment
segment data containing information for addressing
A form of scripter. “Instruction” A central processing unit visible to the programmer.
``Instruction counter'' is the execution unit of the
The register associated with the running process containing the address
``Interleave'' Memory to reduce memory access time
Successive module access “interrupt” A process in the system due to the occurrence of a certain event
Interruption of an “interrupt process” A process that is activated in response to an interrupt operation.
Process “Inward Call” Call for execution of one procedure at one ring number.
Separate procedures for execution at the actual downward link number
Call "I/O controller" Base control for special I/O subsystems
Device that performs control ``I/O processor'' Peripheral storage device, that is, I/O device and main storage device
A potentially asynchronous system that primarily deals with the movement of data between
"JP table" Logical address for heading of process control block
``Job'' is a system work unit ``Job Control Language (JCL)'' is a language for describing jobs and their constituent parts ``Job Steps'' is a program defined by JCL statements.
The main subdivisions of a job that stop at the execution of the process ``Job step table'' Mapping or printing of the first part of the process name.
System table "Linked Modules" used to find the process group table. Output of the static linker. Cross references are static linkers
Compilation unit solved by
(CU) collection group ``linking'' Stationary linking term reference ``logical channel'' Channel term reference ``logical processor'' Hardware resources and
Collection of control information ``Main memory'' Instructions can be executed or data can be directly read from now on.
all addressable registers that can be loaded into registers.
Storage device ``Magnetic tape controller'' A peripheral subsystem related to a magnetic tape device.
Elements "Mass storage device controller" Peripheral device subsystem related to mass storage devices
Elements of “Members” The role played by records in relation to the generation of sets.
Discount. The current status of your membership record is set in
What is inserted or not inserted?
It is. "Memory Management" Physical memory allocation, relocation, and allocation
The operating system equipment "message" for release from a source that is not a file or the final result
Microinstruction words, control storage words, and microinstruction words.
The same "microprogram" used to implement the control functions of the processor
"Multiplex" is a set of machine codes, usually time-sharing hardware such as memory.
Division of resources ``Multiprogramming'' Two or more programs on a single computer
Simultaneous execution of systems in ``native mode'' Computer operations in a native environment ``offset'' In address generation, the address of a segment is
After the start of the segment where the specified part starts
Number of bytes "operating system" to ensure valid operation of the user's software
Basic software system "Outward Call" designed for
call another procedure for execution at the ring number of
``Owner'' The role a record plays in relation to a set. Setsu
There is a record of the occurrence of incidents along with the role of the owner.
Exists for a lifetime. ``Peripheral device control unit'' A channel program that performs input/output operations.
Independent microprogrammed processes that run
sa. “Peripheral subsystem interface” Free peripheral device control unit and I/O control unit
Standard used to transfer and control between
``Physical channel'' Refer to channel section ``Physical data structure'' Structure of data when physically recorded on a medium
Complete Definition of “Physical I/O” Transfer of data between memory and peripheral or end equipment
The operating system that initiates and controls the transfer
``Physical storage device'' is the hardware used to store data.
Various types of recording media and recording/reading hardware
Consists of state. "P operation" Entry to standby state or receive message
A "pointer" is a machine instruction that contains a semaphore for a process to perform. A pointer is used to uniquely identify an entry in an information structure.
Information elements used. The content of the pointer is a unique symbol
The actual entry in an address space is
address. "Pointer Database" A computer's normal addressing space and
Points whose contents are based on different address spaces
Ta. Generally, database pointers are
address space larger than the address the air has.
Consolidate memory that is currently unused.
A form of indirection that alleviates the problem of
I do. "segment in a pointer" whose contents are a partial segment of the entity addressed
A pointer that is a virtual memory address. virtual mail
Segments with insufficient memory addresses are
Same as the segment part of the segment pointer
Therefore, it can be known implicitly. "virtual memory pointer" whose contents are the virtual memory pointers of the addressed entity.
A pointer that is a memory address ``priority instruction'' An instruction ``procedure'' that must be executed in ring 0 A name that can be executed by a non-concurrency processor
software functions, i.e. algorithms
(algorithm), which is the format
, Gobol program, PL/1 internal procedures, etc.
be. "Call procedure" Creates a stack frame inside the stack segment.
``Procedure descriptor'' mechanism for opening procedure location and entry pointer
The word "segment of a procedure" whose content represents a procedure or a part of a procedure
Segment type "process"
Sequential execution of instructions "process address space"
A ``process control block'' is a memory address that can be transferred at any time to define the state of a process.
Data containing the required information (defined and recognizable)
(Hardware) “Process Group” Usually the processes required to perform a single job step.
``Process Group Builder'' is a related set of processes whose behavior produces linked modules.
``Process group loader'' is the part of the linker that executes the final solution in the linked module.
spawns a set of executable processes, then
load a set of programs into memory and begin their execution
Operating system equipment "Process group table" See P table section "Process link" Go to ready state process or standby process queue
Entry "Process state" Displays the dynamic state of the CPU process, e.g.
``process switch'' disconnects one process from the central processing unit and transfers it to another
``Process synchronization'' is a hardware function related to devices.
Functions to do. Generally these functions are
and PV operations. ``Processor'' receives data, processes it, gives a result,
The sequence of operations in response to a memorized program
A unit that can control kens, in a narrow sense.
is a central processing unit, broadly defined as a central processing unit, peripheral equipment.
equipment, or hardware/software processing
means a mechanical device. “Program” The procedures and relationships necessary to solve a certain problem.
related information to specifications, i.e. executed by a computer.
calculates the user's job or
an ordered instruction that performs a phase of a job
collection. ``Program execution'' Process operation according to program specifications ``Protection'' Enhanced by hardware and software
processes that interfere with each other or
Mutual address space is shared in such a way that
``P table'' function to prevent process control block
A hardware-defined data structure containing entries.
Construction. A P table entry always identifies a process group.
Indicates the complete set of PCBs included. Also, process group
Also called table. “Q/PR/RDY” A queue of a process in a ready state.
Queue: Order of entities waiting for information, processes, or availability
Ordered list "Ready state" There is no associated processor, but all but the processor
all necessary resources are available for the change to the running state.
A “record” of the state of a process A piece of data that represents an object in the real world
Basic. For example, "personnel" records indicating employees, customers
``Customer'' records indicating purchases, ``Purchase Order'' records indicating purchases.
Record. “Record Class” Define each record to allow only one record class
A set of similar records. For example, for all personnel
Records, records of all customers, records of all purchase orders, etc. “Record Descriptor” Used in the creation, recognition, and destruction of record structures.
Structure of information used. Single recording descriptor
Concerning the record class of. ``Relative address'' Increase or decrease location of one object relative to another ``Relocation'' From one location in main memory to the next
Contains all necessary reference adjustments for the previous location.
``return'' moving a segment to another location where one procedure returns the point at which it entered another procedure.
necessary to repeat the action of the procedure at the immediately following point.
Required Functions and Operations “Ring” Reading of process calls to a segment
Segments that restrict egress, writing, and execution
Protected attribute ``roll-in'' Control of a processor for a new process
``Rollout'' Performing the operations necessary to perform a process Stopping control of a processor by a process
``Execution state'' is the execution of the calculations necessary for the
``scratchpad memory'' CPU control also known as local storage unit
256 locations in ALU for storing information
``Scheduling'' Determining the sequence of operations ``Scientific operation registers'' 64-bit registers used for binary floating-point number operations
Tsuto register. When the system is for scientific operations
In the present invention, there are four registers for scientific operations.
Ru. “Segment” Adjacent main memory that is treated as one unit
PACE "Segmentation" Segmentation instead of a single linear storage in main memory
``Segment-based'' division into logical groupings called segments.The current origin of the segment. This is the segment data
of each field in one word of the descriptor.
One "segment descriptor" to the segment table that defines the characteristics of the segment.
entry, i.e. the segment descriptor finger
``Segmented Address'' See section ``Effective Addresses'' ``Segment Number'' Segment Table Number (Segmented Address)
A specific segment consisting of one of the
and the segment table entries for the selected table.
During generation of another "segment relative address" address, to obtain the absolute address
The final number added to the segment base ``segment table'' Address designation for that segment in the process
Segment day used to ensure constant capacity
Table containing scripters. a segment of a process
The collection of tables is the address space for said process.
Define the "Segment table entry" An item in the segment table. Each segment table entry is a segment disk
It is Lipta. "Segment table word" A segment table word that indicates the segment table of a process.
Entry to the entry table word array. This array is
Two address spaces within the process control block
one of the keywords. "Semaphore" Used to control communication between each process
Data structure "semaphore block" A data structure containing only the declaration of a semaphore descriptor.
Data Block “Set” Collection of one or more records. The definition of this set is
Has one “owner” record with zero, one or more
has a "member" record. 1 set is the order
It is attached and has the following meaning. That is, "first member", "last member", "next member", "previous member", "set class" A set class is a set based on the rules for:
It is a collection with a name. That is, the role of sets, the selection of set occurrences, the ordering of sets, and a set being a member of only one set class.
- is. One record is the only one in one set class.
can be one member of one set. “Set Descriptor” Initial settings, insertion, search, etc. related to the set structure.
Information structures used in calling and removing. 1 set
A descriptor pertains to a single set class. "Stack" Accepting and storing data using a last-in, first-out method
and a mechanism for permitting searches. stack frame
It consists of a number of adjacent parts called . "Stack operation area" Storage area, caller's instruction counter, parameter
Dataspace and local variables – in short, calls
the current frame that is most useful for executing the specified procedure
The current star holding a pointer to the data in
``Stack base word'' part of the stack frame.
Stack for associated rings 0, 1 and 2
Contains the segmented address of the segment.
A group of three words called a "stack frame" Data stored for a single procedure call
Adjacent portions of a stack segment that hold ``stack operations'' Information about and from the stack
Pushdown and popup of memory and retrieval
Tup operation. In fact, the information stored in the stack
Manipulation of pointers used for referencing. "Stack overflow" Used to store more information on the stack
An action that the possible space cannot hold. This is hard
detected by software. "Stack register" See section on T register "Stack segment" Segment of the process that includes the stack "Static linking" Compilation of source procedure and target of said procedure
An intermediate step between the execution of the form. linking
resolves external references made to said procedure.
“Status register” to resolve: 8 bits that specify the status of the currently executing procedure.
``swapping'' registers by writing segments to secondary storage.
of the main memory space occupied by the
Cancellation. Actual writing to secondary storage is performed by
If the segment was read last, then
Can be suppressed if unchanged. “Synchronization” Two or more programs that have a fixed relationship in time
Synchronous execution of processes. "System-based" Acts as the backbone for all information structures
A fixed area in main memory called a “task” A user-defined task consisting of only one stream of asynchronous instructions.
The first segment of the procedure stack is the T register.
The hardware address visible to the software, including the
Wear register "unit recording control device" for card devices, paper tape devices, and printing devices.
Peripheral subsystems associated with a single recording device such as
``User process group'' is a system element that exists independently of any job.
Internal display of any job step other than the process group ``Blank indicator''.
In other words, there is no hardware in the CPU that indicates that there is no CJP.
A structure located in the auxiliary register of the ALU. "Virtual memory" Programmers can use virtual memory regardless of the size of physical memory.
An addressing concept that lets you encode
The virtual memory management device automatically divides the main memory and
Manages the exchange of segments to and from the next storage device.
Ru. "V operation" For sending signals between processes for the completion of a certain event
Intended machine instructions. This V operation is
Compute on mafia. Abbreviation system ACU: Address control unit ALU: Arithmetic/logic unit AS: Address syllable ASW: Address space word BAR: Boundary address register BCD: Binary coded decimal number BR: Base register CCE: Channel command entry CCU: Channel control unit CMRN: Call Side maximum ring number CCW: Channel command word CET: Current state entry time CIA: Control storage interface adapter CJP: Currently running process CPU: Central processing unit CU: Compilation unit CSU: Control storage unit D: Displacement DMU : Data management unit DA : Equipment adapter EAR : Effective address ring EXW : Exception word GR : General purpose register GTW : G table word IC : Instruction counter IFU : Instruction fetch unit I/O : Input/output IOC : Input/output control unit IPQW : Internal Process keyword IR: Index register ITBB: Indirection to base register ITS: Indirection to segment J: Job JCL: Job control language JTW: J table word LCT: Logical channel table LIFO: Last in, first out LSU: Local storage memory or scratch
Padded memory MBZ: Must be zero MOS: Metal oxide film semiconductor MAXR: Maximum ring number at which the procedure can be executed.
MAXR is SEG EP segment disk
Found in Lipta. MSC: Mass storage controller MTC: Magnetic tape controller NFS: Non-functional state NPRN: New process ring number NJP: New process that replaces the currently running process
Process PCB: Process control block PCT: Physical channel table PCU: Peripheral control unit PL/1: Programming language/1 PMW: Process main word Q/PR/RDY: Ready process queue RD: Read ring RHU: Reserved for hardware use
RPW: Execution process word RSU: Reserved for software use.
RTA: Accounting for ready state time RTO: Remaining time expired SBW: Stack base word SEG: Segment number SKW: Stack word SEG _EP :header in a procedure descriptor
segment SEG containing the entry point _PD : Segment containing procedure descriptor
SR: Scientific operation register SRA: Segment relative address STE: Segment table entry STN: Segment table number STR: Status register STW: Segment table word STWA: Segment table word array T: T register (stack register) URC: Unit record Control device WR: Write ring WTA: Write time accounting

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the multiprogramming system according to the present invention, FIG. 2 is a schematic diagram of various hardware used in the present invention, and FIG. 3 is a diagram showing the reserved storage area in the register shown in FIG. Abbreviations of terms used, Part 4
5 is a schematic diagram of the system for addressing the process control blocks; FIG. 6 is a system-based diagram of a computer system employing the present invention; FIG. 7A and FIG. FIG. 7B is a schematic diagram of the stack segment and stack frame of a computer system using the present invention, and FIG. 8 is a schematic diagram of the G segment, particularly the G-O
Schematic diagram of a system for addressing queues of processes in segments; FIG. 9 is an exploded diagram of a G-O segment showing the queues of processes and process linking of a computer system using the present invention; FIGS. 10A-10L are PCB Figures 11A to 11R are block diagrams of the structures in the system base; Figure 12 is a schematic diagram of the addressing scheme of user segments and system segments using the system base and PCB structures;
Figures 3A to 13C are schematic diagrams of the control unit of the present invention; Figures 14A to 14I are flowcharts of the dispatcher unit in firmware of a computer system using the present invention;
Figures 16A-15H are schematic diagrams of records and their pointers used in set instructions; Figures 16A-16C are diagrams of database page formats and descriptors that describe pages; Figure 17 is a diagram of finding database pages in main memory; Figures 18A and 18B are schematic diagrams of descriptors describing the sets and records used by database instructions; Figures 19A-19F are diagrams of the instruction format used by database instructions; 20A-20E are flowcharts of database direct discovery commands in firmware/hardware. 101... Processing device subsystem, 102...
Storage device subsystem, 103...Peripheral device subsystem, 104...Central processing unit (CPU), 1
05...Input/output control unit (IOC), 106...
...Peripheral device control unit, 107...Device adapter, 108...Peripheral device input/output device, 109...
Main memory synchronizer, 110... Buffer storage device, 111... Computation unit, 112...
Emulation equipment (emulator), 130...
...Control storage device, 201...General purpose register (GR), 202-203...Stack register,
204-205...Format, 206...Boundary address register (BAR), 207...Status register (STR), 400...Process control block (PCB), 501...Base address register (BAR), 502...System Base, 503...
...J table (entry), 505...J table pointer,
701... Stack frame, 702... T register, 703... Storage area, 704... Communication area, 801... G table, 802... GO segment, 803, 805... Process ring (queue), 901... ...Pointer, 902...Head,
903-904...Semaphore, 905...Queue, 1001...Capability byte, 1002...Priority byte, 1003...Status byte, 1004
...DEXT number, 1005...Account mode bit, 1006...Science mode bit, 100
7...Code mode bit, 1008...First 4 bits, 1009...Next 4 bits, 1010
...Operation field bit (A), 1011...
Suspension field bit (S), 1012... Substate field (SS), 1013... Intermediate operation field (MOI), 1014... Extended decor mode bit, 1016... Status byte, 10
17,1019...MBZ field, 1018
...Multi-processor bytes, 1019...MBZ
Field, 1026...STWSZ field,
1027...STWA field, 1028...
MBZ field, 1030...ATG field, 1031...RING field, 1032...
...Segment relative address (SRA), 1033...
...TAG field, 1034...RING field, 1036...TAG field, 1037...
...RING field, 1102...J table pointer, 1105...Indicator, 1107...
Process control block pointer, 1109...G
Table pointer, 1110...existence indicator,
1113...Flag Field (U), 111
4...Written flag field (W), 11
15...Gating indicator, 1116
...Base field, 1117...RSU field, 1118...MBZ field, 111
9...SIZE field, 1120...MBZ field, 1123...MBZ field, 112
5,1128,1131...MFS field,
1126-1127...Retry count field, 1129...PRI field, 1130...
...AB field, 1132...ARN field, 1133...JP field, 1136...
Serial number field, 1139... Upper limit, 1140,
1141...Channel number (CN), 1142~
1144...Field, 1148...MBZ field, 1149...G field, 1201
... Base register, 1202 ... Boundary address register, 1204 ... J table, 1205 ... P
Table, 1206... Process control block (PCB), 1211... User segment, 121
2...G segment table, 1213...Q, 1
214...Segment, 1215...System base, 1216...J table entry, 1301...
Control storage unit (CSU), 1302...Control storage interface adapter (CIA), 1303
... Control storage loader (CSL), 1304 ... Control load unit (CLU), 1306 ... Central processing unit, 1307 ... General purpose register, 1308 ...
Base register, 1309...Scientific data register, 1310...T register, 1311...Status register, 1312...Instruction counter, 1313
...Hardware control mask register, 1315
... Scratch pad memory, 1317 ... Arithmetic logic unit (ALU), 1318 ... Instruction fetch unit (IFU), 1319 ... Address control unit (ACU), 1320 ... System clock, 1321 ... Data management Unit (DMU), 1325... Control storage word, 132
6...Sequential type field, 1327...Blanching/micro OP field, 1328...
... Content generation instruction, 1329 ... Field from data to bus, 1330 ... Micro OP field, 1331 ... Checking field (P), 1333 ... Control storage array, 1335 ...
Block, 1337...KS register, 1338
...Incrementer, 1339...Interrupt return register (KA), 1340...KU register,
1341...Command, 1343...Local register, 1344...QMB bus, 1346...Return register, 1347...KT return register, 1349...KV return launch register,
1351...Decoding logic, 1352...Comparison logic, 1355...Maintenance panel, 1357
...read latch, 1359...micro OP decoder, 1360-1365...AND gate,
1501, 1510...Type field, 1
502...Record field, 1503, 1511
...Length field, 1504, 1512...
Recording body, 1505, 1513...Pointer sequence field, 1520...Next pointer field, 1521...Previous pointer field,
1524...Owner pointer field, 153
2...First pointer field, 1533...
Last pointer field, 1601... Page header, 1602... Row offset array, 160
3...offset, 1604...D-switch,
1610, 1612...Record, 1622...Area number, 1623...Digit count, 1624...
...Page number, 1625...Segment number, 162
6...Last page indicator, 1630...
MBZ field, 1632...Displacement, 1802
...P field, 1803...Set descriptor, 1804...Other pointer fields,
1805...Set edit mode field (K), 1806...Displacement field, 1820...
...F field, 1821...Record type field, 1822...Record length field, 191
0,1920,1930...Operation code, 191
1,1923,1933,1935...MBZ field, 1912,1934...Base register number (complement code), 1921,1931,1
932...Complement code, 1924...Logical deletion field, 1925...Pointer mode field, 1926...BR field, 1941,1
951...Type field, 1942, 195
2...Base register field, 1943, 1
953...address syllable, 1954...
MBZ field, 1955...Base register number, 1957...MBZ field, 1960
...Operation code, 1961...Basic field,
1962...Type field, 1963...P
field, 1965...first-next-previous pointer field, 1966...displacement field, 19
67...BR field.

Claims (1)

Claims: 1. A memory comprising a plurality of segments of addressable space, each segment identified by a segment number, for storing a set of one or more records. , each set has one owner record and one or more member records, and each record has its segment number and an off-set that positions the record within the segment relative to a predetermined storage location. each record in each of the plurality of sets has a respective identification of a given one or point record of the other plurality of records in the set. internally storing one or more database pointers for providing, each pointer thereby representing a storage location of said point record identified relative to said predetermined record of said set; In a programmed data processing device: (a) the address syllable of an instruction that directly retrieves a database record causes one of said sets to be retrieved;
(b) first means for accessing one of said database pointers from one record in said set and transferring said pointer to a first temporary register; defining the actual structure of a partition of said memory that holds things, and including the number of the segment in which said partition resides;
a second field responsive to a field of the contents of the database pointer in the first temporary register to obtain a descriptor from a storage location;
(c) from a table in said set the relative intra-set position or offset of each said point record with respect to a predetermined storage location within said set; third means responsive to another field of the contents of a database pointer; and (d) relative means or offset of said segment number and said point record to obtain an indication of a memory location holding said point record. and fourth means for loading into a second temporary register an apparatus for automatically converting a pointer identification of said point record into an indication of its storage location in memory.