JPS61131688U - - Google Patents
Info
- Publication number
- JPS61131688U JPS61131688U JP1464485U JP1464485U JPS61131688U JP S61131688 U JPS61131688 U JP S61131688U JP 1464485 U JP1464485 U JP 1464485U JP 1464485 U JP1464485 U JP 1464485U JP S61131688 U JPS61131688 U JP S61131688U
- Authority
- JP
- Japan
- Prior art keywords
- remaining time
- analog display
- displays
- unit
- display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Measurement Of Predetermined Time Intervals (AREA)
- Electric Clocks (AREA)
Description
図面はこの考案の一実施例を示し、第１図はタ
イマ装置のブロツク回路図、第２図はＲＡＭ８の
構成図、第３図は表示部の構成およびスイツチの
種類を説明する図、第４図は全体の動作を説明す
るジエネラルフローチヤートを示す図、第５図お
よび第６図は第４図で示したステツプＡ５の具体
的内容を説明するフローチヤートを示す図、第７
図および第８図はスイツチ操作等に応じて変遷す
る表示状態図である。
１……発振回路、２……第１の分周回路、３…
…第２の分周回路、４……コントローラ、５……
ＲＯＭ、６……タイミングジエネレータ、７……
入力部、８……ＲＡＭ、９……表示部、１１……
演算部、１３……アドレス制御部、２１……上位
単位アナログ表示体、２２……下位単位アナログ
表示体、Ｓ１……スタートストツプスイツチ、Ｓ
２……モード切替スイツチ。
The drawings show one embodiment of this invention, and FIG. 1 is a block circuit diagram of a timer device, FIG. 2 is a block diagram of the RAM 8, FIG. 3 is a diagram explaining the structure of the display section and types of switches, and FIG. The figure shows a general flowchart explaining the overall operation, FIGS. 5 and 6 show flowcharts explaining the specific contents of step A5 shown in FIG. 4, and FIG.
FIG. 8 and FIG. 8 are diagrams of display states that change depending on switch operations and the like. 1...Oscillation circuit, 2...First frequency dividing circuit, 3...
...Second frequency dividing circuit, 4...Controller, 5...
ROM, 6... Timing generator, 7...
Input section, 8...RAM, 9...Display section, 11...
Arithmetic unit, 13...Address control unit, 21...Upper unit analog display, 22...Lower unit analog display, S1 ...Start/stop switch, S
2 ...Mode changeover switch.
Claims (1)
共に、残り時間を表示するタイマ装置において、
残り時間の上位単位を表示する上位単位アナログ
表示体と、残り時間の下位単位を表示する下位単
位アナログ表示体と、前記タイマ装置が停止中に
前記残り時間の下位単位が０の時前記残り時間を
前記上位単位アナログ表示体のみで表示する第１
の表示制御手段と、前記タイマの動作中に残り時
間の下位単位が０の時前記残り時間を前記上位単
位アナログ表示体と下位単位アナログ表示体の組
み合せで表示する第２の表示制御手段とから成る
タイマ装置。 In a timer device that performs subtraction counting with respect to a preset time and displays the remaining time,
an upper unit analog display that displays the upper unit of the remaining time; a lower unit analog display that displays the lower unit of the remaining time; and the remaining time when the lower unit of the remaining time is 0 while the timer device is stopped. The first display unit displays only the upper unit analog display body.
and a second display control means for displaying the remaining time by a combination of the upper unit analog display and the lower unit analog display when the lower unit of the remaining time is 0 while the timer is operating. A timer device consisting of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1464485U JPH039029Y2 (en) | 1985-02-06 | 1985-02-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1464485U JPH039029Y2 (en) | 1985-02-06 | 1985-02-06 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61131688U true JPS61131688U (en) | 1986-08-16 |
| JPH039029Y2 JPH039029Y2 (en) | 1991-03-06 |
Family
ID=30499757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1464485U Expired JPH039029Y2 (en) | 1985-02-06 | 1985-02-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH039029Y2 (en) |
-
1985
- 1985-02-06 JP JP1464485U patent/JPH039029Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH039029Y2 (en) | 1991-03-06 |