JPS61131669U - - Google Patents

Info

Publication number
JPS61131669U
JPS61131669U JP1477385U JP1477385U JPS61131669U JP S61131669 U JPS61131669 U JP S61131669U JP 1477385 U JP1477385 U JP 1477385U JP 1477385 U JP1477385 U JP 1477385U JP S61131669 U JPS61131669 U JP S61131669U
Authority
JP
Japan
Prior art keywords
circuit
signal
reference clock
clock signal
conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1477385U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1477385U priority Critical patent/JPS61131669U/ja
Publication of JPS61131669U publication Critical patent/JPS61131669U/ja
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案による三角波信号校正装置の
構成図、第2図は第1図の動作を示すタイミング
チヤート、第3図は測定される信号のRAMP波
形部分とサンプリングの様子を示す図、第4図は
従来のオシロスコープによる測定を示す図、第5
図はオシロスコープのCRT管面上で目視により
波形を観測し直線性を算出する様子を説明する図
である。 図中1は微分回路、2は波形整形回路、3はサ
ンプリングパルス発生回路、4は分周器、5はク
ロツク信号発生器、6はパルスカウンタ/コンパ
レータ、7は高速A/D変換回路、8はメモリ回
路、9は演算回路、10は表示回路である。
Fig. 1 is a configuration diagram of the triangular wave signal calibration device according to this invention, Fig. 2 is a timing chart showing the operation of Fig. 1, Fig. 3 is a diagram showing the RAMP waveform part of the signal to be measured and the sampling state, Figure 4 shows measurement using a conventional oscilloscope, Figure 5
The figure is a diagram illustrating how linearity is calculated by visually observing a waveform on the CRT tube surface of an oscilloscope. In the figure, 1 is a differentiation circuit, 2 is a waveform shaping circuit, 3 is a sampling pulse generation circuit, 4 is a frequency divider, 5 is a clock signal generator, 6 is a pulse counter/comparator, 7 is a high-speed A/D conversion circuit, 8 9 is a memory circuit, 9 is an arithmetic circuit, and 10 is a display circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号を微分する微分回路と、上記微分回路
の出力信号を波形整形する波形整形回路と、基準
クロツク信号を発生する基準クロツク信号発生器
と、上記波形整形回路の出力で制御される期間だ
け上記基準クロツク信号又はそのてい倍の周期の
パルス列を発生するサンプリングパルス発生回路
と、上記サンプリングパルス列でトリガ駆動され
て入力信号を逐次A/D変換するA/D変換回路
と、上記A/D変換回路の変換結果を記憶するメ
モリ回路と、この1組のA/D変換データ群から
入力信号の直線性を算出する演算回路と、上記演
算回路の演算結果を表示する表示回路とを具備し
たことを特徴とする三角波信号校正装置。
A differentiating circuit that differentiates the input signal, a waveform shaping circuit that shapes the output signal of the differentiating circuit, a reference clock signal generator that generates a reference clock signal, and the above-mentioned signal only for a period controlled by the output of the waveform shaping circuit. a sampling pulse generation circuit that generates a pulse train of a reference clock signal or a period twice that of the reference clock signal; an A/D conversion circuit that is triggered by the sampling pulse train and sequentially A/D converts the input signal; and the A/D conversion circuit. A memory circuit for storing the conversion result of the above, an arithmetic circuit for calculating the linearity of the input signal from this set of A/D conversion data, and a display circuit for displaying the arithmetic result of the arithmetic circuit. Characteristic triangular wave signal calibration device.
JP1477385U 1985-02-05 1985-02-05 Pending JPS61131669U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1477385U JPS61131669U (en) 1985-02-05 1985-02-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1477385U JPS61131669U (en) 1985-02-05 1985-02-05

Publications (1)

Publication Number Publication Date
JPS61131669U true JPS61131669U (en) 1986-08-16

Family

ID=30500005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1477385U Pending JPS61131669U (en) 1985-02-05 1985-02-05

Country Status (1)

Country Link
JP (1) JPS61131669U (en)

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