JPS61131207A - Alternating current bias circuit for sound recording - Google Patents

Alternating current bias circuit for sound recording

Info

Publication number
JPS61131207A
JPS61131207A JP59253287A JP25328784A JPS61131207A JP S61131207 A JPS61131207 A JP S61131207A JP 59253287 A JP59253287 A JP 59253287A JP 25328784 A JP25328784 A JP 25328784A JP S61131207 A JPS61131207 A JP S61131207A
Authority
JP
Japan
Prior art keywords
circuit
current
transistor
bias
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59253287A
Other languages
Japanese (ja)
Inventor
Hisanobu Kakihara
柿原 久信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59253287A priority Critical patent/JPS61131207A/en
Publication of JPS61131207A publication Critical patent/JPS61131207A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/02Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
    • G11B5/027Analogue recording
    • G11B5/03Biasing

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  • Amplifiers (AREA)

Abstract

PURPOSE:To obtain a circuit which generates no click sound with an AC bias signal during reproducing operation by providing a time constant circuit which slows down the rising and falling of the DC operation voltage of a constant current circuit. CONSTITUTION:A transistor (TR) 2 for control is impressed with a control signal A at its base at time t1 to turn on, and a DC operating voltage B impressed to the constant current circuit 5 rises slowly with the time constant determined by the internal resistance of the TR 2 and a capacitor 17. A current mirror circuit 10 outputs an intermittent current which is intermitted at the same period with an AC bias frequency signal C and increases slowly as the collector current of a TR 9, thereby obtaining an AC bias signal D. When the control signal A is ceased at time t2 and the base of the TR 2 goes up to H, this TR 2 turns off, but as the capacitor 17 of the time constant circuit 16 is discharged to a resistance 18, the operating voltage B drops and the constant circuit 5 loses current constancy and its output current decreases, so that the AC bias signal falls to zero at time t3 eventually. Therefore, no click tone is generated during reproducing operation.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は磁気テープレコーダの録音用交流バイアス回
路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an AC bias circuit for recording in a magnetic tape recorder.

[従来の技術] 従来この種回路として第3図に示すものがあった。第3
図は従来の録音用バイアス回路を示す回路図で、図にお
いて、(1)は直流電源、(2)は制御信号のベースへ
の印加によってオン、オフする制御用トランジスタ、(
3) (4)は定電流回路(5)を構成するトランジス
タ、(6)は定電流回路(5)の電流値を設定する抵抗
、(7)は交流バイアス周波数でオン、オフする断続ス
イッチングトランジスタ、(8) (9)はカレントミ
ラー回路(10)を構成するトランジスタ、(11)は
交流バイアス信号の振幅を適当にするためのトランス、
(12)はトランス(11)と共振することにより交流
バイアス信号波形を正弦波電圧とするためのコンデンサ
で、これらトランス(11)及びコンデンサ(12)と
で交流バイアス印加回路(13)を構成している。(1
4)は録音用信号源、(15)は録音用ヘッドである。
[Prior Art] A conventional circuit of this type is shown in FIG. Third
The figure is a circuit diagram showing a conventional recording bias circuit. In the figure, (1) is a DC power supply, (2) is a control transistor that is turned on and off by applying a control signal to the base, (
3) (4) is a transistor that constitutes the constant current circuit (5), (6) is a resistor that sets the current value of the constant current circuit (5), and (7) is an intermittent switching transistor that turns on and off at the AC bias frequency. , (8) (9) is a transistor constituting the current mirror circuit (10), (11) is a transformer for appropriate amplitude of the AC bias signal,
(12) is a capacitor for making the AC bias signal waveform into a sine wave voltage by resonating with the transformer (11), and these transformer (11) and capacitor (12) constitute an AC bias application circuit (13). ing. (1
4) is a recording signal source, and (15) is a recording head.

次にその動作を第4図にて説明する。第4図は信号波形
図で第4図Aは1−ランジスタ(2)のベースに印加さ
れる制御信号、同図Bは定電流回路(5)に印加される
直流動作電圧、同図Cはトランジスタ(7)のベースに
印加される交流バイアス周波数の信号、同図りは交流バ
イアス印加回路(13)から録音用ヘッド(15)に印
加される交流バイアス信号を示している。
Next, the operation will be explained with reference to FIG. Figure 4 is a signal waveform diagram. Figure 4A is the control signal applied to the base of the transistor (2), Figure B is the DC operating voltage applied to the constant current circuit (5), and Figure C is the control signal applied to the base of the transistor (2). The AC bias frequency signal applied to the base of the transistor (7) shows the AC bias signal applied from the AC bias application circuit (13) to the recording head (15).

令弟4図の時点t1でLレベルの制御信号Aが制御用ト
ランジスタ(2)のベースに印加されると、トランジス
タ(2)はオンし、1−ランジスタ(3)(4)及び抵
抗(6)からなる定電流回路(5)に動作電圧Bが印加
されて動作を開始し、トランジスタ(4)はトランジス
タ(3)のベース・エミッタ間電圧(シリコントランジ
スタの場合約0.7V)を抵抗(6)の抵抗値で割った
値とほぼ等しい電流値のコレクタ電流を流す。この定電
流コレクタ電流は、トランジスタ(7)とカレントミラ
ー回路(10)の一方のトランジスタ(8)とに交互に
切換えられる。即ち断続スイッチングトランジスタ(7
)は第4図Cに示す信号によりオン、オフされており、
そのトランジスタがオンの時はトランジスタ(8)には
電流は流れずカレントミラー回路(10)は動作せず、
トランジスタ(7)がオフの時は、トランジスタ(8)
がオンし定電流回路(5)の電流はトランジスタ(8)
側に切換えられ、トランジスタ(8)と共にトランジス
タ(9)にもコレクタ電流が流れる。このカレントミラ
ー回路(10)から出力されるトランジスタ(7)のオ
ン、オフによる断続電流は、交流バイアス印加回路(1
3)により第4図りに示すよう適当な振幅の正弦波に変
換され録音用信号源(14)の信号と重畳して録音用ヘ
ッド(15)に印加され、録音される。      1
次に時点t2で制御信号Aがなくなりトランジスタ(2
)のベースがHレベルとなると、このトランジスタ(2
)はオフとなりそれのコレクタ電流は流れず、定電流回
路(5)への動作電圧BはLとなりその動作は停止する
。それでトランジスタ(4)のコレクタ電流はゼロとな
り、カレントミラー回路(10)の出力電流も常にゼロ
となって交流バイアス信号りの発生は停止する。即ち制
御信号Aがトランジスタ(2)のベースに印加されてい
る時のみ交流バイアス信号りが録音ヘッド(15)に出
力される。
When the L-level control signal A is applied to the base of the control transistor (2) at time t1 in Figure 4, the transistor (2) is turned on, and the transistors (3) and (4) and the resistor (6) are turned on. ) is applied to the constant current circuit (5) to start operation, and the transistor (4) connects the base-emitter voltage (approximately 0.7 V in the case of a silicon transistor) of the transistor (3) to the resistor ( 6) A collector current with a current value approximately equal to the value divided by the resistance value is caused to flow. This constant collector current is alternately switched between the transistor (7) and one transistor (8) of the current mirror circuit (10). That is, the intermittent switching transistor (7
) is turned on and off by the signal shown in Figure 4C,
When that transistor is on, no current flows through the transistor (8) and the current mirror circuit (10) does not operate.
When transistor (7) is off, transistor (8)
is turned on, and the current of the constant current circuit (5) flows through the transistor (8).
The collector current flows through transistor (9) as well as transistor (8). The intermittent current generated by the on/off of the transistor (7) output from the current mirror circuit (10) is generated by the AC bias application circuit (10).
3), the signal is converted into a sine wave with an appropriate amplitude as shown in the fourth diagram, and is applied to the recording head (15) while being superimposed on the signal from the recording signal source (14) to be recorded. 1
Next, at time t2, the control signal A disappears and the transistor (2
) becomes H level, this transistor (2
) is turned off and its collector current does not flow, and the operating voltage B to the constant current circuit (5) becomes L and its operation stops. Therefore, the collector current of the transistor (4) becomes zero, the output current of the current mirror circuit (10) also becomes zero, and the generation of the AC bias signal stops. That is, the AC bias signal is output to the recording head (15) only when the control signal A is applied to the base of the transistor (2).

[発明が解決しようとする問題点] 従来の録音用交流バイアス回路は以上のように構成され
ているので、制御信号Aの印加(時点tl)によって所
定振幅の交流バイアス信号が急に発生して録音され、制
御信号Aの消滅(時点t2)で急に交流バイアス信号が
なくなる。即ち交流バイアス信号の出始めと終りの急峻
な信号の変化が録音される。そのためこれを再生した場
合、この交流バイアス信号の出始めと終りとにクリック
音が聞こえるという問題点があった。
[Problems to be Solved by the Invention] Since the conventional recording AC bias circuit is configured as described above, an AC bias signal of a predetermined amplitude is suddenly generated by applying the control signal A (time tl). The AC bias signal suddenly disappears when the control signal A disappears (time t2). That is, the sharp signal changes at the beginning and end of the AC bias signal are recorded. Therefore, when this is played back, there is a problem in that a click sound can be heard at the beginning and end of the AC bias signal.

この発明は上記のような問題点を解決するためになされ
たもので、再生時にクリック音の生じない録音用交流バ
イアス回路を提供することを目的とする。
The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an AC bias circuit for recording that does not produce click sounds during playback.

[問題点を解決するための手段] この発明にかかる録音用交流バイアス回路は、上記従来
の回路における、制御用トランジスタのオン、オフによ
る定電流回路の直流動作電圧Bの立ち上がり、立ち下が
りを、ゆるやかにする時定数回路を設けたものである。
[Means for Solving the Problems] The recording AC bias circuit according to the present invention changes the rise and fall of the DC operating voltage B of the constant current circuit by turning on and off the control transistor in the conventional circuit described above. It is equipped with a time constant circuit to make it more gradual.

[作 用] この発明においては、定電流回路の直流動作電圧が、急
峻に立ち上がり立ち下がらないでゆるやかに変化し、録
音ヘッドに印加される交流バイアス信号の振幅も出始め
にはなめらかに増加していき、終りにはなめらかに減少
していくので、再生時にクリック音が生ずることはない
[Function] In this invention, the DC operating voltage of the constant current circuit changes gradually without rising and falling sharply, and the amplitude of the AC bias signal applied to the recording head also increases smoothly at the beginning. The value gradually increases and decreases smoothly at the end, so no click sound is generated during playback.

[実施例] 以下この発明の実施例を図について説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.

第1図はこの発明の一実施例を示す回路図で、図におい
て(1)〜(15)は第3図の同一符号と同一部分を示
し、 (16)はコンデンサ(]7)と抵抗(18)と
からなる時定数回路である。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, (1) to (15) indicate the same parts with the same symbols as in FIG. 18).

次にその動作を第2図の信号波形図にて説明する。第2
図のA−Dは第4図のA〜Dに相当する信号で、それぞ
れ制御信号A、直流動作電圧B、交流バイアス周波数信
号C及び交流バイアス信号りを示す。まず時点t1で制
御信号Aが制御用トランジスタ(2)のベースに印加さ
れてトランジスタ(2)はオンとなるが、コレクタ電流
は最初は時定数回路(16)に流れコンデンサ(17)
を充電していくので、定電流回路(5)に印加される動
作電圧は第2図Bに示すようにトランジスタ(2)の内
部抵抗とコンデンサ(17)によってきまる時定数でゆ
るやかに立ち」二がっていく。それに応じて定電流回路
(5)の電流、即ちトランジスタ(4)のコレクタ電流
もゆるやかに増加していき最終的には、1ヘランジスタ
(3)のベース・エミッタ電圧(シリコントランジスタ
の場合約0.7V)を抵抗(6)の抵抗値で割った値と
なる。トランジスタ(7)は交流バイアス周波数信号C
でオン、オフされているので、そのオン、オフに応じて
定電流回路(5)の出力電流がこのトランジスタ(7)
とカレン1〜ミラ一回路(10)とに切換えられ、カレ
ントミラー回路(10)からは、信号Cと同一周期で断
続されたゆるやかに増加する断続電流がトランジスタ(
9)のコレクタ電流として出力される。この断続出力電
流は第2図りのように交流バイアス印加回路(13)に
より正弦波に変換され、録音用信号源(14)の信号と
重畳して録音ヘッド(15)に印加され録音される。
Next, the operation will be explained with reference to the signal waveform diagram in FIG. Second
A to D in the figure are signals corresponding to A to D in FIG. 4, and indicate a control signal A, a DC operating voltage B, an AC bias frequency signal C, and an AC bias signal, respectively. First, at time t1, the control signal A is applied to the base of the control transistor (2) and the transistor (2) is turned on, but the collector current initially flows to the time constant circuit (16) and the capacitor (17).
As shown in Figure 2B, the operating voltage applied to the constant current circuit (5) rises gradually with a time constant determined by the internal resistance of the transistor (2) and the capacitor (17). I'm going down. Correspondingly, the current of the constant current circuit (5), that is, the collector current of the transistor (4), gradually increases, and finally the base-emitter voltage of the 1-herlange transistor (3) (approximately 0.0. 7V) divided by the resistance value of the resistor (6). Transistor (7) receives AC bias frequency signal C
Since the transistor (7) is turned on and off, the output current of the constant current circuit (5) changes depending on whether it is turned on or off.
The current mirror circuit (10) sends a slowly increasing intermittent current that is intermittent at the same period as the signal C to the transistor (10).
9) is output as the collector current. This intermittent output current is converted into a sine wave by the AC bias application circuit (13) as shown in the second diagram, and is applied to the recording head (15) to be recorded while being superimposed on the signal from the recording signal source (14).

次に時点t2で制御信号Aがなくなりトランジスタ(2
)のベースが■]となると、このトランジスタ(2)は
オフとなるが、時定数回路(16)のコンデンサ(17
)が充電されており動作電圧Bが残存しているので、定
電流回路(5)はまだ動作を続け、トランジスタ(4)
はコレクタ電流を流し交流バイアス信号りは出力される
。コンデンサ(17)の充電電圧が抵抗(18)に放電
するにしたがって、動作電圧Bが減少し定電流回路(5
)は定電流性を失って出力電流は減少し最終的には時点
t3でゼロとなる。
Next, at time t2, the control signal A disappears and the transistor (2
) becomes ■], this transistor (2) turns off, but the capacitor (17) of the time constant circuit (16)
) is charged and the operating voltage B remains, so the constant current circuit (5) continues to operate, and the transistor (4)
The collector current flows and the AC bias signal is output. As the charging voltage of the capacitor (17) discharges into the resistor (18), the operating voltage B decreases and the constant current circuit (5
) loses its constant current property, the output current decreases, and finally reaches zero at time t3.

それに応じて交流バイアス印加回路(13)からの交流
バイアス信号りの振幅はゆるやかに減少していき時点t
3で交流バイアス信号りは発生しなくなる。このように
急峻に立ち上がる制御信号Aが印加されても動作電圧B
はゆるやかに立ち上がり、交流バイアス信号りはなめら
かに振幅を増加していき、制御信号Aが急に立ち下がっ
ても動作電圧の立ち下がりはゆるやかとなり交流バイア
ス信号りの振幅はなめらかに減少してゼロとなる。従っ
てこのような交流バイアス信号が録音ヘッド(15)で
磁気テープに記憶されても再生時にクリック音が生ずる
ことはない。
Correspondingly, the amplitude of the AC bias signal from the AC bias application circuit (13) gradually decreases until time t.
3, no AC bias signal is generated. Even if control signal A that rises sharply is applied in this way, operating voltage B
rises slowly, and the amplitude of the AC bias signal increases smoothly.Even if the control signal A suddenly falls, the fall of the operating voltage is gradual, and the amplitude of the AC bias signal smoothly decreases to zero. becomes. Therefore, even if such an AC bias signal is stored on the magnetic tape by the recording head (15), no click sound will be generated during reproduction.

以」二の回路はトランジスタ、抵抗等の個々の回路部品
を配線して構成してもよいが、半導体集積回路によって
も構成し得ることはもちろんである。
The above two circuits may be constructed by wiring individual circuit components such as transistors and resistors, but of course they may also be constructed using semiconductor integrated circuits.

[発明の効果] この発明は以上のように定電流回路の直流動作電圧の立
ち上がり、立ち下がりをゆるやかにする時限回路を設け
たので、再生時に交流バイアス信号によるクリック音が
生じない録音用交流バイアス回路がi!Itな回路付加
によって得られる効果がある。
[Effects of the Invention] As described above, the present invention is provided with a time-limiting circuit that slows down the rise and fall of the DC operating voltage of the constant current circuit, so that the AC bias for recording does not generate click sounds due to the AC bias signal during playback. The circuit is i! There is an effect obtained by adding a special circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示す回路図、第2図はそ
の各部の信号波形図、第3図は従来の録音用交流バイア
ス回路を示す回路図、第4図はその各部の信号波形図で
ある。 図において(1)は直流電源、(2)は制御用トランジ
スタ、(5)は定電流回路、(7)は断続スイッチング
トランジスタ、(10)はカレントミラー回路、(13
)は交流バイアス信号印加回路、(14)は録音用信号
源、(15)は録音ヘッド、(16)は時定数回路であ
る。 図中同一符号は同−或は相当部分を示す。
Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a signal waveform diagram of each part thereof, Fig. 3 is a circuit diagram showing a conventional recording AC bias circuit, and Fig. 4 is a signal diagram of each part thereof. FIG. In the figure, (1) is a DC power supply, (2) is a control transistor, (5) is a constant current circuit, (7) is an intermittent switching transistor, (10) is a current mirror circuit, and (13) is a constant current circuit.
) is an AC bias signal application circuit, (14) is a recording signal source, (15) is a recording head, and (16) is a time constant circuit. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

【特許請求の範囲】[Claims] (1)制御信号によってオン、オフする制御用トランジ
スタ、このトランジスタのオン、オフによって直流動作
電圧が印加、遮断される定電流回路、交流バイアス周波
数でオン、オフする断続スイッチングトランジスタ、こ
のトランジスタのオン、オフによって上記定電流回路の
出力電流が切換えられ、この切換えに応じた断続電流を
出力するカレントミラー回路、及びこのカレントミラー
回路の断続出力電流を正弦波電圧に変換し録音用信号と
重畳して録音用ヘッドに印加する交流バイアス信号印加
回路を備えた録音用交流バイアス回路において、上記制
御用トランジスタのオン、オフによる上記定電流回路の
直流動作電圧の立ち上がり、立ち下がりをゆるやかにす
る時定数回路を設けたことを特徴とする録音用交流バイ
アス回路。
(1) A control transistor that turns on and off according to a control signal, a constant current circuit that applies or cuts off a DC operating voltage depending on whether this transistor is turned on or off, an intermittent switching transistor that turns on or off at an AC bias frequency, and this transistor that turns on or off. , the output current of the constant current circuit is switched by turning off, and a current mirror circuit outputs an intermittent current according to this switching, and the intermittent output current of this current mirror circuit is converted into a sine wave voltage and superimposed on the recording signal. In a recording AC bias circuit equipped with an AC bias signal application circuit that applies an AC bias signal to a recording head, a time constant is provided to slow the rise and fall of the DC operating voltage of the constant current circuit due to turning on and off of the control transistor. An alternating current bias circuit for recording characterized by providing a circuit.
(2)上記時定数回路は、上記制御用トランジスタのオ
ンによって充電されるコンデンサと、このトランジスタ
のオフによってこのコンデンサの充電電圧を放電する抵
抗とからなり、上記コンデンサの充電電圧を上記定電流
回路の直流動作電圧として印加するようになされたもの
である特許請求の範囲第1項記載の録音用交流バイアス
回路。
(2) The time constant circuit includes a capacitor that is charged when the control transistor is turned on, and a resistor that discharges the charging voltage of the capacitor when the transistor is turned off, and the charging voltage of the capacitor is transferred to the constant current circuit. 2. The recording AC bias circuit according to claim 1, wherein the recording AC bias circuit is adapted to be applied as a DC operating voltage.
JP59253287A 1984-11-29 1984-11-29 Alternating current bias circuit for sound recording Pending JPS61131207A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59253287A JPS61131207A (en) 1984-11-29 1984-11-29 Alternating current bias circuit for sound recording

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59253287A JPS61131207A (en) 1984-11-29 1984-11-29 Alternating current bias circuit for sound recording

Publications (1)

Publication Number Publication Date
JPS61131207A true JPS61131207A (en) 1986-06-18

Family

ID=17249182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59253287A Pending JPS61131207A (en) 1984-11-29 1984-11-29 Alternating current bias circuit for sound recording

Country Status (1)

Country Link
JP (1) JPS61131207A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5819709A (en) * 1981-07-27 1983-02-04 Matsushita Electric Ind Co Ltd Magnetic recorder and reproducer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5819709A (en) * 1981-07-27 1983-02-04 Matsushita Electric Ind Co Ltd Magnetic recorder and reproducer

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