JPS61122991A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To realize a first in, first out FIFO of large capacity and high speed by writing a data inputted in writing register sequence in a memory cell and taking out the data according to a written order. CONSTITUTION:In case of 8 signal sequences, a value of a signal sequence SIN is held in registers SR1-SR8 of a shift register sequence 2 and other SRd9 SR9-SR256 are reset. Under this condition, when a transfer signal TR=1 and a reading/writing signal R/W=1 are applied to a driver 10, by a clock signal TCLKB, a gate sequence 11 is turned on, values of the registers SR1-SR256 are all written in a memory cell of a designated word line. When the signals TR=1 and R/W=0 are applied to the driver 10, by a signal TCLKA, a gate sequence 8 is turned on and the contents of the memory cell are all read by registers R1-R256. Under this condition, a counting value 8 of a counter 3 is applied to a decoder 7, a register PSR8 is set, an output gate 5 is turned on, and an output of a register R8 is taken by a data bus DB and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and is a semiconductor memory device capable of storing a large capacity memory at high speed (FIFO). Regarding storage devices.

[Problems to be solved by conventional technology and invention]

The so-called FIFO, which outputs data in sequence from the first input, is performed in units of registers or in units of memory systems. However, although register-based processing is fast, it is not suitable for large-capacity FIFOs.
Alternatively, large-capacity processing can be performed on a memory system basis, but there is a problem in that the processing speed is slow. Therefore, large capacity FIFO1? A semiconductor memory device that operates at high speed has not yet been proposed.

[Means for resolving the problem]

In the present invention, a write register array consisting of a plurality of shift registers connected to one address selection line of the memory cell via a gate, and a plurality of registers connected to the one address selection line of the memory cell via a gate. A readout register array consisting of a plurality of shift registers that control output gates connected to each output of the readout register array and output the output of the readout register to a data bus connected to the output gate. a counter that counts the number of data input to the write register string and specifies the position of the pointer shift register string based on the counted value; There is provided a semiconductor memory device in which data input to the memory cell is written into the memory cell and the data is taken out from the data bus in the order in which the data was written.

[For production]

A write register row consisting of a plurality of shift registers is provided corresponding to one address selection line, for example, a Hahit line, of the mesori cell, and input data is stored in the register row in the order of input. The number of input data is counted by a counter. The memory contents of the above register row are collectively stored in a memory cell, word f.
8 is specified separately.

On the other hand, a readout register array consisting of a plurality of registers is provided corresponding to the pit line, and reads out the stored contents at once and holds the contents. The readout register row is provided with an output gate, and this gate is controlled by the pointer shift register row, and the pointer shift register row receives the value counted by the above-mentioned counter via the column decoder, that is, the first input value. The output gates are initialized to the data position signal, and the output gates are opened in the order of input data to take out the data onto the data bus.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

Ic1 Figure 1 shows a configuration diagram of a semiconductor memory device as an embodiment of the present invention. In Figure 1, l is a dynamic RA.
The M device is shown, and the sense amplifier, row decoder, column decoder, etc. are omitted. This example is bit line BLI
~BL256, word line WL1~WI, memory cell (MC) Th of 65 connected to 256 in a matrix
have. A shift register row 2 consisting of the same number of shift registers as the bit lines is provided to the let lines BLI to BL256 via a transformer 7 agate row 11t.
An input signal s0 is applied to the shift register SRI. Further, a counter 3 for counting the clock signal 5CLK2'f is provided.

On the other hand, the bit lines BLl to BL256 are provided with the same number of registers 4 as the bit lines via transformer 7 agate columns 8, and their outputs are connected to the data bus DB via the output gate column 5. Bus DB is output amplifier 9
The output gate array 5 is connected to a pointer shift register (P
The PSR column is controlled by the column decoder 7 which receives the output of the counter 3.

A transfer lock driver 10 is provided which outputs a clock signal TaLtm or T CL Ic A to control the transformer 7 agate column 8 or 11t.

@1 As an example concrete circuit of the shift register 5RI-8R2560 shown in Figure 1, a two-phase ratio shift register is used as the second
The operation timing chart is shown in FIG. In other words, the operation of the shift register is to first transfer the value of the node N14 of the shift register SR1 at t/lJR to the node N□ by turning on the transistor Q in response to the clock pulse Pi as a master transfer, and transfer the value of the node N14 of the shift register SR1 at t/lJR to the node N□. When the voltage level is "1", the level of node N is inverted.

Further, as a fast transfer, the clock pulse P2 is used to turn on the transistor Qxs t-, thereby increasing the level of the node N and the level of the node N8. with the same level, and the nodes N2. The signal level of node N24 is inverted to the signal level of . The register row 4 shown in FIG. Shown in Figure 4.

In FIG. 4, the bit lines BLi are connected to BLi.

Transistors Qsy and QCs driven by the clock signal TcLKAVc indicate the gates of the transfer gate row 8, and one pointer command POIK: of the pointer shift register row 6 is driven and the SQ and SQ outputs of 7 lip-flops to be described later are connected to the data bus. Transistor Q, which outputs to DB. and Q. C indicates the gate of transistor row 5
Therefore, as a register, the transistor pair Qs4 and C
31 and a pair of capacitors C and C2 are shown connected as shown.

The 7 lip 70 tube path shown in FIG. 4 is Tcm.

The transfer gate Qsa*C37 is turned on and set or reset to the level signal of either BLi or BLi, and among the results, the pointer command P
OI Vc to transfer) Qi. .

What is driven by Qi2 is read out by the output amplifier 9 via the data bus. That is, the clip 7a block circuit simply holds the value on the bit line, but does not shift it to the next stage 7 lip 70 block.

An exemplary circuit diagram of the pointer shift register array 6 is shown in FIG. The nth pointer shift register PSRn is
Transistors Q6° to Qsy are connected as shown in the figure, and 256 transistors are successively connected.

The pointer shift register of FIG. 5 is f-driven by PE and NPEPE f-clock pulses TcL□ having different phases as shown in FIG. Let us describe its operation.

When the PE signal is at “H” level, output information 5 of the n-1st stage
Set Ln-□=1, and all other output information SL, =-...
...=SLn-z=BLn=SLn+t=””=SL
Let ssa=0. The trunk ylQ641cx charges up the n-th stage SPn to 1, and SPn enters the gate of the transistor Qys, so that the n-1st stage S PH
−Reset to t=0. These SPn tsP
The information of n- is retained even if PK becomes %L level. In this state, the NPE signal is enabled and drives the transistors C6□, Q, 2, etc., so that the transistor Q
SPn = 1 and SPn for the gates of 6° and C7°, respectively.
Convey information on =07. These transistors Q. and Q. The information accumulated in the gate of the NEP signal is “L”
0 which is held even when the level becomes 0. Thus the transistor Q
6°.

When the PE signal goes to "H" level with Qyo prepared, 5Ln=11SLn- becomes O, and as a result, the only "1" information is transferred to the adjacent bit.0 At this time, the transistor QyiA+ Qtsm
To ensure that 5Ln-, = 0, the transistor Q
7゜■Prevents the gate from being brought to a high potential, transistor Q6! A, Q63! Since the gate of C6° is brought to a sufficiently high potential at 1, the gate voltage of transistor Qasm quickly becomes ``L'' level together with the output of SLn.

In Figure 5, transistor Qss + Qmt *
Q7□ or 3 called Qsa -Qst v Qst
The pair of transistors is for 70-setting prevention against the majority of SLL being "0", and the transistor Qsge Qss is a depressing transistor or a resistance element. In this way, the NPE and PE signals are shifted one pit at a time, and the registers at the previous stage are cleared. Pointer shift register PSR
The reason why only one of 1 to PSR,s is rlJ is that the output t of register 4 is connected to data bus DB.
- This is to peek at each page one by one. However, in the process described later, the pointer register is changed from PS to PSRn as described above.
P S Rn =
P S Rt.

The operation of the memory device shown in FIG. 1 using the above-described circuit will be described. First, the D-RAM full, the write register I) 182, and the read register side 4 can each operate independently and asynchronously.

Therefore, D-RAM can be accessed normally.
11: When there is no normal access to the D-RAM, write and read operations associated with FIFO processing described below are performed.

In the FIFO operation, first, the shift register column 2 is cleared and the counter 31C clear signal CLR is applied to reset the counter 3. However, clearing the shift register column 2 is not necessarily necessary depending on the application and purpose.

Next, an input signal string SIN is applied from the first register SRI of the shift register string 2. The signal string s4 is completely shifted by the clock signal 5CLK2[j] in the shift register string 2. On the other hand, the clock signal 5CLK2 is applied to the counter 3, which counts the number of shifts in the input signal string. For example, if there are eight signal trains, the count value n = 8. When the above shift is completed, the counter fixing signal FIXK: The processing count value is fixed.
While the value of the code sequence S4 is held and the other SR9 to 5R256 are reset, the transfer request signal TR=1 and the read/V included signal/W=1 are transferred to the lock driver 1o.
When applied to the clock signal T. The gate row 11 in LKR is turned on, and the value of SRI~5R256 becomes
A description will be given of reading data written in the 0th order memory cells that are collectively written to the memory cells of the designated word MWI, d. When TR=1 and R/W=O are applied to the transfer lock driver lO, the clock signal TcLK turns on the E-fgate column 8, and the contents of the stored memory cells are collectively transferred to the registers R1 to R256. It will be published one after another. It is clear that R8 holds the data first input to the shift register 2, and R1 holds the data input after f&.

In the above state, the count value of the counter 3=8 is applied to the column decoder 7, and the decoder sets the eighth point shift register PSR,'i.

In addition, the L diPSR turns on the output gate 57 of the register R6 and outputs the output of the register R6 to the data bus DB. The data released from the data bus DBVC is outputted via the output amplifier 9. Therefore, clock signal 5CLKI
machined, sequentially PSR, →PSR, →・・・・・・PS
By shifting the set states of R and PSR, the data recorded in the memory cells is taken out in accordance with the order of data input to the register 4. In other words, FIFO has been realized.

, Although the above embodiments are cases in which FIFO is performed only for word m WL d , FIFO is generally performed for a plurality of word lines in many cases. In such a case, the above-mentioned operation will be repeated.

Don't do this! FIFO1k! In order to carry out one recording entirely on its own, a word line drive recording control circuit 12 is provided as shown in FIG. In other words, input signal string S0 to shift register string 2
input, when a predetermined word line is selected and writing to a predetermined memory cell continues repeatedly.

The selection driving order of word lines is memorized. Next, word lines are selected according to the word line selection drive order stored in the read mode. By initializing the pointer shift register 'ff:8 each time a word is selected, automatic FIFO is also possible for the word line.

It is obvious that the register circuits of register row 2 and register row 4 can have various circuit configurations other than those shown in FIGS. 2 and 4. For example, register row 4 shown in the figure for the first prisoner.
Another example of the circuit is shown in FIG.

Even if this circuit fails, transistor Q4y is transformer 7
One gate of agate column 8 is shown, transistor Q4
゜, Q48 indicates a pair of gates in the transfer gate array 5. As a latch circuit, transistor pair Q4m
and Q-as, and a pair of capacitors C3 and C4 are connected as shown, and a charge-up transistor Q
44 are connected as shown. Of course, a charge pump circuit can be further provided in SQ,n (not shown). In FIG. 7, one gate of the transfer gate 8 is a transistor Q4□, and a charge-up transistor Q44k is provided, and its operation is similar to that of the circuit shown in FIG.

Furthermore, the register array 4 can be not only a latch type circuit as shown in FIGS. 4 and 7, but also a shift register as shown in FIG. 2. Similarly, the shift register array 2, The circuits of the pointer shift register array 6 may have other circuit configurations as long as they have the same functions as described above.

It goes without saying that CLR, F in Figure 1
Control signals such as IX, TR, R/W, etc. do not necessarily have to occupy their own pins, but can be generated within the device by mode recognition that can be combined with other various control signals, etc., as necessary. Even if it's a signal, it's difficult.

〔Effect of the invention〕

By implementing the present invention as described above, a large-capacity, high-speed FIFO can be realized.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device as an embodiment of the present invention, FIG. 2 is a circuit diagram as an embodiment of a shift register in the device, FIG. 3 is the operation timing of the circuit in FIG. Figure 4 is the first
5 is a circuit diagram as an example of the register in the device shown in FIG. 1. FIG. 6 is an operation timing diagram of the circuit shown in FIG. 5. The figure is the first
O circuit diagram as another example of the register in the device shown in FIG.
It is. (Explanation of symbols) 1...D-RAM, 2...Shift register row, 3...Counter, 4...Register row, 5... ...Output gate row, 6...
Pointer shift register column, 7...Column decoder, 8...Transformer 7 assert column, 9...
...output amplifier, IO...transfer lock driver, 11...transfer gate row, 12.
...Word line drive recording control circuit. Page 5, Page 6, Page 7, Mu procedural amendment document, December 1, 1985.

Claims (1)

[Claims] 1. A write register array consisting of a plurality of shift registers connected to one address selection line of a memory cell through a gate; A read register string consisting of a plurality of registers, a plurality of read register strings that control output gates connected to each output of the read register string, and output the outputs of the read registers to a data bus connected to the output gates. a pointer shift register array consisting of a shift register; a counter that counts the number of data input to the write register array and specifies a position of the pointer shift register array based on the counted value; 1. A semiconductor memory device, wherein data input to a column is written into the memory cell, and the data is taken out from the data bus in the order in which the data is written. 2. Storing the activation order of the other address selection line of the memory cell that is activated when writing to the memory cell, and when taking out the contents of the memory cell to the read register, the other address selection line is activated according to the stored activation order. 2. The semiconductor memory device according to claim 1, wherein the address selection line is activated.