JPS61122583U - - Google Patents
Info
- Publication number
- JPS61122583U JPS61122583U JP540385U JP540385U JPS61122583U JP S61122583 U JPS61122583 U JP S61122583U JP 540385 U JP540385 U JP 540385U JP 540385 U JP540385 U JP 540385U JP S61122583 U JPS61122583 U JP S61122583U
- Authority
- JP
- Japan
- Prior art keywords
- gps receiver
- utility
- model registration
- frequency
- code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000037430 deletion Effects 0.000 claims 2
- 238000012217 deletion Methods 0.000 claims 2
- 230000037431 insertion Effects 0.000 claims 2
- 238000003780 insertion Methods 0.000 claims 2
- 230000001105 regulatory effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Position Fixing By Use Of Radio Waves (AREA)
Description
第１図はＧＰＳ受信機のブロツク図、第２図は
第１図における信号処理回路のブロツク図、第３
図はドプラシフト量を示す図、第４図は本案の一
実施例を示す図、第５図はエクスクルーシブオア
回路の動作説明図、第６図は捕捉のためのフロー
チヤート、第７図はＢＰＦの中心周波数を合せる
ためのフローチヤートである。
１…アンテナ、２…ＬＮＡ、３…ＢＰＦ、４…
ミキサ、５…局部発振器、６…中間周波増幅器、
７ａ〜７ｄ…信号処理回路、８…インターフエー
ス、９…コンピユータ。
Figure 1 is a block diagram of the GPS receiver, Figure 2 is a block diagram of the signal processing circuit in Figure 1, and Figure 3 is a block diagram of the signal processing circuit in Figure 1.
The figure shows the amount of Doppler shift, Fig. 4 shows an example of the present invention, Fig. 5 is an explanatory diagram of the operation of the exclusive OR circuit, Fig. 6 is a flowchart for acquisition, and Fig. 7 is a diagram of the BPF. This is a flowchart for matching the center frequency. 1...Antenna, 2...LNA, 3...BPF, 4...
mixer, 5... local oscillator, 6... intermediate frequency amplifier,
7a to 7d...signal processing circuit, 8...interface, 9...computer.
Claims (1)
ＰＮ符号をあらかじめドプラシフト量を算入した
周波数の局部発振器で混合した後に入力信号で混
合器において混合することにより相関をとること
とし、前記局部発振器の周波数をコンピユータに
よりモニタすることを特徴とするＧＰＳ受信機。 ２ 実用新案登録請求の範囲第１項において、前
記混合器を論理回路で構成することを特徴とする
ＧＰＳ受信機。 ３ 実用新案登録請求の範囲第１項において、前
記直列相関回路における帯域フイルタを複数個備
え、各々の帯域を変えておき、コンピユータから
の指令により、スイツチ手段により切替ることと
し、符号捕捉用パルス挿入削除回路におけるパル
ス挿入削除タイミングを変化させることを特徴と
するＧＰＳ受信機。 ４ 実用新案登録請求の範囲第３項において、帯
域フイルタのうち、最も帯域幅の狭いフイルタに
位相変調信号の復調回路を接続したことを特徴と
するＧＰＳ受信機。 ５ 実用新案登録請求の範囲第３項において、帯
域フイルタのうち、最も帯域幅の狭いフイルタ出
力に検波器とそれにつながるアナログデイジタル
変換器を設け、コンピユータにより読み取り、局
部発振器の周波数を変更する手段を有することを
特徴とするＧＰＳ受信機。 ６ 実用新案登録請求の範囲第５項において、符
号同期ループにＶＣＸＯ中心周波数が常に入力の
符号速度の整数倍となるように、追跡以外の状態
の時、カウンタにより、周波数を測定し、デイジ
タル・アナログ変換器および加算器を用いること
により調整することを特徴とするＧＰＳ受信機。[Claims for Utility Model Registration] 1. In a GPS receiver having a serial correlation circuit, correlation is obtained by mixing the PN code with a local oscillator of a frequency that takes into account the amount of Doppler shift in advance, and then mixing it with an input signal in a mixer. , a GPS receiver characterized in that the frequency of the local oscillator is monitored by a computer. 2. The GPS receiver according to claim 1, wherein the mixer is constructed of a logic circuit. 3. In claim 1 of the utility model registration claim, the serial correlation circuit is provided with a plurality of band filters, each having a different band, and is switched by a switch means in accordance with a command from a computer, and the code capturing pulse is A GPS receiver characterized by changing pulse insertion/deletion timing in an insertion/deletion circuit. 4. A GPS receiver according to claim 3 of the utility model registration, characterized in that a phase modulation signal demodulation circuit is connected to a filter with the narrowest bandwidth among the band filters. 5 In claim 3 of the utility model registration claim, a detector and an analog-to-digital converter connected to the detector are provided at the output of the filter with the narrowest bandwidth among the band filters, and a means for reading the output by a computer and changing the frequency of the local oscillator is provided. A GPS receiver comprising: 6 In claim 5 of the utility model registration, in order to ensure that the VCXO center frequency is always an integral multiple of the input code speed in the code-locked loop, the frequency is measured by a counter and digital A GPS receiver characterized in that it is regulated by using an analog converter and an adder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP540385U JPS61122583U (en) | 1985-01-21 | 1985-01-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP540385U JPS61122583U (en) | 1985-01-21 | 1985-01-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61122583U true JPS61122583U (en) | 1986-08-01 |
Family
ID=30481880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP540385U Pending JPS61122583U (en) | 1985-01-21 | 1985-01-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61122583U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03181875A (en) * | 1989-12-12 | 1991-08-07 | Pioneer Electron Corp | Satellite signal pick-up system of gps receiver |
| JPH07260919A (en) * | 1995-02-13 | 1995-10-13 | Furuno Electric Co Ltd | Receiver for position measurement signal |
| JP2008107219A (en) * | 2006-10-26 | 2008-05-08 | Seiko Epson Corp | Positioning device, electronic device, and program |
-
1985
- 1985-01-21 JP JP540385U patent/JPS61122583U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03181875A (en) * | 1989-12-12 | 1991-08-07 | Pioneer Electron Corp | Satellite signal pick-up system of gps receiver |
| JPH07260919A (en) * | 1995-02-13 | 1995-10-13 | Furuno Electric Co Ltd | Receiver for position measurement signal |
| JP2008107219A (en) * | 2006-10-26 | 2008-05-08 | Seiko Epson Corp | Positioning device, electronic device, and program |
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