JPS61120455A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61120455A JPS61120455A JP24064284A JP24064284A JPS61120455A JP S61120455 A JPS61120455 A JP S61120455A JP 24064284 A JP24064284 A JP 24064284A JP 24064284 A JP24064284 A JP 24064284A JP S61120455 A JPS61120455 A JP S61120455A
- Authority
- JP
- Japan
- Prior art keywords
- light
- substrate
- signal processing
- chips
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000011796 hollow space material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 150000001875 compounds Chemical class 0.000 abstract description 2
- 230000008054 signal transmission Effects 0.000 abstract description 2
- 230000005611 electricity Effects 0.000 abstract 1
- 230000006698 induction Effects 0.000 abstract 1
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 7
- 239000012212 insulator Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
- H01L31/16—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Led Devices (AREA)
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、ウニ−ハスケーブル−インテグレーションに
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to sea urchin hub cable integration.
ＬＳＩチップに含まれる多数のバンドから、セラミック
基板に配線するために、■ＥＥＥ、 、Ｔｒａｎｓ。■EEE, Trans.
ｏｎ、 Ｃｏｍｐｏｎｅｎｔｓ、 ＨｙＢｒｉｄｓ、
ａｎｄ ＭａｎｎｆａｃｔｕｒｉｎｇＴｅｃｈｎｏｌｏ
ｇｙ、 ｖｏｌ、 ＣＨＭＴ−６，扁２． ’ｒＮＮＥ
１９８３０図１４に示すように、セラミック基板内に
配線を形成する方法が提案されている。この方法は、チ
ップの大型化に伴ない利用され始める技術であるが、二
次元平面でチップ間配線を行なうので、回路スピードの
点で制限を受ける。on, Components, HyBrids,
and Mannfactoring Technology
gy, vol, CHMT-6, Bian 2. 'rNNE
19830 As shown in FIG. 14, a method of forming wiring within a ceramic substrate has been proposed. This method is a technology that is beginning to be used as chips become larger, but since inter-chip wiring is performed on a two-dimensional plane, it is limited in terms of circuit speed.
本発明は、ＬＳＩチップ（あるいはウェーハ）間の情報
伝達を垂直方向に行なわせることによシ、信号処理効率
を向上させるものである。The present invention improves signal processing efficiency by vertically transmitting information between LSI chips (or wafers).
重ね合わせたＬＳＩチップ（あるいはウェーハ）間の接
続を電気的に行なわせる場合、多数の配線束を均一にバ
ンドと接続することを、機械的に難しい。また、テップ
（ウェーハ）で発生する熱を逃す為には、チップ間に介
在する物質は金属であることが望ましい。−万、チップ
（ウェーハ）間の通信に光を用いれば、上記の問題を一
挙に教法することができる。When electrical connections are made between stacked LSI chips (or wafers), it is mechanically difficult to uniformly connect a large number of wiring bundles to bands. Furthermore, in order to release the heat generated by the chips (wafers), it is desirable that the material interposed between the chips be metal. - If light is used for communication between chips (wafers), the above problems can be solved all at once.
以下、本発明の実施例を第１図を用いて説明する。同図
は、素子の断面図を示しである。Embodiments of the present invention will be described below with reference to FIG. This figure shows a cross-sectional view of the element.
図中、１はＳｉ半導体基板、２および４は、信号処理回
路（演算回路、メモリー等）でおり、３゜５は発光素子
である。３．５の発光素子は、各々２．４からの信号を
光に変換し、その光は基板１の下方に放射される。３，
５の下部は、光が下方に透過し易い様に、基板１の厚さ
を薄くしであるが、基板１が薄ければ特に薄くする必要
はない。In the figure, 1 is a Si semiconductor substrate, 2 and 4 are signal processing circuits (arithmetic circuit, memory, etc.), and 3.5 is a light emitting element. The light emitting elements 3.5 each convert the signal from 2.4 into light, and the light is emitted below the substrate 1. 3,
The thickness of the substrate 1 is made thinner at the lower part of the substrate 5 so that light can easily pass downward, but there is no need to make it particularly thin if the substrate 1 is thin.
６は、熱伝導率の高い物質（例えば、 Ａｔ。6 is a material with high thermal conductivity (for example, At.
Ｃｒ、Ｗ、Ｎｉ等の金属）で形成され、７，８は、発光
素子、３，５からの光を通す為に、中空にしである。7 and 8 are hollow to allow light from the light emitting elements 3 and 5 to pass through.
６を通って来た光信号は、Ｓｉ半導体基板、９内に形成
した受光素子、１１．１３で光電変換を行ない、その電
気信号は、１０．１２の信号処理回路（演算回路、メモ
リー等）に入力される。The optical signal that has passed through 6 undergoes photoelectric conversion at the Si semiconductor substrate, the photodetector formed in 9, and 11.13, and the electrical signal is sent to the signal processing circuit (arithmetic circuit, memory, etc.) at 10.12. is input.
特に発光素子である３、５は、Ｓｉでは実現できないの
で、■−■化合物（例えば、ＧａＡＳ系）をＭＢ Ｅ
（Ｍｏｌｅｃａｌａｒ Ｂｅａｍ ｇ、ｐｉｔａｘｙ）
＠るいは、ＭＯＣＶＤ（Ｍｅｔａｌ Ｑｒｇａｎｉ
ｃ ＣｈｅｍｉｃａｌＶａｐｏｕｒ Ｄｅｐｏｓｉｔｉ
ｏｎ）法で形成すればよい。In particular, the light-emitting elements 3 and 5 cannot be realized with Si, so a ■-■ compound (e.g., GaAS type) is used as MBE.
(Molecal Beam g, pitaxy)
@ Ruiha, MOCVD (Metal Qrgani
c Chemical Vapor Deposit
on) method.
１．６．９の基板は加工された後、接着用樹脂で接着す
る。この時、１，６．９の合わせは、１および９を動作
させながら位置合わせが行なえるので、特に合せマーク
は不要となる。金属体、６は、基板１，９で発生する熱
を外部に吸収できる。After the substrate of 1.6.9 is processed, it is bonded with adhesive resin. At this time, alignment of 1 and 6.9 can be performed while operating 1 and 9, so no alignment mark is particularly required. The metal body 6 can absorb heat generated by the substrates 1 and 9 to the outside.
以上の説明では、３．５を発光素子、１１゜１３を受光
素子としたが、その逆であってもよい。In the above description, 3.5 is the light emitting element and 11.degree. 13 is the light receiving element, but the opposite may be used.
また、基板９内に、発光素子、受光素子を含ませること
によシ、チップ（ウエーノＳ）の多段接続が可能である
。Further, by including a light emitting element and a light receiving element in the substrate 9, it is possible to connect chips (Weno S) in multiple stages.
第２゛図は、第１図の基板１あるいは９に対する平面図
を示す。３ｉ半導体基板２１内に配置された２２．２４
は信号処理回路であり、２６．２７の配線を介して、２
３．２５の発光（あるいは受光）素子につながる。２２
．２４は、素子内配線２８．２９によって相互につなが
っている。FIG. 2 shows a plan view of the substrate 1 or 9 of FIG. 22.24 arranged in the 3i semiconductor substrate 21
is a signal processing circuit, and 2 is connected via wiring 26.27.
3.25 is connected to the light emitting (or light receiving) element. 22
．． 24 are connected to each other by intra-device wirings 28 and 29.
本実施例では、ヒートシンクの作用を確実にするために
、第１図の６の材料は金属としたが、発生熱量が小さい
場合には、半導体、絶縁体でもよく、さらには省略して
もよい。In this embodiment, the material 6 in Fig. 1 is made of metal in order to ensure the function of the heat sink, but if the amount of heat generated is small, it may be made of a semiconductor or an insulator, or may even be omitted. .
本発明の別の実施例を第３図に示す。同図において、３
１〜４０．４２は、第１図における１〜１０．１２と同
じものである。本実施例では、基板３９とに、４０．４
２につながる電極板、４５゜４６を形成し、その上に光
導電膜４７を、さらにその上に透明電極板４８を形成し
たものである。Another embodiment of the invention is shown in FIG. In the same figure, 3
1 to 40.42 are the same as 1 to 10.12 in FIG. In this embodiment, the substrate 39 is 40.4
2, a photoconductive film 47 is formed thereon, and a transparent electrode plate 48 is further formed thereon.
４４は絶縁物である。例えば、４４はＳｉｎ、。44 is an insulator. For example, 44 is Sin.
４５．４６は人ｔ１４７はアモルファス５ｉあるいは３
ｅ系光電変換膜等、４８としてはＩＴＯ（インジウム、
ティン、オキサイド）を用いればよい。本実施例では、
基板３９上面に受光部を形成できるので、信号処理回路
４０．４２の面積が大きくとれ、また、光の利用率が向
上し、チップ（あるいはウェーハ）間の位置合せが容易
になる。45.46 is human t147 is amorphous 5i or 3
e-based photoelectric conversion film, etc., 48 is ITO (indium,
Tin, oxide) may be used. In this example,
Since the light receiving section can be formed on the upper surface of the substrate 39, the area of the signal processing circuits 40 and 42 can be increased, the efficiency of light utilization is improved, and alignment between chips (or wafers) is facilitated.
なお、５０は、電極４８の電圧が基板３１の電圧と異な
る場合に用いる絶縁物であり、基板３１の裏面の酸化膜
を代用しても良いし、あるいは、金属３６の上面を酸化
、おるいは絶縁膜をコーティングしても良い。Note that 50 is an insulator used when the voltage of the electrode 48 is different from the voltage of the substrate 31, and the oxide film on the back surface of the substrate 31 may be used instead, or the upper surface of the metal 36 may be oxidized or may be coated with an insulating film.
本発明によれば、複数枚重ねたチップ（あるいはウェー
ハ）間の信号伝達を光によシ行なうので、信号処理効率
が向上する。また、チップ（ウェーハ）間は電気的に分
離されているので、素子内で発生する雑音の誘導を受け
ず、信頼度の高い情報伝達が可能となる。光導波路とし
て用いる金属体は、静電シールドを兼ね、熱吸収を効率
良く行なえる。According to the present invention, signal transmission between a plurality of stacked chips (or wafers) is carried out by light, so signal processing efficiency is improved. Furthermore, since the chips (wafers) are electrically isolated, they are not influenced by noise generated within the elements, allowing highly reliable information transmission. The metal body used as the optical waveguide also serves as an electrostatic shield and can efficiently absorb heat.
第１図は本発明の実施例の素子の断面図、第２図はその
平面図、第３図は本発明の別の実施例に対する素子の断
面図を示す。
１・・・Ｓｉ半導体基板、２・・・信号処理回路、３・
・・発第 １ 図
ｆＪＺ 図
第３図FIG. 1 is a sectional view of an element according to an embodiment of the invention, FIG. 2 is a plan view thereof, and FIG. 3 is a sectional view of an element according to another embodiment of the invention. DESCRIPTION OF SYMBOLS 1... Si semiconductor substrate, 2... Signal processing circuit, 3...
・・Departure No. 1 Figure fJZ Figure 3
Claims (1)
を含み、第２の半導体基板内に、少なくとも１個の受光
素子を含み、第１の半導体基板と第２の半導体基板との
間に、該発光素子と該受光素子とをむすぶ線を中空で囲
んだ金属板を配置することを特徴とする半導体装置。1. At least one light emitting element is included in the first semiconductor substrate, at least one light receiving element is included in the second semiconductor substrate, and between the first semiconductor substrate and the second semiconductor substrate A semiconductor device characterized in that a metal plate is disposed in which a line connecting the light emitting element and the light receiving element is surrounded by a hollow space.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24064284A JPS61120455A (en) | 1984-11-16 | 1984-11-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24064284A JPS61120455A (en) | 1984-11-16 | 1984-11-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61120455A true JPS61120455A (en) | 1986-06-07 |
Family
ID=17062532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24064284A Pending JPS61120455A (en) | 1984-11-16 | 1984-11-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61120455A (en) |
-
1984
- 1984-11-16 JP JP24064284A patent/JPS61120455A/en active Pending
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