JPS61116450U - - Google Patents
Info
- Publication number
- JPS61116450U JPS61116450U JP19660984U JP19660984U JPS61116450U JP S61116450 U JPS61116450 U JP S61116450U JP 19660984 U JP19660984 U JP 19660984U JP 19660984 U JP19660984 U JP 19660984U JP S61116450 U JPS61116450 U JP S61116450U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- sweep signal
- phase
- locked loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
Description
第１図は本発明の一実施例における自動周波数
制御装置の構成を示す回路ブロツク図、第２図は
同装置の作用説明は用いるための信号波形図、第
３図は従来の自動周波数制御回路の構成を示す回
路ブロツク図、第４図は同装置の作用説明に用い
る信号波形図である。
１……高周波増幅器、２……中間周波増幅器、
３……パイロツト信号抽出用の狭帯域フイルタ、
４……水晶発振器、５……位相比較器、６……ル
ープフイルタ、７……電圧保持回路、８……電圧
制御発振器、９……周波数変換器、１０……掃引
信号発生回路、１１……スイツチ回路、１２……
加算回路、１３……振幅可変回路、１４……加算
回路、ＲＳ……受信波、ＰＳ……パイロツト信号
、ＨＳ……ホールド信号、ＣＳ……制御信号、Ｓ
Ｓ……掃引信号、ＳＳ１……振幅が可変された掃
引信号、ＳＳ２……保持電圧に重畳後の掃引信号
。
Fig. 1 is a circuit block diagram showing the configuration of an automatic frequency control device according to an embodiment of the present invention, Fig. 2 is a signal waveform diagram for explaining the operation of the device, and Fig. 3 is a conventional automatic frequency control circuit. FIG. 4 is a signal waveform diagram used to explain the operation of the device. 1...High frequency amplifier, 2...Intermediate frequency amplifier,
3...Narrowband filter for pilot signal extraction,
4... Crystal oscillator, 5... Phase comparator, 6... Loop filter, 7... Voltage holding circuit, 8... Voltage controlled oscillator, 9... Frequency converter, 10... Sweep signal generation circuit, 11... ...Switch circuit, 12...
Adding circuit, 13... Amplitude variable circuit, 14... Adding circuit, RS... Received wave, PS... Pilot signal, HS... Hold signal, CS... Control signal, S
S...Sweep signal, SS1 ...Sweep signal with variable amplitude, SS2 ...Sweep signal after being superimposed on the holding voltage.
Claims (1)
るパイロツト信号と自己の基準信号との位相差が
一定になるように位相同期動作を行ない、これに
より受信波の基準周波数信号を得る自動周波数制
御装置において、所定周波数の掃引信号を発生す
る掃引信号発生回路と、前記位相同期ループで同
期外れが発生したときこの同期外れが発生する直
前のループ電圧を保持する電圧保持回路と、前記
同期外れの発生後前記掃引信号発生回路から発生
される掃引信号を所定のレベルから徐々に増加さ
せる振幅可変回路と、この振幅可変回路から出力
された掃引信号を前記電圧保持回路で保持された
ループ電圧に重畳させて得られる電圧をループ電
圧として前記位相同期ループの電圧制御発振器に
供給する加算回路とを具備したことを特徴とする
自動周波数制御装置。 (2) 同期外れが発生した時点からパイロツト信
号が再来するまでに相当する期間を経過したのち
、振幅可変回路および加算回路は、掃引信号の振
幅の増加および位相同期ループの電圧制御発振器
への供給をそれぞれ開始するものである実用新案
登録請求の範囲第(1)項記載の自動周波数制御装
置。 (3) 同期外れが発生した時点から、振幅可変回
路および加算回路は、掃引信号の振幅の増加およ
び位相同期ループの電圧制御発振器への供給をそ
れぞれ開始するものである実用新案登録請求の範
囲第(1)項記載の自動周波数制御装置。[Claims for Utility Model Registration] (1) It is equipped with a phase-locked loop and performs phase-locking operation so that the phase difference between the pilot signal sent from the transmitting station and its own reference signal is constant, thereby An automatic frequency control device that obtains a reference frequency signal includes a sweep signal generation circuit that generates a sweep signal of a predetermined frequency, and a voltage that maintains the loop voltage immediately before synchronization occurs when synchronization occurs in the phase-locked loop. a holding circuit; an amplitude variable circuit that gradually increases the sweep signal generated from the sweep signal generation circuit from a predetermined level after the occurrence of the synchronization loss; and a voltage holding circuit that applies the sweep signal output from the amplitude variable circuit to the voltage holding circuit. 1. An automatic frequency control device comprising: an addition circuit that supplies a voltage obtained by superimposing the voltage held on the loop voltage held by the voltage controlled oscillator as a loop voltage to a voltage controlled oscillator of the phase-locked loop. (2) After a period corresponding to the time when the synchronization occurs until the pilot signal reappears, the amplitude variable circuit and addition circuit increase the amplitude of the sweep signal and supply it to the voltage controlled oscillator of the phase-locked loop. The automatic frequency control device according to claim (1) of the utility model registration claim, which starts each of the following. (3) From the moment when synchronization occurs, the amplitude variable circuit and the adder circuit start increasing the amplitude of the sweep signal and starting supplying the sweep signal to the voltage controlled oscillator of the phase-locked loop. The automatic frequency control device described in paragraph (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19660984U JPS61116450U (en) | 1984-12-28 | 1984-12-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19660984U JPS61116450U (en) | 1984-12-28 | 1984-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61116450U true JPS61116450U (en) | 1986-07-23 |
Family
ID=30754425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19660984U Pending JPS61116450U (en) | 1984-12-28 | 1984-12-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61116450U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06204863A (en) * | 1993-01-06 | 1994-07-22 | Sony Corp | Pll circuit |
-
1984
- 1984-12-28 JP JP19660984U patent/JPS61116450U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06204863A (en) * | 1993-01-06 | 1994-07-22 | Sony Corp | Pll circuit |
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