JPS61114337A - Floating point multiplier - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution at an exponent part by providing a switch circuit to an adder circuit and therefore omitting an adder circuit for addition of '-1'. CONSTITUTION:A floating point multiplier is provided with a multiplication circuit part 1, an adder circuit part 2 and a normalization processing part 3. The circuit 2 includes switch circuits 26 and 27. These circuits 26 and 27 supply input signals 103 and 104 of an exponent part and deliver them to an adder circuit 22. Then a signal 114 of '-1' is delivered together with a signal 111 of the result of addition obtained before normalization which equals to the output of the circuit 22 in case a decision signal 108 delivered from a shift signal output circuit 25 shows that a signal 107 showing the result of multiplica tion of the part 1 is not normalized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a multiplication circuit unit that multiplies mantissa parts, an addition circuit unit that adds exponent parts, and a method based on calculation results of the multiplication circuit unit and the addition circuit unit. A floating point multiplier consisting of a normalization processing section that performs normalization processing on the mantissa.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional example of this type of floating point multiplier. The multiplication circuit section 1 receives mantissa input signals 101 and 102, multiplies the mantissa parts, and generates a signal indicating the multiplication result. 1
Outputs 07. Adder circuit section 2 includes adder circuits 21 and 2.
2. It is composed of an overflow/underflow detection circuit 26, an overflow/underflow processing circuit 24, and a shift signal output circuit 25i. Exponent input signal 1
06 and 104 are input to the adder circuit 21, and the exponent parts are added. The addition result signal 110 output from the adder circuit 21 is added to another adder circuit 22 (by two people).

The shift signal output circuit 25 inputting the signal 107 outputs the signal 1
07 is normalized, and outputs the judgment signal 108 to the adder circuit 22 and the shift processing circuit 61 of the normalization processing section 3 (two outputs).

The addition circuit 22 which has added the addition result signal 110 and the judgment signal 108 adds the signal 11o (20) according to the judgment signal 108 when the signal 107 is normalized, and adds the signal 11o (20) when the signal 107 is not normalized. Sometimes the signal f101:
, -1 and outputs the normalized addition signal 111 to the overflow/underflow detection circuit 26 and the overflow/underflow processing circuit 24 (two outputs).

The overflow/underflow detection circuit 26 inputting the addition signal 111 determines whether the addition signal 111 is outside a predetermined range, that is, whether it is an overflow or underflow, and outputs the determination signal 112.
is output from the overflow/underflow processing circuits 24 and 62 (=output. The normalization processing section 6 is connected to the shift processing circuit 3
1 and the overflow/underflow processing circuit 62 becomes. The shift processing circuit 31 that receives the multiplication result signal 107 and the judgment signal 108 normalizes the multiplication result signal 107, that is, shifts the multiplication result signal 107 using the judgment signal 108.
The signal 109 of the normalized multiplication result is overflowed.
Underflow processing circuit 62 (two outputs).

Overflow/underflow processing circuits 24 and 6
2 is the output signal 1 when the signal 111 is overflowing or underflowing from the judgment signal 1120.
From 05 and 106 overflow underflow a-
When the signal is output and there is no overflow or underflow (= is the output signal 105 and 106)
output signals 109 and 111, respectively.

[Problem that the invention seeks to solve]

The problem was that a second adder was required, which increased the hard fair.

Therefore, it is an object of the present invention to provide a floating point multiplier that can eliminate the adder for normalization and has a smaller hardware scale than the conventional one.

[Means for solving problems]

The floating point multiplier according to the present invention manually inputs the second exponent part input signal and outputs it to the adder circuit, and if the multiplication result in the multiplier circuit section is not normalized, the floating point multiplier according to the present invention The adder circuit section includes first and second switching circuits that output the signal of the addition result before normalization, which is the output of the adder circuit, to the adder circuit;
This eliminates the need for an adder circuit (adder circuit 22 in FIG. 2) for adding -1.

(Example〕 Embodiments of the present invention will be described with reference to the drawings.

No. 111 is a block diagram showing an embodiment of a floating point multiplier according to the present invention.

The floating point multiplier of this embodiment differs from the conventional example shown in FIG. If 108 indicates that the signal 107 indicating the multiplication result in the multiplication circuit section l is not normalized, then the at signal 1 of -1'' is also applied.
14. Switching circuits 26 and 27 are provided to output the signal 111 of the addition result before normalization, which is the output of the addition circuit 22. ' The operation of this embodiment is the same as the conventional example shown in FIG.

〔Effect of the invention〕

Unnecessary (the circuit of the 2-digit exponent part can be simplified).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a floating point multiplier according to the present invention, and FIG. 2 is a block diagram showing a conventional example of a floating point multiplier. 1: Multiplication circuit section, 2: Addition circuit section, 3: Normalization processing section, 22: Addition circuit, 25; Shift signal output circuit, 26.27: Switching circuit, 103.104: Exponent part input signal, 108: Judgment Signal, 111: Signal of addition result, 1
14: -1'' signal.

Claims (1)

[Scope of Claims] A multiplication circuit unit that multiplies the mantissa part, an addition circuit unit that adds the exponent part, and a normalization processing unit that normalizes the mantissa part from the calculation results of the multiplication circuit unit and the addition circuit unit. In the floating point multiplier, the first and second exponent part input signals are respectively inputted and outputted to the adder circuit, and if the multiplication result in the multiplier circuit section is not normalized, each of the floating point multipliers receives "-1". ” signal,
A floating point multiplier, characterized in that the adder circuit section includes first and second switching circuits that output a signal of the addition result before normalization, which is an output of the adder circuit, to the adder circuit.