JPS61113194A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS61113194A
JPS61113194A JP59233814A JP23381484A JPS61113194A JP S61113194 A JPS61113194 A JP S61113194A JP 59233814 A JP59233814 A JP 59233814A JP 23381484 A JP23381484 A JP 23381484A JP S61113194 A JPS61113194 A JP S61113194A
Authority
JP
Japan
Prior art keywords
channel mos
mos transistor
ion implantation
rom
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59233814A
Other languages
Japanese (ja)
Inventor
Fumito Kawamura
川村　文人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59233814A priority Critical patent/JPS61113194A/en
Publication of JPS61113194A publication Critical patent/JPS61113194A/en
Pending legal-status Critical Current

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  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To read the identification number of a ROM with the aid of the conduction start voltage of a serial connection circuit by installing a circuit where a resistance element, a P-channel MOS transistor and an N-channel MOS transistor are serially connected. CONSTITUTION:According as ion implantation is carried out or not, the resistance element 5 changes a resistance value in question to a certain resistance value or infinity. According as the ion implantation is executed or not, transistors 3 and 4 change thresholds of the P-channel MOS transistor 4 and the N-channel MOS transistor 3 to VT1P, VT2P, VT1N or VT2N. If the ion implantation causes either the P-channel MOS transistor 4 or the N-channel MOS transistor 3 to be depression-type transistor, VT2NorP is assumed to equal 0V. by utilizing that five types of conduction start voltages can be obtained between terminals 1 and 2, the ROM code number is recognized in quinary.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路装置に関し、特にイオン注入
により記憶内容を書き込む几ＯＭｔ有する半導体集積回
路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit having an OMt in which memory contents are written by ion implantation.

〔従来の技術〕[Conventional technology]

従来、イオン注入により記憶内容を書き込むＲＯＭを有
する半導体集積回路装置において、前記ＲＯＭの識別番
号の読み出しは、外観では不可能であるのでチェック用
トランジスタを用いて、１０進法での１クタ認識するの
に、４コのトランジスタを使って認識している。つまり
、各々のトランジスタをデプレクシ、／形トランジスタ
にするか、否かによって２進法で認識するというもので
ある。テプレノション形トラ７ジスタになっておｎば、
ゲートとソースを接地した状態でドレイ／に電圧を加え
ることによって、このトランジスタは導通状態となる。Conventionally, in a semiconductor integrated circuit device having a ROM in which memory contents are written by ion implantation, it is impossible to read the identification number of the ROM by looking at the outside, so a check transistor is used to recognize the identification number in decimal notation. However, it is recognized using four transistors. In other words, each transistor is recognized using a binary system depending on whether it is a deplexer or / type transistor. If you become a teplenotion type tiger 7 dista,
The transistor becomes conductive by applying a voltage to the drain with the gate and source grounded.

このことを利用しているのである。This is what they are taking advantage of.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した４個のトランジスタを使い２進法で認識すると
いう従来のＲＯＭの識別番号の読み出し方法は、４回の
測定を必要とし、測定回数が多すぎるという不便な欠点
があった。The conventional method of reading the identification number of a ROM, which uses four transistors and performs binary recognition, requires four measurements, which is an inconvenient drawback in that the number of measurements is too large.

この発明は、イオン注入により記憶内容を書き込むＲＯ
Ｍ　を有する半導体集積回路装置において、前記ＲＯＭ
の識別番号を従来より少ない測定回数で、読み出す事を
可能とする半導体集積回路装置を提供することを目的と
する。This invention is an RO that writes memory contents by ion implantation.
In the semiconductor integrated circuit device having M, the ROM
An object of the present invention is to provide a semiconductor integrated circuit device that can read out the identification number of a person with fewer measurements than conventional ones.

〔問題点を解決するための手段〕[Means for solving problems]

この発明の半導体集積回路装置は、イオノ注入により記
憶内容を書き込むＲＯＭを有する半導体集積回路装置に
おいて、抵抗素子とＰチャネル形ＭＯＳトランジスタと
Ｎチャネル形ＭＯＳトランジスタを直列接続した回路を
有し、前記直列接続回路の導通開始電圧により、前記孔
ＯＭの識別番号の読み出しを可能とした事を特徴として
構成される。A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a ROM in which memory contents are written by ion implantation, and includes a circuit in which a resistance element, a P-channel MOS transistor, and an N-channel MOS transistor are connected in series. The structure is characterized in that the identification number of the hole OM can be read out based on the conduction start voltage of the connecting circuit.

〔実施例〕〔Example〕

以下、この発明の実施例につき、図面を参照して説明す
る。第１図は、この発明の一実施例を説明するための回
路図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram for explaining one embodiment of the present invention.

第１図において、１及び２はそｎぞれ端子ｌ及び端子２
である。また３はＮチャネルＭＯＳトランジスタ、４は
Ｐチャネル間Ｏ８）ランジスタ、５は抵抗であり、抵抗
５とＰチャネル間Ｏ８トランジスタ４とＮチャネルＭＯ
ＳＦう７−）−スタ３は直列接続されている。また３と
４のトランジスタにおいては、ゲートとドレイ／及びソ
ースとサブストレートラそれぞれ接続する。In FIG. 1, 1 and 2 are terminal l and terminal 2, respectively.
It is. 3 is an N-channel MOS transistor, 4 is a P-channel O8) transistor, and 5 is a resistor between the resistor 5 and P-channel O8 transistor 4 and N-channel MOS transistor.
The SF7-)-stars 3 are connected in series. In transistors 3 and 4, the gate and drain/and the source and substrate are connected, respectively.

抵抗素子においては、イオン注入を行うか否かによって
、抵抗値をある一定の抵抗値か無限大かに変化させる。In a resistor element, the resistance value changes from a certain resistance value to an infinite value depending on whether ion implantation is performed or not.

トランジスタにおいては、トランジスタのゲート領域に
イオノ注入を行うか否かによって、Ｐチャネル間Ｏ８ト
ランジスタとＮチャネルＭＯＳトランジスタノ閾値ｔＶ
ＴｔｐカＶｔｚｐ　　＋　ＶｒｘＮカＶＴ２Ｎに変化さ
せる。In transistors, the threshold value tV between the P-channel O8 transistor and the N-channel MOS transistor depends on whether or not ion implantation is performed in the gate region of the transistor.
Change Ttp to Vtzp + VrxN to VT2N.

第１図において端子１に電圧を加えていき、端子ｌと端
子２０間での導通開始時の端子ｌに加えた電圧を測定す
る。In FIG. 1, a voltage is applied to the terminal 1, and the voltage applied to the terminal 1 when conduction between the terminal 1 and the terminal 20 starts is measured.

端子１と端子２との間の導通開始電圧は％　ＩＶＴＩＰ
Ｉ＋　ＩＶＴＩＮＩ　ｌ　ｌ　ＶＴ２Ｐ　ｌ＋　ＩＶＴ
ＩＮＩ　、　ＩＶＴＩＰＩ＋１ＶＴ２Ｎ　ｌ　、　ＩＶ
Ｔ２Ｐｌ＋ＩＶ７２Ｎ＋　、　無ｔｓ犬ト５種類できる
。この時、イオン注入を行うことによって、Ｐチャネル
間Ｏ８）う／ジスタ、ＮチャネルＭＯＳ）ラノジスタの
どちらかデプレクショノ形トラ７ジスタになる場合はＶ
　Ｔ２Ｎ　ｏｒ　Ｐ　”　ＯＶとする。The conduction start voltage between terminal 1 and terminal 2 is % IVTIP
I+ IVTINI l l VT2P l+ IVT
INI, IVTIPI+1VT2Nl, IV
T2Pl+IV72N+, 5 types of non-TS dogs are available. At this time, by performing ion implantation, if either the P-channel MOS transistor or the N-channel MOS transistor becomes a depletion type transistor, V
T2N or P” OV.

もこの端子ｌと端子２の間の導通開始電圧が５種類でき
ることを利用してＲＯＭコード番号の認識を５進法で行
う。Also, by utilizing the fact that there are five types of conduction start voltage between terminal 1 and terminal 2, the ROM code number is recognized in quinary notation.

よって、ＲＯＭコード番号を１０進法による１ケタ認識
するのに、第１図の回路を２個必要とすることがわかる
。Therefore, it can be seen that two circuits shown in FIG. 1 are required to recognize a single digit ROM code number in decimal notation.

なお上述の実施例においては、ＲＯＭ識別番号が１０進
法での１ケタの場合についてのＲＯＭ識別番号の読み出
し方法であるが一般にＲＯＭ識別番号ｔｌｏ進法でのＮ
ケタ（任意の整数）で指定する場合についても、図１に
示す回路ｆ　Ｎ　／　４ｏｇ１ｏ５の小数点以下〈りあ
げの整斂ケ製造することによって同様の効果が得られる
。In the above embodiment, the ROM identification number is read in the case where the ROM identification number is a single digit in decimal system, but in general, the ROM identification number is N in tlo system.
Even in the case of specifying in digits (arbitrary integers), the same effect can be obtained by manufacturing the circuit f N /4og1o5 shown in FIG.

また図１に示している回路において、ＰチャネルＭＯＳ
トランジスタとＮチャネルＭＯＳトラ７ジスタと抵抗素
子の接続順番を変えても同様の効果が得られる。Furthermore, in the circuit shown in FIG.
A similar effect can be obtained by changing the connection order of the transistor, N-channel MOS transistor, and resistor.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、イオン注入によ
り記憶内容を書き込むＲＯＭ　１ｒ−有する半導体集積
回路装置において、ＲＯＭ識別番号を、従来方法よりも
、少ない測定回数で認識できる。As described above, according to the present invention, in a semiconductor integrated circuit device having a ROM 1r- to which memory contents are written by ion implantation, the ROM identification number can be recognized with fewer measurements than in the conventional method.

つまｌ）、ＲＯＭコード番号が、１０進法での１ケタの
番号で指定するものならば、従来方法によｎば４回の測
定を要するが、この実施例によれば２回の測定で認識で
き、従来より少ない測定回数で、読み出す事を可能にで
きるという効果がある。In other words, if the ROM code number is specified by a single digit number in decimal notation, four measurements would be required using the conventional method, but with this embodiment, only two measurements would be required. It has the effect of being able to be recognized and read out with fewer measurements than conventional methods.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を説明するための回路図であ
る。 ｌ・・・・・・端子１．２・・・・・・端子２．３・・
・・・・ＮチャネルＭＯＳトランジスタ、４・・・・・
・ＰチャネルＭＯＳトラ／ジスメ、５・・・・・・抵抗
。 姥冬／ 鴻す２FIG. 1 is a circuit diagram for explaining one embodiment of the present invention. l...Terminal 1.2...Terminal 2.3...
...N-channel MOS transistor, 4...
・P channel MOS transistor/jisume, 5...Resistance. Ubafuyu / Kosu 2

Claims (1)

【特許請求の範囲】[Claims] 　イオン注入により記憶内容を書き込むＲＯＭを有する
半導体集積回路装置において、抵抗素子とＰチャネル形
ＭＯＳトランジスタとＮチャネル形ＭＯＳトランジスタ
を直列接続した回路を有し、前記直列接続回路の導通開
始電圧により、前記ＲＯＭの識別番号の読み出しを可能
とした事を特徴とする半導体集積回路装置。A semiconductor integrated circuit device having a ROM in which memory contents are written by ion implantation includes a circuit in which a resistive element, a P-channel MOS transistor, and an N-channel MOS transistor are connected in series, and the conduction start voltage of the series-connected circuit causes the A semiconductor integrated circuit device characterized in that it is possible to read an identification number of a ROM.
JP59233814A 1984-11-06 1984-11-06 Semiconductor integrated circuit device Pending JPS61113194A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59233814A JPS61113194A (en) 1984-11-06 1984-11-06 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59233814A JPS61113194A (en) 1984-11-06 1984-11-06 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS61113194A true JPS61113194A (en) 1986-05-31

Family

ID=16960993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59233814A Pending JPS61113194A (en) 1984-11-06 1984-11-06 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS61113194A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62298999A (en) * 1986-06-18 1987-12-26 Matsushita Electric Ind Co Ltd Semiconductor memory device
US8407656B2 (en) 2011-06-24 2013-03-26 International Business Machines Corporation Method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62298999A (en) * 1986-06-18 1987-12-26 Matsushita Electric Ind Co Ltd Semiconductor memory device
US8407656B2 (en) 2011-06-24 2013-03-26 International Business Machines Corporation Method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range

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