JPS61112429A - Logic circuit - Google Patents

Abstract

PURPOSE:To realize an optional logical equation with one kind of cell and inverter by using a logical gate having four inputs and whose output shown H,L levels and high impedance depending on the combination of the inputs. CONSTITUTION:The midpoint X of CMOS FETs (M13, M14, M29, M30) and CMOS FET of the same polarity (M15, M16, M31, M32) is connected mutually. In this circuit connection tri-state (H, L levels and high impedance) is obtained by two input signals. Since an optional logic such as AND or OR is obtained depending on the combination of inputs, a full adder is constituted and the power consumption is reduced because of the adoption of CMOS.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a high-speed, low-power consumption logic circuit suitable for integrated circuits in general.

[Background of the invention]

With the recent increase in the speed of integrated circuits for digital arithmetic operations, there is a desire to increase the speed of full adder circuits, which are the most basic components of arithmetic operation circuits.

As a method suitable for increasing the speed of the full adder circuit, the sum output S0 is generated by switching two of the three inputs A, B, and C to the full adder circuit, and the carry output is generated by switching B and C. Algorithms for generating C0 have been known for some time. This can be expressed as a logical formula as follows.

Sum output 50=x-c+x-c Carry output C0=X-C+X-B X:A+B Regarding the reason why the circuit using this algorithm is fast,
A conventional example will be described below. FIG. 1(a) is a diagram showing a conventional example (ICCC'82P151-P2S5) of a full adder circuit, in which MOS transistors M1 to M4 are connected to A and B.
The inverter N1 constitutes a partial circuit that generates the exclusive NOR X of

MOS transistors M5 to M8 constitute a partial circuit that generates the exclusive NOR of X and C, and the inverter N2 is a 6M0S that generates the exclusive logic of X and C, that is, the sum output S0, by taking the NOR. Transistor M9~
M12 is a partial circuit configured as a transmission gate that generates a carry output. This partial circuit controls whether to pass the signal C or the signal B to the node L1 using X and X.

Inverter N3 generates carry output C0 by negating the signal at node L1.

FIG. 1(b) is a diagram illustrating a partial circuit that generates the carry output shown in FIG. 1(,).

Since the delay time of the full adder circuit in Figure 1 (,) is considered to be almost the same for the sum output 80 and the carry output C0, the following
The delay time in the carry output partial circuit shown in FIG. 3(b) will be described, and the reason why the above-mentioned method is high-speed will be explained.

If three input signals A, B, and C are input at the same time, before the A and B signals generate the X and is input.

Simultaneously with the input of these B and C signals, the two input terminals Tl and I
The terminal capacitances C1 and C2 at 2 are charged or discharged.

Therefore, the X and X signals generated later than the B and CM signals are the first
Input terminal I3 in figure (b). The delay time after arriving at I4 is determined by the capacitance C of the output terminal through two parallel-connected transistors M9 and Mll or 1, MIO, and M12.
It is only the time to charge or discharge 3.

In MOS transistor circuits, in the above case, only one stage of transistors is used.

Since the capacitor is charged or discharged, the delay time is considered to be approximately the same as the delay time of the inverter.

Therefore, from the input of the X and X signals to the output of 00, there is a delay time equivalent to two stages of inverters.

On the other hand, the delay time required to generate the X and X signals from the A and B signals is the sum of the delay time of one stage of exclusive NOR and one stage of inverter.

Since the delay time of the exclusive NOR used in Figure 1(a) is considered to be approximately the time of two inverter stages, the first
The delay time of the entire full adder circuit shown in the figure (,) is approximately equivalent to five stages of inverters.

Therefore, the delay time of the conventional example shown in FIG.
It can be seen that the speed has been increased compared to the previous one.

As described above, although the conventional circuit shown in FIG. 1(, ) is capable of increasing the operating speed, it also has several drawbacks.

First of all, since the full adder circuit shown in FIG. 1(a) uses a transfer gate, it has the drawback of increasing power consumption, although it is an 0M05 circuit.

That is, the transistors Ml, M in FIG. 1(a)
2. M5. Even if M6 is in the on state, the inverter Nl,
The input signal level of N2 is a level lower than the power supply voltage by the threshold voltage of the MOS transistor.

For this reason, a large steady current flows through the inverters Nl and N2 from the power source to the ground point.

As described above, the fact that a large steady current flows even in the 0M08 circuit may pose a problem when large-scale integration is performed.

Second, to compensate for the above-mentioned drawbacks of transfer gates, it is common to use n-MOS transfer gates and p-MOS transfer gates.
There is a method using a transmission gate in which MOS transfer gates are connected in parallel, as shown in Figure 1(a).
It is also used in part of the circuit.

In this case, the problem of the threshold voltage of the MoS transistor as described above does not occur.

However, in this method, since there are two paths for transmitting the same signal, even if a transistor in one of the paths is faulty, the failure cannot be detected in an initial test.

Therefore, if a failure occurs due to aging, problems may arise in the reliability of the integrated circuit.

Thirdly, when a transfer gate is used, it is necessary to draw out the wiring from the diffusion layer region which becomes the source or drain region.

Therefore, the area of these diffusion layer regions increases,
Due to the increased junction capacitance, the speed may not be much faster than logic gates with vertically stacked transistors.

[Purpose of the invention]

The present invention has been made in consideration of the above points.

The present invention provides regular full adder circuits and half adder circuits that are high speed, have low power consumption, are highly reliable for long-term use, and can be constructed from a plurality of identical cells.

[Summary of the invention]

The present invention makes it possible to construct high-speed, low power consumption full adder circuits and half adder circuits by using a plurality of identical cells of complete CuO2 type and a plurality of inverters.

According to the present invention, an arithmetic unit such as an ALU or a multiplier that uses both a full adder circuit and a half adder circuit can be configured with only one type of cell and an inverter.

It is possible to significantly reduce design man-hours and layout man-hours.6 [Embodiments of the Invention] The present invention will be described below according to embodiments. Figure 2(a)
is the first embodiment of the present invention.

Figure 2 (,) shows the configuration of the full adder circuit.

A, B, and C are the three inputs, So is the sum output, and C0 is the carry output.

Also, X and X are the exclusive OR and exclusive NOR of A and H, respectively.6 As can be seen from the circuit diagram in Figure 2(a), the full adder circuit of the present invention consists of four identical cells. It has a regular circuit configuration.

The four cells generate X, X, and C0°So, respectively.

A common signal input method is adopted for the four cells of the circuit of FIG. 2(a) of the present invention.

In order to clarify this, a basic cell in which the input signal is generalized is extracted and shown in FIG. 2(b).

This basic cell has four inputs P, P, R, and S, and implements the logic function P-R+P-3.

In this basic cell, if we set P=A, R=B, and S=B, we can obtain the exclusive OR X of A and B, and p=A,
By setting R=B and S=B, it becomes possible to obtain the exclusive NOR X of A and B.

Also, if the inputs are set as P=X, R=C, and S=C, the sum output S
0 can be obtained, P=X, R=C.

By setting S=B, a carry output C0 can be obtained.

As described above, in the present invention, by changing the input signal with only one basic cell, it is possible to obtain all the desired outputs necessary for the full adder circuit.

This means that the present invention is very effective not only in general integrated circuits but also in integrated circuits such as gate arrays, the demand of which has been increasing in recent years.

Now, consider the operation of the embodiment shown in FIG. 2(a).

This circuit generates X and X using input signals A and B, and
, by switching between C and C using
By generating 0 and switching between B and C, a carry output C0 is generated.

In this circuit, the delay times of So and C0 are considered to be the same, so only the delay time of C0 will be considered below, and the details of the 00 generation partial circuit are shown in FIG.

Now, assuming that three input signals A, B, and C arrive at the same time, the X and X signals are the same as the input signals A, B, and X.

It is output after passing through one stage of the X generation subcircuit.

Therefore, the states of the input signals B and C of the 00 generation partial circuit have already been determined before the X and X signals are output.

In this case, if the B and C signals are input to the gate of the transistor farthest from the output terminal of the C0 generation cell, the terminal capacitances C4 to C7 will be charged or discharged before the X and X signals are input. . Therefore, the delay time from the input to the output of the X and X signals is only one stage of inverter.

Further, the delay time from the input of the A and B signals to the output of X and X is equivalent to approximately three stages of inverters.

From the above, the entire adder circuit of the present invention has a delay time approximately equivalent to four stages of inverters, and can operate faster than the conventional example shown in FIG. 1(a).

Moreover, the full adder circuit shown in FIG. 2(a) is a complete CMOS
Unlike the conventional example shown in Figure 1(a), this type has the advantage that power consumption is extremely low because the level of the output terminal is always at the power supply potential or ground potential and no through current flows. .

Since there is only one path for transmitting the same signal, it is possible to easily detect failure points during initial testing, making it possible to realize highly reliable integrated circuits.

FIG. 4 shows a second embodiment of the invention.

In this embodiment, the X generation partial circuit in the full adder circuit of FIG. 2(a) is replaced with an inverter N8. In this case, although the operating speed of the entire full adder circuit is delayed by one inverter stage, it has the advantage that the number of elements can be reduced by six.

FIG. 5 shows a third embodiment of the invention.

This embodiment shows a half-adder circuit, and as can be seen from the circuit diagram in FIG. It is the same as that used in circuits.

=A, R=B, S=B, and P=1. P=B.

By setting R=A and S=1, the sum output and carry output necessary for the half adder circuit are obtained.

As described above, the present invention has the advantage that a full adder circuit and a half adder circuit can be realized using exactly the same basic circuit cell.

FIG. 6 shows a fourth embodiment of the present invention.

This example shows a partial product addition circuit of parallel multipliers,
Here, for the sake of explanation, a 3×3 multiplier is used.

FAI to FA3 in FIG. 6 indicate the full adder circuits in FIG. 2(,), and HAI to HA3 indicate the half adder circuits in FIG. 5.

However, for ease of viewing, the internal parts of the full adder circuit and half adder circuit are shown conceptually.

FAI~FA3. Rectangle 01-G inside HAI-HA3
18 represents the basic cell of FIG.

W1 to W6 in FIG. 6 are HAI, respectively.

FAI, HA2. HA3. FA2. It is the sum output of FA3, and W7 to W12 are each HAI.

FAI, HA2. HA3. FA2. This is the carry output of FA3.

Also, W2. W3. W7 to Wll are HA2. It also serves as an input signal for HA3 and FAI to FA3.

Other input signals to HAI-HA3 and FAI-FA3 are provided by partial product generation circuits not shown in FIG.

Since the partial product generating circuit is an AND circuit, it can be easily realized using the basic cell shown in FIG.

From the above, it can be seen that when constructing a parallel multiplier using the present invention, it is sufficient to regularly arrange only the same basic cells and inverters.

Therefore, it is possible to significantly reduce design man-hours and layout man-hours.

Further, since the parallel multiplier has a large number of elements, it has a large effect of reducing power consumption, which is one of the features of the present invention.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize full adder circuits and half adder circuits that are faster and consume less power than conventional examples.

Moreover, according to the present invention, a full adder circuit and a half adder circuit can be realized using a plurality of the same basic cells.

This means that it is possible to regularly realize arbitrary arithmetic circuits consisting of full-adder circuits and half-adder circuits as basic elements, which will greatly reduce the design and layout man-hours in the future of highly integrated high-speed digital arithmetic integrated circuits. It has the great effect of reducing

The present invention also has the advantage of providing a means for easily realizing high-speed multipliers, ALUs, etc., if necessary, using a CMOS gate array.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional example taken up for detailed explanation of the present invention, FIG. 2(a) is a circuit diagram of a first embodiment,
FIG. 2(b) is a basic cell circuit diagram that is a component of the first embodiment, FIG. 3 is a partial circuit diagram of the first embodiment, and FIG. 4 is a circuit diagram of the second embodiment. FIG. 5 is a circuit diagram of the third embodiment, and FIG. 6 is a circuit block diagram of the fourth embodiment. Ml, M2. MS, MS, M9. MLO, M29~M4
4. M49~MS 2. MS 1-MS 8...NM
O5) - transistor, M3. M4. M7. M.S. Ml 1. Ml 2. Ml 3-M28. M45~M4
8゜M53~M60...PMOS transistor, N1
~NIO...Inverter, C1-C7...Capacity, H
AI~HA3...half adder circuit, FAI~FA3...
Full adder circuit, Gl to G18...basic circuit cell, vco
... Dentomi 1 figure (good) Kuzu Z figure body) Tomi 2 figure (b) Tomi 3 concave ■4 figure 5 figure

Claims (1)

[Claims] It has one and four input terminals, and when the first and fourth input terminals are both low level or the second and third input terminals are both low level, the output terminal becomes high level. , 1st
, the third input terminals are both high level, or the second,
When both of the fourth input terminals are at a high level, the output terminal becomes a low level, and when inputs other than the above, the output terminal becomes a high impedance. A logic circuit characterized by realizing the following. 2. In the logic circuit according to claim 1, the logic gate includes two pairs of first and second transistors connected in series between the first power supply voltage terminal and the output terminal. and the first set of transistors are 1 and 2, respectively;
The second set of transistors is 3 and 4, respectively, and two third transistors are connected in series between the second power supply voltage terminal and the output terminal.
There are two pairs of fourth transistors, the third pair of transistors are 5 and 6, respectively, the fourth pair of transistors are 7 and 8, respectively, and the first signal is applied to the control terminals of transistors 1 and 6. , a second signal is applied to the control terminals of transistors 3 and 8, a third signal is applied to the control terminals of transistors 2 and 7, and an inverted signal of the third signal is applied to the control terminals of transistors 4 and 5. A logic circuit characterized by using a logic gate that adds a fourth signal. 3. In the logic circuit according to claim 2, 4.
Consisting of two logic gates and three inverters, the first
input the input signal to the input terminal of the first inverter, the first input terminal of the first logic gate, and the second input terminal of the second logic gate, and input the second input signal to the input terminal of the second inverter. The input terminal and the third input terminal of the first logic gate and the third input terminal of the second logic gate are inputted, and the third input signal is inputted to the input terminal of the third inverter and the third input terminal of the third logic gate. inputting the output signal of the first inverter to the second input terminal of the first logic gate and the first input terminal of the second logic gate;
The output signal of the inverter is input to the fourth logic gate of the first logic gate.
and the fourth input terminal of the second logic gate, and the output signal of the third inverter is input to the fourth input terminal of the second logic gate, and the output signal of the third inverter is input to the fourth input terminal of the second logic gate. 4 input terminal and the third input terminal of the fourth logic gate, and the output signal of the first logic gate is input to the first input terminal of the third logic gate and the third input terminal of the fourth logic gate. inputting the output signal of the second logic gate to the second input terminal of the third logic gate and the second input terminal of the fourth logic gate; A sum output is obtained from the output terminal of the third logic gate, and the fourth
A logic circuit comprising a full adder circuit that obtains a carry output from an output terminal of a logic gate. 4. In the logic circuit according to claim 2, 2.
Consisting of two logic gates and two inverters, the first
An input signal is input to the input terminal of the first inverter and the first input terminal of the first logic gate, and a second input signal is input to the input terminal of the second inverter and the third input terminal of the first logic gate. The output signal of the first inverter is inputted to the second input terminal of the first logic gate and the second input terminal of the second logic gate, and the output signal of the first inverter is inputted to the second input terminal of the first logic gate. inputting an output signal to a fourth input terminal of the first logic gate and a third input terminal of the second logic gate;
A first power supply voltage is input to the first and fourth input terminals of the second logic gate, a sum output is obtained from the output terminal of the first logic gate, and a sum output is obtained from the output terminal of the second logic gate. A logic circuit comprising a half-adder circuit that obtains a carry output.