JPS6111052B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protective relay device that protects a multi-terminal power transmission system having three or more terminals including a cable system by introducing a zero-sequence voltage into a current comparison type ratio differential relay element.

2. Description of the Related Art Conventionally, there has been an indicator line relay device as one of protective relay devices for protecting a multi-terminal power transmission system, and an example thereof will be explained with reference to FIGS. 1 and 2. FIG. 1 is a diagram showing a protective relay device that protects a four-terminal power transmission system, in which terminal currents i _2A to i _2D are taken from each terminal A to D through a main current transformer 1 and insulated. The current is introduced through a current transformer 2 and an indicator line 3 into a ratio differential relay device 4 installed on the A terminal side, for example.
This ratio differential relay device 4 determines internal and external faults, and in the case of an internal fault, transmits a trip signal to each terminal through a display line (not shown) different from the display line 3. I also try to trip the disconnector.

Next, FIG. 2 is a diagram specifically showing the configuration of a ratio differential relay device. Each terminal current i _2A to i _2D is determined by the display line 3, the matching circuit 5, which adjusts the impedance of the impedance to the same value, and the isolation current transformer 6,...
After extracting the current as i _2A ′ ~ i _2D ′ through ...,
These are added to the vector sum circuit 7 to create a vector sum, and the vector sum current I _d is added to the full wave rectifier circuit 8.
The electric quantity |I _d | is obtained by full-wave rectification.
Let this electric quantity |I _d | be the operating quantity. Further, the currents i _2A ′ to i _2D ′ are passed through a half-wave rectifier circuit 9 that rectifies a positive half-wave and a half-wave rectifier circuit 1 that rectifies a negative half-wave.
0 respectively to obtain the electrical quantities i _2A ′ ⁺ ~i _2D ′ ⁺ and i _2A ′ ⁻ ~i _2D ′ ⁻ , and add these to the adder circuits 11 and 11, respectively, to obtain the electrical quantities K・Σ _i ⁺ and K・Σ _i ⁻ is obtained (K is a constant). This amount of electricity is defined as the amount of suppression.

The operation amount and suppression amount obtained in this way are compared with the DC bias amount K ₀ and then added to the level detection circuits 12, 12, respectively, and the operation formula {|I
_d |−K·Σ _i −K ₀ >0} is obtained. Here, K
Σ _i collectively refers to K·Σ _i ⁺ and K·Σ _i ⁻ . Then,
If the operating conditions of the above equations continue for more than the time t determined by the subsequent time measurement circuits 13, 13, the time measurement circuits 13, 13 output a signal, and the subsequent time delay circuits 14, 14 output a signal continuously. After that, these two output signals are added to the AND circuit 15, and the circuit 15 sends out a trip signal.

FIG. 3 is a ratio characteristic diagram showing the above operating principle. Therefore, in the ratio characteristics shown in Figure 3,
If an external failure occurs at point _F2 in FIG. 1, all of the currents i _2A to i _2C flowing into the protection zone flow out from the D terminal. Therefore, i _2A + i _2B + i _2C = −i _2
D , and the vector sum current I _d of each terminal current is I
_d =i _2A ′+i _2B ′+i _2C ′+i _2D ′=0, and therefore the amount of operation |I _d | becomes zero. On the other hand, as for the amount of suppression, as shown in Fig. 4, the amount of electricity KΣ is proportional to the amount of electricity that is the sum of the positive wave or negative wave of the current flowing into the protection zone and the current flowing out of the protection zone.
It is the sum of _i and the DC bias amount K ₀ , which ensures correct or incorrect operation.

On the other hand, if an internal failure occurs at point F1 in Figure ₁ , the current flowing into the protected area is i _2A ~ i _2C and the current flowing outside the protected area is i _2D , then i _2A +
i _2B +i _2C > -i _2D , and the vector sum current I _d of each terminal current is I _d = i _2A ′ as shown in FIG.
+i _2B ′+i _2C ′+i _2D ′>0, and the amount of operation |I _d
| becomes |I _d |>0. In addition, the amount of suppression is the amount of electricity KΣ _i , which is proportional to the amount of electricity obtained by adding the positive wave or negative wave of the inflow current and outflow current, separately, and the amount of DC bias K ₀ , |I _d ｜
If the condition -KΣ _i -K ₀ >0 continues for more than t time determined by the time measurement circuit 13, the ratio differential relay device 4 operates and determines that there is an internal failure.

However, when the protection system shown in FIG. 1 is composed of cables, the ground capacitance is large compared to the overhead system, and the internal charging current I _cio flows out in the event of an external failure. Although not shown in Figure 1, the magnitude of I _cio is 3 of the effective ground current I _R in a high resistance grounding system.
There are many strains that more than double.

Therefore, as shown in the vector diagram of Figure 6,
F The vector sum current I _d of each terminal current at the time of an external fault of a _two- point ground fault is I _d = i _2A ′ + i _2B ′ + i _2C ′ + i _2D ′
=-I _cio (I _cio ': I _cio is the amount of electricity passed through the display line 3 and matching circuit 5), and the operating amount is |I _d |=|
I _cio ′| In addition, the amount of suppression is the current flowing into the protection zone and the current flowing out outside the protection zone (i _2D ′
DC bias amount K ₀ is added to the amount of electricity K・Σ _i , which is proportional to the amount of electricity obtained by adding the positive wave or negative wave of +I _cio ′) to each separately.
is added. At this time, |I _d |−K・Σ _i
If the condition -K ₀ >0 continues for more than time t determined by the time measuring circuit 13 shown in FIG. 2, a malfunction will occur. In order to eliminate the influence of this charging current I _cio , the following two methods are conventionally used. That is, how to compensate for internal charging current. This is a method of calculating the logical product of the vector sum current I _d , the output of the phase comparison element of the zero-sequence voltage V ₀ , and the output of the ratio differential relay device 4.

First, the method will be described. FIG. 7 is a diagram showing a device configuration when the charging current I _cio is compensated by the same method, and FIG. 8 is a vector diagram thereof. The system-side internal charging current −I _cio at the time of an external failure is 90° behind the zero-sequence voltage V ₀ , and −
Since I _cio ' has a delayed phase with respect to -I _cio by α (α: indicates the transmission delay angle due to the display line), if this zero-phase voltage V ₀ is applied to the phase shift circuit 17 via the transformer 16, Obtain V ₀ 〓α which lags by α with respect to V ₀ , and obtain the electrical quantity I _{C COMP} which leads by 90° with respect to this electrical quantity. If this is added to the vector sum circuit 7 along with the terminal currents i _2A ′ to i _2D ′, the internal charging current can be canceled and its influence can be eliminated.

Next, we will discuss the method. FIG. 9 shows the device configuration when a phase comparison element is provided, and the 10th
The figure is a diagram showing the phase characteristics of the phase comparison element.
Now, the vector sum current I _d of each terminal current and the quantity of electricity V ₀ 〓α obtained from the zero-phase voltage V ₀ via the transformer 16 and the phase shift circuit 17 enter the buffer circuit 18 and convert it into a square wave. After that, these square waves are input into the AND circuit 19, and if the overlap time of the square waves is greater than or equal to the time t determined by the subsequent time measuring circuit 20, a signal is output from the time measuring circuit 20 and this is the time delay. The circuit 21 provides continuous output. This causes the phase comparison element to output a signal.
Here, t'=(180°-θ)×1 cycle time/36
When it is set to 0°, as shown in FIG. 10, a characteristic is obtained that operates when the electrical quantity of I _d is within the slope with respect to the zero-phase voltage V ₀ 〓α.

Therefore, the internal charging current during external fault −I _cio ′
(The amount of electricity that lags −I _cio by α via the display line)
is outside the operating range as shown in FIG. 10. Therefore, by configuring as shown in FIG. 9, unnecessary operations due to internal charging current can be prevented.

However, in both of the above two methods, the zero-sequence voltage
V ₀ must be introduced into the relay device. However, multi-terminal power transmission systems often operate with one or several terminals at rest. On the other hand, as shown in FIG. 11, in the case where the zero-sequence voltage is obtained from the busbar instrument transformer 23, the A terminal, which introduces the zero-sequence voltage into the ratio differential relay device 24, is at the rest end. If the disconnector 25A is opened, the zero-sequence voltage cannot be introduced, so malfunctions due to the charging current cannot be avoided.

The present invention has been made in view of the above circumstances, and its purpose is to reduce the amount of zero-sequence voltage transferred from each terminal even when a multi-terminal system is operated with several terminals at rest. The present invention provides a protective relay device that automatically selects a zero-sequence voltage to be used and introduces it into the relay device, thereby avoiding malfunctions caused by internal current.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 12 shows the overall configuration of a multi-terminal display line relay device, FIG. 13 is a specific configuration diagram of the ratio differential relay device shown in FIG. 12, especially in the case of compensating for internal charging current, and FIG. 14 12 is a specific configuration diagram of the ratio differential relay device shown in FIG. 12, especially when a phase comparison element is used. In addition, in FIGS. 12 to 14, conventional devices (for example, FIG. 1, FIG. 2, . . .
etc.) are designated by the same reference numerals, and the description of some of them will be omitted here.

First, the configuration for obtaining the amount of electricity for compensating the internal charging current will be described. In FIGS. 12 and 13, after the zero-phase voltages V _0A to V _0C of each A to C terminal are taken out via the isolation transformer 26, the display line 27
This is a configuration in which the zero-sequence voltages V _0A to V _0C are supplied to the ratio differential relay device 24 using
Matching circuit 2 for adjusting the impedance of 7, ...... and this display line 27, ...... to the same value
8,... Voltage V via isolation transformer 29,......
Take out as _0A ′ to V _0C ′. In this case, assuming that the relay device installation terminal is the A terminal, V _0B ′ and V _0C ′ are the amounts of transferred electricity. The voltages V _0A ′ to V _0C ′ taken out by the isolation transformers 29, . The use condition S of the A terminal ("1" when the breaker or disconnector 25 is in a closed state, and "0" when it is in an open state) is applied to the other input part of the AND circuit 31A. Moreover, the other input part of the AND circuit 31B has A
A condition obtained by inverting the terminal use condition S by a negative circuit 32 is added. Similarly, the negation condition of the A terminal usage condition S and the condition _B ' obtained by passing the output of the AND circuit 31B through the time delay circuit 33B and the negation circuit 34 are added to the other input portion of the AND circuit 31C.
V _0A ′ to V _0C ′ are gate circuits 35A to 35, which will be described later.
After being synthesized by the synthesis circuit 36 via C, this synthesized signal is input to the phase shift circuit 17 and adjusted so that it has a leading phase of 90 degrees with respect to V _0A ′ to V _0C ′, and the internal charging current compensation I _{C COMP} is being taken out. Note that the gate circuits 35A to 35C are time delay circuits 33A to 35C.
It is controlled by signals V _A ' to V _C ' output from 33C.

Next, the configuration of FIG. 14 using phase comparison elements is almost the same as that of FIG. 13, but the difference in configuration is that the square wave output signals V _A to _V Each signal passes through an OR circuit 37, and the output signal of this circuit 37 and the vector sum current _Id are compared in phase. The signal obtained as a result of this comparison is used as the zero-sequence voltage quantity.

Next, the operation of the device configured as above will be explained. Note that the configurations shown in FIGS. 13 and 14 are examples assuming that the order of use of zero-sequence voltages is V _0A to V _0C , and the response of the zero-sequence voltage selection circuit in FIGS. 13 and 14 is is shown in FIG.

(1) Regarding obtaining the amount of electricity to compensate for the internal charging current. When the terminals other than the A terminal are at rest, that is, the A terminal use condition S is "1", and therefore the AND circuits 31B and 31C are locked by the negative condition of the A terminal use condition S. Therefore, as shown in FIG. 15A, the AND circuit 31
Only the output signal V _A of A is a square wave signal, and this signal V _A is converted into a continuous "1" signal by the time delay circuit 33A, and the output of V _A ' (V _B ', V _C ' are "0"). As a result, only the gate circuit 35A becomes open, and V _0A ' is the internal charging current compensation I _{C COMP}
used for purposes.

Next, a case where the A terminal becomes the rest end will be explained. In other words, the A terminal usage condition S is “0”
Therefore, the AND circuit 31A is locked,
The signals of V _A and V _A ' become "0". Therefore, the gate circuit 35A is also in a locked state. At this time,
Since there is a zero-phase voltage V _0B from the B terminal, the output signal V _B of the AND circuit 31B becomes a square wave signal as shown in FIG. 15B. Therefore, the AND circuit 31C transfers the signal V _B to the time delay circuit 33B.
It is locked by the signal V _B ' which is converted into a continuous "1" signal. Therefore, V _B ' is "1" and V _C ' is "0".
Therefore, only the gate circuit 35B is opened and V _0B ' is used for internal charging current compensation I _{C COMP} .

Next, a case where terminals A and B become idle ends, that is, a case where two terminals of terminals C and D shown in FIG. 12 are operated will be described. In this case, since the zero-phase voltages V _0A and V _0B from the A and B terminals do not exist, the condition S is "0" and the AND circuit 31A,
The output signals V _A and V _B of 31B become "0". Therefore, AND circuits 31A, 31B and gate circuits 35A, 35B are all in a locked state.

On the other hand, since there is a zero-phase voltage V _0C ' from the C terminal, the output signal V _C of the AND circuit 31C becomes a square wave signal as shown in FIG. 15C. and,
The signal V _C is converted into a continuous "1" signal by the time delay circuit 33C, and the gate circuit 35 is output by the output of V _C '.
Only C becomes open, and the zero-phase voltage V _0C ' is used for internal charging current compensation I _{C COMP} .

In principle, this relay device using current differential cannot be applied in cases where A, B, and C terminals are idle terminals and only one terminal is operated, so in a multi-terminal (n) system, (n-1) One terminal is selected from the zero-sequence voltages of the terminals. That is,
Of the zero-sequence voltages at the (n-1) terminals, the voltage at the (n-2) terminals is transferred to the terminals where the differential relay device is installed. Here, if (1 cycle + margin) is used as the delay time of the time delay circuits 33A to 33C, the square wave signals of V _A to V _C are converted to continuous "1" signals, as shown in FIG. _A ′ to V _C ′. Therefore, even in the case where there is a rest end, the influence of the internal charging current can be easily eliminated.

(2) Next, the case of obtaining the amount of electricity used in the phase comparison element will be described with reference to FIG. When a terminal other than the A terminal is at rest, only the output voltage V _A of the AND circuit 31 _A is at the first terminal, as shown in FIG. 15A.
The signal is introduced into an OR circuit 37 shown in FIG. 4 and used as a phase comparison signal.

Next, the case where the A terminal becomes the rest end will be described. As shown in FIG. 15B, only the output voltage V _B of the AND circuit 31 _B is introduced into the OR circuit 37 and used as a phase comparison signal by the inverted signal of the A terminal usage condition. In this case, since the A terminal usage condition S=0, the AND circuit _31A is locked and V _A =0, and since _B '=0, the AND circuit 31c is locked and V _C =0.
It becomes 0.

Next, a case where the A and B terminals are at rest ends will be described. In this case, as shown in FIG. 15C, due to ="1" and _B '="1", the output voltage V _C is output from the AND circuit 31c and introduced into the OR circuit 37 as a phase comparison signal. used. From the above points, even if there is a rest end, the influence of the internal charging current can be easily eliminated by the phase comparison element.

Therefore, in this device, the zero-sequence voltages to be used can be automatically selected in an orderly manner and introduced into the phase comparator circuit and the internal charging current compensation circuit.

In the above embodiment, a four-terminal system was described, but in principle it is also applicable to a multi-terminal system of three or more terminals. FIG. 16 shows an example in which the system is applied to a multi-terminal (n) system, and two electrical quantities are obtained, one for phase comparison and one for internal charging current compensation. The outline of the configuration can be easily understood from the combination of FIGS. 13 and 14, and therefore, in FIG. 16, the same parts as in FIGS.

Furthermore, although the above embodiments have been described with reference to the display line relay device, the present invention can also be applied to, for example, FM carrier and PCM carrier relay devices, which are one type of pilot relay device. First, in the case of the FM carrier relay device, as shown in Fig. 17a, the input electrical quantity is converted into a frequency (microwave) corresponding to the electrical quantity by the frequency converter 38 and transmitted, and this is received. The device 39 on the side may convert it into an amount of electricity corresponding to the frequency.

In addition, in the case of the PCM carrier relay device, as shown in FIG. 17b, the input electrical quantity is converted into a pulse code corresponding to the electrical quantity by the code conversion device 41, transmitted by microwave, and received. The pulse code is converted into an electrical quantity corresponding to the pulse code by a device 42 on the side.

Furthermore, in the above embodiment, the analog quantity of zero-sequence electricity was transmitted using the display line as a transmission means, but for example, as shown in Fig. 18, the zero-sequence electricity quantity was transmitted at each terminal as shown in Fig. 19. Alternatively, the signal may be converted into a digital quantity (rectangular wave) and transmitted. In this case, the transmission means include microwave,
Power line carrier waves can be used. Therefore, 43 shown in FIG. 18 is a device that converts a rectangular signal into a microwave or power line carrier wave, and 44 is a device that converts a microwave or power line board transmission wave into a rectangular signal.

As detailed above, according to the present invention, even if there is an idle end in a multi-terminal system, the necessary zero-sequence voltage is automatically selected from the zero-sequence voltages of each terminal and introduced into the relay device. This makes it possible to eliminate the influence of malfunctions caused by internal charging current.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an indicator line relay device as an example of a conventional protective relay device, Fig. 2 is an internal block diagram of the ratio differential relay device shown in Fig. 1, and Fig. 3 is a diagram similar to that shown in Fig. 1. 4 is a characteristic diagram explaining the amount of suppression, FIGS. 5 and 6 are characteristic diagrams of the amount of operation and suppression in internal and external failures, and FIG. The figure is a block diagram of a conventional device when compensating the internal charging current, FIG. 8 is a vector diagram of FIG. 7, FIG. 9 is a block diagram of a conventional device when a phase comparison element is provided, and FIG. Fig. 11 is a configuration diagram illustrating the conventional example, and Fig. 12 is a phase characteristic diagram.
13 is a block diagram illustrating an embodiment of the protective relay device according to the present invention, FIG. 13 is a specific block diagram of the ratio differential relay device shown in FIG. 14 is a specific configuration diagram of the ratio differential relay device shown in FIG. 12 when a phase comparison element is used, and FIGS. 15 a to 15 c are waveforms illustrating the operation of the device shown in FIGS. 12 to 14. 16 to 19 are configuration diagrams and characteristic diagrams illustrating other embodiments of the device of the present invention. 1...Main current transformer, 2...Isolated current transformer, 3...Display line, 4...Ratio differential relay device, 5...Matching circuit, 7...Vector sum circuit, 8...Full wave Rectifier circuit, 9... Positive wave half-wave rectifier circuit, 10... Negative wave half-wave rectifier circuit, 11... Addition circuit, 13... Time measurement circuit, 14... Time delay circuit, 15...... AND circuit, 17... Phase shift circuit, 24... Ratio differential relay device (with internal charging current countermeasure), 25... Line breaker or disconnector, 27... Display line, 28... Matching circuit, 29... Isolation transformer, 31 _A , 31 _B ...AND circuit, 32...NOT circuit, 33 _A , 33 _B ...Time delay circuit, 34...NOT circuit, 35 _A , 35 _B ...
...Gate circuit, 36...Synthesis circuit, 37...OR circuit.

Claims (1)

[Scope of Claims] 1. In a protective relay device for a power transmission system that operates with one or more terminals in an n-terminal (n≧3) power transmission system as a rest end, The amount of electricity obtained by scalar combining the terminal currents of each terminal is the amount of electricity, and the amount of electricity obtained by scalar composition of the terminal currents of each terminal is the amount of suppression. a differential relay element; a zero-sequence voltage acquisition means that is provided with a transformer at a plurality of terminals and takes out the zero-sequence voltage of each terminal; A plurality of logical judgment circuits into which the zero-sequence voltage of each terminal extracted by the voltage acquisition means is input, and a wire breaker or disconnector (hereinafter referred to as a wire breaker, etc.) are connected to the other input terminals of these logic judgment circuits. It has a negation circuit which inputs a usage condition signal (designated as . A selection signal is output from the logic judgment circuit corresponding to the terminal that has been selected, and when the terminal becomes a rest end and a circuit breaker or the like is open, the negation circuit is used to select a signal from the other logic judgment circuit in a predetermined order. a selection signal output means for outputting a selection signal according to the selection signal; and a selection signal output means provided individually corresponding to the plurality of terminals and outputting a zero-sequence voltage of a terminal selected based on the selection signal output from the selection signal output means. and a phase shift circuit that adjusts the phase of the zero-phase voltage output from the gate circuit and outputs the phase-shifted zero-phase voltage, and outputs the phase-shifted zero-phase voltage as an internal charging current compensation signal. 1. A protective relay device comprising: selecting means, wherein the internal charging current compensation signal is applied to the operation amount in the ratio differential relay element to compensate for the system internal charging current. 2. In a protective relay device for a power transmission system that operates with one or more terminals in an n-terminal (n≧3) power transmission system as a rest terminal, the amount of electricity obtained by vector-synthesizing the terminal currents of each of the terminals is used as the operating amount. and the amount of electricity obtained by scalar combining the terminal currents of each terminal as the amount of suppression, and a first condition signal for outputting a trip signal when the difference between these operating amounts and the amount of suppression exceeds a predetermined value. a ratio differential relay element that outputs a zero-sequence voltage; a plurality of logic judgment circuits into which the zero-sequence voltage of each terminal extracted by the zero-sequence voltage acquisition means is input, and a use condition signal such as a circuit breaker is preliminarily provided to the other input terminal of these logic judgment circuits. The logic judgment circuit has a negative circuit that inputs the logic judgment circuits other than the logic judgment circuit corresponding to the predetermined terminal so as to lock each other, and normally the logic judgment circuit corresponds to the predetermined terminal. Outputs the output as a phase comparison signal, and this terminal becomes the rest end,
a phase comparison signal output means for outputting the output of the other logical judgment circuit according to a predetermined order as a phase comparison signal by using the negation circuit when a circuit breaker or the like is open; and this phase comparison signal output means a phase comparison element that outputs a second condition signal for outputting a trip signal when the zero-sequence voltage of the terminal corresponding to the phase comparison signal outputted by the operation amount and the phase of the operation amount are in a predetermined phase; A protective relay device comprising: outputting the trip signal on the condition that the condition signal is output from both the phase comparison element and the ratio differential relay element.