JPS61109341A - Timing extraction circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of jitter in a timing signal by providing a gate circuit to a circuit receiving a PCM signal to extract a timing component so as to prevent phase shift in a pulse signal transmitted to a resonance circuit. CONSTITUTION:Threshold voltages +Vth, 0 and -Vth are fed respectively to comparator circuits 10-12 of a timing extraction circuit, they are compared respectively with an AMI signal of a PCM signal and output signals a-c at the leading of the output pulse are fed to a detection circuit 2. The circuit 2 detects the front edge and trailing edge of the signals a-c to output a prede termined pulse, which is fed to a gate circuit 3. The circuit 3 selects the pulse corresponding to the signals a-c and gives the result to a timing signal generat ing circuit 4. Then the generation of phase shift to the pulse signal fed to the circuit 4 is prevented so as to prevent jitter in the outputted timing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timing extraction circuit, and more particularly to a timing extraction circuit for receiving an AMI format pulse code modulation (PCM) signal and extracting its timing components.

[Conventional technology]

PCM signal with bipolar code format (hereinafter referred to as AMI
abbreviated as signal) t? Conventionally, a timing extraction circuit that receives a signal and extracts its timing component generates a pulse when the AMI signal voltage reaches positive and negative threshold voltages while the voltage waveform of the AMI signal is rising and falling, respectively. A circuit is used in which a timing signal is obtained by passing a pulse signal through a resonant circuit and extracting a sine wave component.

FIG. 2 is a waveform diagram listing the voltage waveforms of the AMI signals received by the conventional circuit and the circuit of the present invention.

Before being sent to the timing extraction circuit, the AMI signal is equalized for waveform distortion caused by the transmission path, and the AMI signal is
The voltage of the signal changes from zero voltage 0 to every predetermined period T. The value is either positive peak voltage +Vp1 or negative peak voltage -Vp.

FIG. 2 shows a list of changes in the voltage waveform of the ANI signal within the period T. Since it is an AMI signal, transitions from voltage +Vp to voltage +Vp and from voltage -Vp to voltage -Vp do not appear, and all transitions other than these two are listed.

In the conventional timing extraction circuit, as mentioned above, the AMI
During the double voltage upper punch, a pulse is generated when the voltage reaches a predetermined positive threshold of 4Ivi voltage + VthK,
Further, while the voltage is falling, a pulse is generated when the voltage reaches a predetermined negative threshold voltage -vth.

[Problem that the invention seeks to solve]

Therefore, in the conventional timing extraction circuit, when there is a transition from zero voltage to a positive peak voltage +Vp (or a negative peak voltage -Vp) within the period T, the point P is reached.

(or point q+), and from the negative peak voltage -Vp to the positive peak voltage +Vp (or from the positive peak voltage +Vp to the negative peak voltage -Vp)
When transitioning, pulses are generated at the times of points 1 and 2 (or point q2). However, there is a phase difference between points pt and p2 (or points q1 and Q2) equal to the difference between times τ1 and τ2 (τ2 - τI), and this phase difference causes jitter in the timing signal, causing the sign There is a problem that problems such as erroneous identification may occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a timing extraction circuit which solves the above-mentioned problems and prevents the occurrence of jitter in a timing signal by preventing a phase difference from occurring in a pulse signal sent to a resonant circuit as in the conventional case. .

[Means to solve the problem]

The circuit of the present invention is provided with a positive threshold voltage.
- a first voltage comparator circuit provided with a zero threshold voltage, a second voltage comparator circuit provided with a zero threshold voltage, and a third voltage comparator circuit provided with a negative threshold voltage; Comparing means for comparing the level of the value voltage and the voltage of the received AMI signal and generating a first pulse group consisting of pulses indicating the level;
a detection circuit that detects at least one of a front edge and a trailing edge of each pulse of the first pulse group and generates a second pulse group consisting of pulses that rise at the time of detection and have a predetermined width; a gate circuit that selects and sends out a pulse with a predetermined phase from a group of pulses; and a timing signal that extracts a predetermined frequency component included in a signal consisting of the pulses sent out by the gate circuit and sends it out as a timing signal. It is equipped with a generation circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The received AMI signal is sent to comparison circuits 10, 11 and 12. Comparison circuits 10.11 and 12 are both voltage comparison circuits, and a pulse rises when the voltage of the AMI signal is higher than the positive threshold voltage +vth, zero voltage 0, and negative threshold voltage -vth, respectively. Signals a, b and C are generated and sent to the detection circuit 2. The detection circuit 2 detects the front line (rising edge) and trailing edge (rising edge) of each pulse of the signals a, b, and C.
A circuit for detecting the falling edge of each pulse generates a pulse having a rising edge and a predetermined width at the leading edge or trailing edge of each pulse, and sends it to the gate circuit 3. The gate circuit 3 is the detection circuit 2
This is a circuit that selects and passes only those of the same phase from among the pulses sent from the oscilloscope.Pulses are selected as follows. When the trench AMI signal transitions from zero voltage O to positive peak voltage +Vp, select the pulse that rises at the leading edge of the pulse of signal a, that is, the pulse that rises at the time point p1 in FIG. Further, when the AMI signal changes from the negative peak voltage -Vp to zero voltage O, a pulse that rises at the trailing edge of signal C, that is, a pulse that rises at the time point q1 in FIG. 2 is selected. Furthermore, when the AMI signal transitions from a negative peak voltage -Vp to a positive peak voltage +Vp, and from a positive peak voltage +Vp to a negative peak voltage -
When transitioning to Vp, the pulse rises at the front and trailing edges of the signal, respectively, point p in FIG. Select the pulse that rises at the time of .

The pulses selected by the gate circuit 3 in this manner are sent to the timing signal generation circuit 4 as a signal g.

As shown in FIG.
Since th and -vth are set, all pulses of signal g appear in the same phase. Therefore, the timing 16° obtained by passing the signal g through the resonant circuit 4 does not include jitter caused by the phase shift of the pulse of the signal g, as in the conventional case. As the timing signal generating circuit 4, a tank circuit in which a coil and a capacitor are all connected, a phase locked loop (PLL) circuit, or the like is used as in the conventional case.

Figures 3 and 4 respectively show the percentage of detection times in this example.
FIG. 2 is a block diagram showing a configuration example and a time chart showing an operation example regarding the gate circuit 3 and the gate circuit 3. The trailing edge detection circuits 23, 24 and 25 generate pulses with a predetermined width that rise on the trailing edges of signals a, b and C, respectively. Both of them are sent to the gate circuit 3.I edge detection circuit 20 and trailing edge detection circuit 2
The output signal No. 5 passes through the OR gate 31 and is sent to one input terminal of the inhibit gate 38 as a signal d. Therefore, the signal d consists of a pulse that rises at the front edge of the signal a and a pulse that rises at the trailing edge of the signal C.

The output signals of the leading edge detection circuit 21 and the trailing edge detection circuit 24 are sent to the logical sum gate 3 as a signal e through the sum gate 32.
7 is sent to one input end. Therefore, the signal e consists of a pulse that rises at the leading edge of the signal and a pulse that rises at the trailing edge of the signal. Trailing edge detection circuit 23 and leading edge detection circuit 22
The sending signals are sent to timer circuits 35 and 36, respectively. Each of the timer circuits 35 and 36 is a monostable multivibrator and generates a pulse that rises with the received pulse and has a predetermined width. timed circuit
The output signals '35 and 36 are sent to the other input terminal of the inhibit gate 38 and the other input terminal of the AND gate 37 as a signal f via the OR gate 33. Therefore, the signal f consists of a wide pulse that rises at the trailing edge of the signal a, and a wide pulse that rises at the leading edge of the signal C. The width of this pulse is as short as half the period T (T/2), and the time 2×(τ
2-τI) and the pulse width of the signal d (or e), which is longer than the set time.

Therefore, within the period T in which the AMI signal changes from a negative peak to a positive peak, and within the period T in which it changes from a positive peak to a negative peak, in both cases, within the pulse rising time of the signal f. Pulses of the signals d and e appear, the prohibition gate 38 prohibits the pulse transmission of the signal d, and the AND gate 37 causes the pulse transmission of the signal e. Also, in cases other than the above two cases, the pulses of signals d and e do not appear within the pulse rising time of signal f, and the pulses of signals d and e appear within the pulse falling time of signal f, and the inhibit gate 38 d pulse is sent, and the AND gate 37
stops sending pulses of signal e. The output signals of the inhibit gate 38 and the AND gate 37 are sent to the timing signal generating circuit 4 of FIG. 1 as a signal g via the OR gate 34.

As is clear from the above explanation, the signal g consists of a pulse that rises when the voltage of the AMI signal reaches a positive threshold voltage within the period in which it changes from zero to a positive peak, and a pulse that rises when the voltage of the AMI signal reaches zero. The pulse that rises when the negative threshold voltage is reached within the period in which the voltage of the AMI signal changes from the negative peak to the positive peak, and the pulse that rises when the voltage of the AMI signal changes from the negative peak to the positive peak and from the positive peak to the positive peak. This consists of a pulse that rises when a threshold voltage of zero is reached in both periods within the period of the pulse. As mentioned above, all pulse rises of this signal g appear in the same phase, and the time between each pulse rise is an integral multiple of the period T, so that no phase shift occurs as in the conventional case.

〔Effect of the invention〕

As described above, the present invention has the effect of realizing a timing extraction circuit that prevents jitter from occurring in a timing signal by not causing a phase shift in a pulse signal sent to a resonant circuit as in the prior art.

[Brief explanation of drawings]

1 and 3 are block diagrams showing an embodiment of the present invention, FIG. 2 is a waveform diagram listing the waveforms of AMI signals received by the conventional circuit and the circuit of the present invention, and FIG. 4 is a waveform diagram of the present invention. It is a time chart showing the operation in the example. 10-12... Comparison circuit, 2... Detection circuit, 20-22... Leading edge detection circuit, 23-2
5... Trailing edge detection circuit, 3... Gate circuit, 31-34 Old... OR gate, 35, 36...
...Timed circuit, 37..., ...Logic gate, 3
8...Prohibition gate, 4...Timing signal generation circuit.

Claims (1)

[Claims] A first voltage comparison circuit given a positive threshold voltage, a second voltage comparison circuit given a zero threshold voltage, and a third voltage comparison circuit given a negative threshold voltage. a comparison means for generating a first pulse group consisting of pulses indicative of the level by comparing the level of each of the threshold voltages and the voltage of the received AMI signal; a detection circuit that detects at least one of a leading edge and a trailing edge of each pulse and generates a second pulse group consisting of pulses that rise at the time of detection and have a predetermined width; It includes a gate circuit that selects and sends out pulses of a predetermined phase, and a timing signal generation circuit that extracts a predetermined frequency component contained in a signal consisting of the pulses sent out by the gate circuit and sends it out as a timing signal. A timing extraction circuit characterized by: