JPS61107753A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61107753A
JPS61107753A JP59227800A JP22780084A JPS61107753A JP S61107753 A JPS61107753 A JP S61107753A JP 59227800 A JP59227800 A JP 59227800A JP 22780084 A JP22780084 A JP 22780084A JP S61107753 A JPS61107753 A JP S61107753A
Authority
JP
Japan
Prior art keywords
electrode
region
silicon substrate
electrode plate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59227800A
Other languages
Japanese (ja)
Other versions
JPH027182B2 (en
Inventor
Seiichi Miyagawa
宮川 誠一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Rectifier Corp Japan Ltd
Original Assignee
International Rectifier Corp Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp Japan Ltd filed Critical International Rectifier Corp Japan Ltd
Priority to JP59227800A priority Critical patent/JPS61107753A/en
Publication of JPS61107753A publication Critical patent/JPS61107753A/en
Publication of JPH027182B2 publication Critical patent/JPH027182B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
    • H01L23/4924Bases or plates or solder therefor characterised by the materials
    • H01L23/4926Bases or plates or solder therefor characterised by the materials the materials containing semiconductor material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To simplify the constitution of a semiconductor device by using the same silicon substrate as an external leading-out electrode for a device with two different conduction type regions and electrically insulating the substrate by an internal P-N junction. CONSTITUTION:An external leading-out electrode plate 7' consists of an silicon substrate having low resistance, and a P type diffusion region 8 is formed where corresponding to a base region 3. An N<+> diffusion region P is shaped into the P type diffusion region 8. The N<+> diffusion regions 9 are all connected in the electrode plate 7'. A stepped section 10 is formed to one part of the external leading-out electrode plate 7' composed of the silicon substrate, and a lead wire 12, etc. are lead out of an electrode 11 shaped onto the N<+> region 9 in the stepped section 10.

Description

【発明の詳細な説明】 [産業上の利用分!P] この発明は、半導体装置の外部引出し電極、特に半導体
ペレットの一主面側に2つの互いに異なる領域が複数に
島状に分割されて配置されこの共通領域に設けたそれぞ
れの電極金属と電気的接続を図って外部へ引き出す外部
引出し電極の栴造を改良した半導体装置に関する。
[Detailed description of the invention] [Industrial use! P] This invention relates to an external extraction electrode of a semiconductor device, in particular, two mutually different regions are arranged in a plurality of island shapes on one main surface side of a semiconductor pellet, and each electrode metal provided in this common region and an electrical The present invention relates to a semiconductor device with an improved structure of an external lead-out electrode that is connected to the outside.

[従来の技術] 電力用トランジスタ、ダーリントントランジスタ、ゲー
ト・ターン・オフ・サイリスタ(GTO)等大容量の半
導体装置では、一般に半導体ペレットの一主面側に2つ
の互いに異なる領域が島状に分割されて形成され互いに
入り組んだ複雑なパターン形状となり、この領域上の電
極金属も微細かつ複雑な形状となっている。かかる電極
金属にはこれらと゛電気的に接続される外部引出し電極
が設けられるが、前記のように電極金属が微細かつ複雑
な形状をしているために一般に次のような方策がとられ
ている。
[Prior Art] In large-capacity semiconductor devices such as power transistors, Darlington transistors, and gate turn-off thyristors (GTOs), two mutually different regions are generally divided into island shapes on one main surface of a semiconductor pellet. The electrode metal on this region also has a fine and complicated shape. Such electrode metals are provided with external lead-out electrodes that are electrically connected to them, but since the electrode metals have minute and complicated shapes as mentioned above, the following measures are generally taken. .

■ 複数に分割された複雑なパターン形状の電極金属に
直接外部引出し電極を取付ることは困難であるために、
アルミ(Affi)線、金線(AU )を用いてワイヤ
ボンディング法、超音波法、熱圧着法等により各島間を
電気的に接続し、いずれか1つの島から集中的に外部へ
引出すための外部引出し電極を設けている。
■ It is difficult to attach external lead electrodes directly to electrode metal with a complex pattern that is divided into multiple parts.
Electrical connections are made between each island using aluminum (Affi) wires and gold wires (AU) using wire bonding, ultrasonic, thermocompression bonding, etc., and electrical connections are made from any one island to the outside. An external extraction electrode is provided.

■ −導電型領域上の電極金属の島状パターン形状に合
せて金属板を微細加工し、この金属板を介して外部引出
し電極を取付けている。
- A metal plate is microfabricated to match the island pattern of the electrode metal on the conductivity type region, and an external lead electrode is attached via this metal plate.

[発明が解決しようとする問題点] 上記■の場合、分割された島の数が多くなればなるほど
、配線用のワイヤの数が多くなり、信頼性の問題や1つ
の半導体ペレット内に複数の半導体装置を作り込んであ
るものにあっては互いのワイヤ間を電気的に絶縁しなけ
ればならず、一層全体の構成を複雑化、組立作業のW4
雑化等を避けられないという問題点があった。
[Problem to be solved by the invention] In the case of (2) above, the larger the number of divided islands, the larger the number of wiring wires, which may lead to reliability problems and the problem of multiple For products that incorporate semiconductor devices, it is necessary to electrically insulate the wires from each other, which further complicates the overall configuration and increases W4 assembly work.
There was a problem that clutter etc. could not be avoided.

また、上記■の場合まず、金属板の前記パターン形状に
合せた微細加工がきわめて困難であり、さらに組立時に
両パターンの位置合せが難しく、極端な場合には位置ず
れによる短絡事故等も招来するという問題点があった。
In addition, in the case of (■) above, firstly, it is extremely difficult to perform microfabrication to match the pattern shape of the metal plate, and furthermore, it is difficult to align both patterns during assembly, and in extreme cases, short circuit accidents due to misalignment may occur. There was a problem.

この発明は上記のような問題点を解消するためになされ
たもので、半導体ペレットの一生面上の2つの互いに異
なる導電型領域から容易に取り出すごとができる外部引
出し電極構造を有する半導体装置を提供することを目的
とす、るものである。
This invention was made to solve the above-mentioned problems, and provides a semiconductor device having an external extraction electrode structure that can be easily taken out from two regions of different conductivity types on the surface of a semiconductor pellet. The purpose is to do something.

[問題点を解決するための手段] この発明にかかる半導体装置は、半導体ペレットの一生
面側に露出した2つの互いに異なる導電型領域に対して
1枚のシリコン基板から成る外部引出し電極板を設け、
上記半導体ペレットの一生面側に載置したものである。
[Means for Solving the Problems] A semiconductor device according to the present invention provides an external lead electrode plate made of a single silicon substrate for two regions of different conductivity types exposed on the whole surface side of a semiconductor pellet. ,
It is placed on the permanent surface side of the semiconductor pellet.

[作 用] 外部引出し電極板としてのシリコン基板内にP−N接合
を作り込み互いに絶縁しつつ1枚のシリコン基板により
、半導体ペレットの一生面側の互いに異なる領域から電
極を引き出す。
[Function] P-N junctions are formed in a silicon substrate serving as an externally drawn electrode plate, and electrodes are drawn out from different regions on the whole surface side of a semiconductor pellet using a single silicon substrate while insulating each other.

[実施例] 第1図は、本発明に係る半導体装置を概略的に示した断
面図である。
[Example] FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the present invention.

同図において、半導体ペレット(1)には、熱。□、よ
、、7え、ヵ□□5:/9..9 t’Gよ  □;コ
レクタ領域(2)、ベース領域(3)、このベース領域
(3)内に互いに分離された島状のエミッタ領域(4)
が形成されている。
In the figure, the semiconductor pellet (1) is heated. □, yo,, 7e, ka □□5:/9. .. 9 t'G □; Collector region (2), base region (3), island-shaped emitter region (4) separated from each other within this base region (3)
is formed.

こうして半導体ペレット(1)の−主面側にはベース領
域(3)とエミッタ領域(4)とが同一平面上に互いに
入り組んだ形で現われる。この同一平面上のベース領域
(3)およびエミッタ領域上にはそれぞれ金属電極(5
)、(6)が設けられ、また反対主面側のコレクタ領域
上にも金属電極(7)が設けられる。
In this way, a base region (3) and an emitter region (4) appear on the same plane on the -main surface side of the semiconductor pellet (1) in a form that is intertwined with each other. Metal electrodes (5) are formed on the base region (3) and emitter region on the same plane, respectively.
), (6) are provided, and a metal electrode (7) is also provided on the collector region on the opposite main surface side.

上記エミッタ領域(4)の金属電極(6)上に外部引出
し電極板(7′)が設けられるがこの外部引出し電極板
(7′)の素材はシリコン基板から成り、ベース領域(
3)およびエミッタ領域(4)の金属電極(5)、(6
)のパターン形状に合せた形状に形成される。
An external extraction electrode plate (7') is provided on the metal electrode (6) of the emitter area (4), and the material of this external extraction electrode plate (7') is a silicon substrate, and the base area (
3) and metal electrodes (5), (6) of the emitter region (4).
) is formed in a shape that matches the pattern shape.

すなわら、外部引出し電極板(7)は、低抵抗のシリコ
ン基板から成り、例えば比抵抗3〜15/1000Ω・
Cl1l厚さ300μmのN型シリコン基板を用い、通
常のフォト・リソ技術、選択拡散Fh等によりベース領
域(3)に対応する位置にP型拡散領域(8)を形成し
、次いで、このP型拡散領域(8)内にN十拡散領域(
9)を作り込む。
That is, the external lead electrode plate (7) is made of a low-resistance silicon substrate, and has a specific resistance of, for example, 3 to 15/1000Ω.
Using an N-type silicon substrate with a Cl11 thickness of 300 μm, a P-type diffusion region (8) is formed at a position corresponding to the base region (3) by ordinary photolithography technology, selective diffusion Fh, etc., and then this P-type There are N10 diffusion regions (
9).

N+拡散領域(9ンは電極板(7′〉内ですべて連結さ
れている。
The N+ diffusion regions (9) are all connected within the electrode plate (7').

このP−N接合の作り込みはエミッタ領[(4)と絶縁
分離した外部引出し電極を形成するためである。
The purpose of creating this P-N junction is to form an external lead electrode that is insulated and separated from the emitter region [(4).

シリコン基板から成る外部引出し電極板(7′)の一部
には段差(10)が設けられこの段差(10)のN+領
領域9)上に設けた電極(11)からリード線(12)
等を引き出す。ベース電極はベース領M(4)−電極金
B(6)−電極金属(14)−電極板(7′)のN十領
域°−電極金属(15)の経路で外部と接する。
A step (10) is provided in a part of the external lead electrode plate (7') made of a silicon substrate, and a lead wire (12) is connected from the electrode (11) provided on the N+ region 9) of this step (10).
etc. The base electrode contacts the outside through a path of base region M (4) - electrode metal B (6) - electrode metal (14) - N0 area of electrode plate (7') - electrode metal (15).

上記のベース領域(3)、エミッタ領域(4)の上の金
ff1M(5)、(6)のパターン形状に合せてシリコ
ン基板から成る外部引出し電極板(7)の表面上にも金
B電極(13)、(14)が形成されこれらの金属電極
(5)、(13)および(6)、(14)がそれぞれ例
えばすず−鉛(Sn −Pb )系低温ソルダを介して
重ね合ゼ雰囲気炉等を通して外部引出し電極板(7勺と
半導体ペレット(1)とを一体向に接着する。
Gold B electrodes are also placed on the surface of the external lead electrode plate (7) made of a silicon substrate in accordance with the pattern shapes of the gold ff1M (5) and (6) above the base region (3) and emitter region (4). (13) and (14) are formed, and these metal electrodes (5), (13) and (6), (14) are superimposed, for example, through a tin-lead (Sn-Pb)-based low-temperature solder, respectively. The externally drawn electrode plate (7 pieces) and the semiconductor pellet (1) are bonded together through a furnace or the like.

なお、外部引出し電極板(7′)はその外側に配置され
る銅等から成る電極ポスト(図示せず)に接着若しくは
圧接される。
Note that the externally drawn electrode plate (7') is bonded or pressed to an electrode post (not shown) made of copper or the like arranged on the outside thereof.

この発明は上記のように外部引出し電極板(7′)をシ
リコン基板で構成したものであるが、使用するシリコン
基板の厚さが200〜300μ■程度と薄いために抵抗
率の点からは実用1殆んど問題がない。
In this invention, the external lead electrode plate (7') is made of a silicon substrate as described above, but since the thickness of the silicon substrate used is as thin as 200 to 300 μ■, it is not practical in terms of resistivity. 1 There are almost no problems.

すなわち、比抵抗1.2X10−2Ω/C11厚さ30
0μmの単位断面積(cm2)当りの抵抗率は3.6X
10−4Ω程度であり、殆んど問題はない。
That is, specific resistance 1.2X10-2Ω/C11 thickness 30
Resistivity per unit cross-sectional area (cm2) of 0μm is 3.6X
It is about 10-4Ω, and there is almost no problem.

また、この抵抗弁が電力用トランジスタ、ダーリントン
トランジスタ等において一種のバランス瓶代となって特
定個所への電流集中を防ぎ、半導体装置の電気的特性を
改善できる効果がある。
Further, this resistance valve serves as a kind of balance bottle in power transistors, Darlington transistors, etc., and has the effect of preventing current concentration to a specific location and improving the electrical characteristics of the semiconductor device.

さらに従来の1個所又は複数個所から引出すものにあっ
ては、電極金属のパターン形状が複雑な場合には各電極
金属と導通領域との間に横方向抵抗が生じ電流特性を落
す原因ともなっていたが、上記の実施例の場合、全電極
と金属接触するので、そのようなこともない。
Furthermore, in conventional devices that are drawn from one or multiple locations, if the pattern of the electrode metal is complex, lateral resistance occurs between each electrode metal and the conductive region, causing a drop in current characteristics. However, in the case of the above embodiment, this does not occur because all the electrodes are in metal contact.

また、ベース領域(3)、エミッタ領14(4)の外部
引出し電極を同一のシリコン基板によって形成している
が、ベース−エミッタ間の耐圧は、例えば20V程度あ
れば足り、したがってこの実施例のようなP−N接合の
作り込みにより両者の絶縁分離が十分可能である。
Furthermore, although the external lead electrodes of the base region (3) and the emitter region 14 (4) are formed of the same silicon substrate, the withstand voltage between the base and the emitter is, for example, about 20V, and therefore this embodiment By creating such a P-N junction, it is possible to sufficiently insulate and separate the two.

なお、上記の実施例では電力用トランジスタを例にして
説明したが、勿論他の半導体装置、例えばGTOにも適
用できるし、また1つの半導体ペレット内に複数の半導
体装置を作り込んだようなものにも利用できる。さらに
シリコン基板から成る外部引出し電極も必ずしも一体的
である必要はなく複数に分割して使用することができる
Although the above embodiment was explained using a power transistor as an example, it can of course be applied to other semiconductor devices, such as a GTO, or a device in which multiple semiconductor devices are built into one semiconductor pellet. It can also be used for Further, the external lead electrode made of a silicon substrate does not necessarily have to be integral, and can be divided into a plurality of parts.

[発明の効果] この発明は、上記のように半導体ペレットの−1面上に
2つの異なる導電型領域を有するものの外部引出し電極
として同一のシリコン基板を使用し内部のP−N接合に
よって電気的に絶縁するようにしたので半導体装置の構
成が簡単となり、さらに外部引出し電極をシリコン基板
で形成するようにしたので、半導体ペレットの金属電極
が複雑なパターン形状をしていてもフォト・リソ技術、
エツチング処理技術により容易に微細加工ができ、前記
パターン形状に合せた形状の外部引出し電極を容易に形
成することができる。しかもこの場合に形成された外部
引出し電極が全面で半導体ペレッt〜の電極金属に接続
されるために従来のように横抵抗を生じさせず、電力用
トランジスタ、ダーリントントランジスタでは全エミッ
タ領域から効率良く電流が集められ、したがってこれに
より、電気的特性が改善され、また、GTO等のサイリ
スタではナージ耐ωが向上する等の効果がある。
[Effects of the Invention] As described above, the present invention uses the same silicon substrate as the external lead electrode of a semiconductor pellet having two different conductivity type regions on the -1 plane, and electrically conducts the semiconductor pellet by an internal P-N junction. This structure simplifies the structure of the semiconductor device, and since the external lead electrodes are formed on a silicon substrate, photolithography technology and
Microfabrication can be easily performed using etching processing technology, and an external lead-out electrode having a shape matching the pattern shape can be easily formed. Moreover, since the external lead electrode formed in this case is connected to the electrode metal of the semiconductor pellet on the entire surface, lateral resistance does not occur unlike in the conventional case, and power transistors and Darlington transistors can be efficiently connected from the entire emitter region. Current is collected, and this improves electrical characteristics, and in thyristors such as GTO, has effects such as improved surge resistance ω.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、この発明の一実施例を示す半導体装置の概略
構造の断面図である。図において、(1)は半導体ペレ
ット、(2)はコレクタ領域、(3)はベース領域、(
4)はエミッタ領域、(5)。 (6)は金属電極、(7′)はシリコン基板から成る外
部引出し電極板、(8)はP型領域、(9)はN中領域
、(13)、(14)は金属電極である。 出  願  人
FIG. 1 is a cross-sectional view of a schematic structure of a semiconductor device showing an embodiment of the present invention. In the figure, (1) is a semiconductor pellet, (2) is a collector region, (3) is a base region, (
4) is the emitter region, (5). (6) is a metal electrode, (7') is an external lead electrode plate made of a silicon substrate, (8) is a P type region, (9) is an N medium region, and (13) and (14) are metal electrodes. applicant

Claims (1)

【特許請求の範囲】[Claims]  半導体ペレットの一主面側に互いに異なる2つの導電
型領域が形成されこの領域上に電極金属が設けられさら
にこれらの電極金属上にそれぞれ外部引出し電極が設け
られる半導体装置において、前記外部引出し電極を互い
に異なる2つの導電型領域に対して電気的に絶縁するた
めに内部にP−N接合を設けた一枚のシリコン基板で構
成した電極板を前記半導体ペレットの一主面側上に載置
したことを特徴とする半導体装置。
In a semiconductor device in which two regions of different conductivity types are formed on one main surface side of a semiconductor pellet, electrode metals are provided on these regions, and external lead electrodes are provided on each of these electrode metals, the external lead electrodes are provided. An electrode plate made of a single silicon substrate with a P-N junction provided therein to electrically insulate two regions of different conductivity types was placed on one main surface side of the semiconductor pellet. A semiconductor device characterized by:
JP59227800A 1984-10-31 1984-10-31 Semiconductor device Granted JPS61107753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59227800A JPS61107753A (en) 1984-10-31 1984-10-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59227800A JPS61107753A (en) 1984-10-31 1984-10-31 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS61107753A true JPS61107753A (en) 1986-05-26
JPH027182B2 JPH027182B2 (en) 1990-02-15

Family

ID=16866582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59227800A Granted JPS61107753A (en) 1984-10-31 1984-10-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61107753A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0418074U (en) * 1990-06-05 1992-02-14

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