JPS61107474A - Image reduction and conversion device - Google Patents

Abstract

PURPOSE:To provide a reduction image having high quality easily and quickly by performing filtering and adding of picture element information written in a same coordinate address of an image memory, and dividing it by the number of addition to obtain output picture element information. CONSTITUTION:The picture element information written in the same coordinate address of an output image memory 3 is made filtering according to the result of a coordinate conversion calculation circuit 2, and is written in the corresponding coordinate address of the memory 3 sequentially for addition. On the other hand, the number of addition of the picture element information written in the same coordinate address of the memory 3 is found in an adder 6. The picture element information of each coordinate address written in the memory 3 is divided by that number, rewritten in the memory 3. This provides the high quality image easily and quickly, which is scale-down conversion in the memory 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image reduction conversion device that can perform image reduction processing at high speed and easily obtain a reduced image without so-called jagged edges.

[Technical background of the invention and its problems]

Recently, various types of image reduction conversion using computer graphics (CG) algorithms have been performed as one type of image processing for broadcasting. This type of image reduction conversion processing is performed by, for example, finding an input pixel corresponding to a specified output pixel by coordinate conversion processing, and writing information about the input pixel to the output pixel. However, in general, each pixel information of the reduced image obtained by such coordinate transformation tends to be discontinuous, resulting in a so-called jagged image that is difficult to see.

Conventionally, in order to solve such problems, for example, T.
In V Society Technical 11 (TE 8 S 95-a, March 22, 1959), the area for coordinate transformation is divided and image reduction processing is performed using a filter according to the reduction ratio for each area. I have to. However, in order to perform this processing, a complex spatial filter circuit is required, as well as parallel access processing in extremely small areas of the image, making the configuration complicated and the image reduction conversion process unavoidably complicated. Ta.

Furthermore, Japanese Patent Laid-Open No. 58-500635 discloses that the aspect ratio of the original image is set to 1/'2.1. /4... is provided, and a load (filtering) is applied to the pixel information according to the reduction ratio of each memory to obtain a reduced-converted output image, thereby removing the jaggedness described above. There is. However, according to such a processing method, an extra memory is required with the aspect ratio of the original image being 1/2°, 1/4, . . . . Further, there are problems such as the need for separate one-dimensional filter circuits depending on the reduction ratio. Moreover, since image processing needs to be performed in accordance with the difference in reduction ratio, it has been an obstacle to increasing the processing speed.

[Purpose of the invention]

The present invention has been made in consideration of these circumstances, and its purpose is to easily obtain high-quality reduced-conversion images without so-called jagged edges at high speed and with a system having a simple configuration. An object of the present invention is to provide an image reduction conversion device.

[Summary of the invention]

In accordance with instructions for coordinate transformation involving reduction processing of an input image stored in an input image memory, the present invention converts coordinate addresses corresponding to each coordinate address of the input image in an output image memory storing a reduction-transformed image. Control writing of the input image calculated and stored in the input image memory to the output image memory, and at this time, filter pixel information written to the same coordinate address of the output image memory according to the coordinate transformation calculation result. At the same time, the filtered pixel information is sequentially added and written to the corresponding coordinate addresses of the output image memory, and the reduction ratio of the input image at each coordinate address of the output image memory due to the coordinate transformation is calculated. The number of additions of the pixel information written by adding it to the same coordinate address of the output image memory is determined, and the pixel information of each coordinate address written to the output image memory is divided by the number of additions. By rewriting to the output pixel memory, a reduced-converted, high-quality image can be easily and quickly obtained on the output image memory.

In other words, input pixel information written to the same coordinate address in the output image memory under coordinate transformation control with reduction processing is filtered and added, and then the pixel information is divided by the number of additions to produce the final output. By obtaining pixel information, this method effectively simplifies and speeds up processing for obtaining high-quality reduced images.

〔Effect of the invention〕

Thus, according to the present invention, a plurality of pieces of input pixel information written to the same coordinate address of the output image memory as the image is reduced is filtered through a filtering circuit whose load is set according to the coordinate transformation. Since the addition is performed after that, it is possible to easily and quickly obtain output pixel information with added blur according to the reduction ratio. Further, by dividing this by the number of times of addition, it becomes possible to perform normalization according to the reduction rate. Therefore, the filtering process required for the image reduction conversion process is significantly simplified, and the ideal filtering process can be performed at high speed.
Great effects such as being able to obtain a high-quality reduced-conversion image without jaggedness can be achieved.

Moreover, the processing can be easily performed without using a large amount of memory as in the conventional case, and the system configuration can be greatly simplified. Further, the time required for the processing decreases as the reduction ratio increases, and it becomes possible to easily achieve real-time image reduction processing. Furthermore, great effects can be expected, such as substantially the same effect as when simultaneously accessing a wide area, which has been considered difficult in the past, and achieving high-speed processing.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment apparatus, and FIG. 2 is a block diagram showing an example of a coordinate conversion calculation circuit in the apparatus shown in FIG.

The input image memory 1 stores an input image f(x
, y), and the input image f (x, y) stored in the input image memory 1 is stored in the coordinate transformation calculation circuit 2.
The image is reduced and converted under the control of , and written into the output image memory 3. The coordinate conversion calculation circuit 2 receives an instruction for image reduction conversion processing from the kindergarten department 4, and calculates, for example, an input image fI+f(x,
y) coordinate system and reduction conversion output image @ Q (X', V'
), and calculate the coordinate transformation coefficients of the output image g (x, y) corresponding to each coordinate address of the input image f (x, y) in sequence. ing.

This coordinate transformation converts, for example, an input image f (x, y) existing on the x-y plane of an x-y-z seated image system to its x'-yl plane in an x'-yLz' coordinate system with a different viewpoint. It can be interpreted as projecting the output image q(xry') to CJ (x', y') -T -f (X, V)
It can be expressed as a coordinate transformation. In addition, this coordinate transformation can be used, for example, to transform the input image f (x, y) vertically.
□Assuming that it is scaled down horizontally by 1/2, it will appear in Figure 3.
(・, ; As shown schematically, it means writing the information of four consecutive pixels in the vertical and horizontal directions of the input image into one pixel of the output image memory 3. The coordinate conversion calculation circuit 2 uses such coordinates According to the relational expression of transformation T, the coordinate transformation coefficient calculation circuit 2a calculates the transformation coefficient as shown in FIG. 2, and according to the coordinate transformation coefficient, the X coordinate address calculation circuit 2
The x and y coordinate address calculation circuit 2y calculates the converted coordinate address (x'Ly') of the output image memory 3 corresponding to each coordinate address (x, y) of the input image memory 1, respectively. Then, under the control of these coordinate addresses, the input image f(x,
y) is scanned and read out and stored in the output image memory 3.
Writing to is controlled.

Therefore, the reduced pixel information Q (X', V') written to the output image memory 3 is as shown in FIG.
(x, y ), its weighting reduces the weight to W(x, y
) is expressed as. The one-dimensional filtering circuit 5 performs filtering processing on the input image f (x, y) successively outputted from the input image memory 1 by rask scanning for each scan line, and sends the filtering output to the above-described filtering circuit 6 via the addition circuit 6. The corresponding coordinate addresses calculated by the coordinate transformation in the output image memory 3 are sequentially added and written for each scan line. This one-dimensional filtering circuit 5 includes a plurality of pieces of input pixel information f continuous in the rask scan direction, which are converted into the same coordinate address of the output image memory 3 by the coordinate transformation, as shown in FIG. 5, for example.
(X, 1), f (X+1, 1/) ~ f (
x+n-1, y), weighting coefficients W(0), w(1) ~ w(n-1) according to the coordinate transformation
is set to perform filtering processing (product-sum calculation). Through such filtering processing, input pixel information written to the same coordinate address of the output image memory 3 on one line of the rask scan is added. In other words, through this filtering process, the sum of partial products for one line of input pixel information written to the same coordinate address of the output image memory 3 is obtained. Then, this partial product sum is sequentially added and written to the corresponding coordinate address of the output image memory 3 mentioned above for each scan line, and the added value of input pixel information to the same coordinate address (product sum: G (x', V') ) is stored at the corresponding coordinate address.

The reduction rate calculation circuit 7 calculates the reduction rate at each coordinate address of the output image from the coordinate transformation T.

This reduction rate can be calculated by using the four corners of the input image as representative points, and calculating the reduction rate S at each of the four corners, as shown in FIG. 6, for example, and the algorithm for calculating the reduction rate shown in FIG. 7. From each of the reduction ratios S at these four corners, an approximate formula for the reduction ratio is determined by the method of least squares, etc., as a variable X of the output address.

This is done by calculating the reduction ratio G (x', y') of each coordinate point according to this approximate formula.

From the reduction ratio S(x':y') at each coordinate address of the output image calculated in this way, the number of input pixel information written at each coordinate address of the output image memory 3,
In other words, the number of times input pixel information is added is determined.

The division circuit 8 obtains information on the number of additions of the input pixel information at each coordinate address of the output image memory 3, and
The information stored in each coordinate address of the output image memory 3 is divided by the number of additions, and the division result q(x'
, y') are rewritten into the output image memory 3. The output pixel information is normalized by this division process, and an output image g(x', y') obtained by reducing the image is obtained in the output image memory 3. In addition, the division circuit 8 is
For example, a ROM whose address is the product-sum value and the number of additions.
By creating a table using , and then using this ROM table, it is possible to speed up the division process.

Thus, according to the present apparatus, image reduction processing can be performed very efficiently, simply, and at high speed as described below. In other words, in linear coordinate transformations such as two-dimensional coordinate transformations and three-dimensional coordinate transformations for images, if we focus on the reduction rate and the continuity (no sudden changes) in one area of the reduced partial product. , it is possible to quickly and easily perform the blurring operation (removal of jagged edges) in the reduction process. In view of this, in this device, the above-mentioned
The dimensional filtering circuit 5 performs partial product sum processing for one scan line on the input image side, and then writes the partial product sum processing result to the corresponding output pixel coordinate address to obtain the product sum value G (x', y'). Therefore, it is possible to easily and quickly perform two-dimensional filtering processing associated with image reduction conversion.

Furthermore, if the filtering weight is determined in accordance with the coordinate transformation T as described above at this time, it becomes possible to perform a simple and ideal filtering process.

After that, the sum of products G (×, ′y′
) can be normalized according to the reduction rate of the coordinate address, so it is possible to easily and quickly obtain a high-quality, jagged-free reduced image while maintaining the continuity of the image reduction rate.

Further, reduction conversion processing can be efficiently executed with a simple system configuration without preparing a large amount of image memory as in the conventional case. Therefore, it becomes possible to simplify the device configuration, and a great practical effect can be achieved.

Note that the present invention is not limited to the embodiments described above. For example, if the reduction ratio for an input image changes continuously from enlargement to reduction, the enlargement can be performed using the conventional inverse conversion method, and the reduction can be performed by switching the conversion mode and processing as described above. . Furthermore, it is also possible to configure the division circuit by including it in a one-dimensional filtering circuit to further simplify the configuration. Furthermore, the number of additions of pixel information to the same coordinate address can be easily calculated from the above-mentioned approximate formula for the reduction ratio, and the number of input pixels output to the same coordinate address in one line also follows the coordinate transformation T. It can be calculated in advance. Therefore, the number of additions on one line relative to the total number of additions can be easily determined, and the above-described processing can be easily performed using this information. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a coordinate transformation calculation circuit in the embodiment device, and FIGS. 3 and 4 are corresponding coordinate addresses for reduction transformation. Figure 5 is a diagram showing the concept of one-dimensional filtering processing, Figure 6 is a diagram showing the concept of reduction rate calculation, and Figure 7 is a diagram showing the algorithm of reduction rate calculation. be. 1... Input image memory, 2... Coordinate transformation calculation circuit,
3... Output image memory, 4... Control unit, 5... 1
Dimensional filtering circuit, 6... Addition circuit, 7...
Reduction ratio calculation circuit, 8... division circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 3 Prisoner 6 Figure 7

Claims (4)

[Claims] (1) means for calculating coordinate addresses of the output image memory corresponding to each coordinate address of the input image when reducing and converting the input image stored in the input image memory and writing it to the output image memory; A filtering circuit that filters pixel information read from the image memory and written to the same coordinate address of the output image memory, and an addition that sequentially adds and writes the filtered pixel information to the corresponding coordinate address of the output image memory. circuit and
means for calculating a reduction rate of the input image at each coordinate address of the output image memory accompanying the coordinate transformation, and calculating the number of input pixels to be added and written to the same coordinate address of the output image memory; An image reduction conversion device comprising: a division circuit that divides pixel information of each coordinate address written in an output image memory according to the number of input pixels and rewrites the divided information in the output image memory. (2) Filtering is performed according to the two-dimensional area of the input image written to the same coordinate address of the output image memory.
2. The image reduction conversion apparatus according to claim 1, wherein the image reduction conversion apparatus is configured to perform the image reduction conversion by determining two-dimensional filtering coefficients for pixel information in a dimensional area. (3) The reduction ratio for each coordinate address in the output image memory is calculated by each representative point coordinate address of the image, and an approximate formula for the reduction ratio that connects these representative point coordinate addresses with each other is determined by the method of least squares. An image reduction conversion device according to claim 1, wherein the image reduction conversion device is an image reduction conversion device. (4) The image reduction/conversion device according to claim 1, wherein the division circuit is constituted by a ROM in which a table is configured in which addresses are added values of pixel information and the number of additions thereof.