JPS61105866A - Charge transfer device - Google Patents

Abstract

PURPOSE:To receive signal charge perfectly transmitting analog signals with high precision by a method wherein the width of storage gates in charge storage part of serial registers is patterned-coupled equally or wider up to coupling points of parallel registers. CONSTITUTION:The width of storage gates 13 formed of the first polysilicon in the direction toward parallel registers 3l is patterned equally up to a shift gate 40 formed of the third polysilicon. The channel width is narrowed at output ends of storage gates 1l3 as well as below the shift gate 40 to minimize the narrow channel effect if any since the potential on transfer gates 14 formed of the second polysilicon is specified not to exceed the potential on the storage gates 13. Therefore, a signal charge may be transferred easily to the parallel registers 3 by means of selecting shift gate voltage. Furthermore, the minimal narrow channel effect may be canceled by fringing fields P of shift gate 40 to receive signal charge perfectly transmitting analog signals with high precision.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a charge transfer device capable of temporarily storing analog signals.

(Prior art) Conventionally, as a technology in this field, there are the following: Transactions of the Institute of Electronics and Communication Engineers, J66-0 [:9] (1983-9) P.
There was one described in 69B.

The configuration will be explained below using figures.

FIG. 2 is a top view of a conventional digital COD field memory in which the memory is constructed using a charge transfer device (hereinafter referred to as 00D). This memory is an input serial register (Input Serial Register)
1 and output serial register (0output Seri
It has a so-called SPS structure in which a parallel register 3 is connected between it and alRegister) 2. Here, the input serial register 1 includes an input section 11 consisting of an input diode (2), an input gate (G), etc., and multiple stages of registers 12-1 to 1z-n (however, 12-1
is a 1-stage register, 12-2 is a 2-stage register, ...12
It has a structure in which n stages of -n (referred to as registers) are arranged in - lines. Similarly, the output≠wo→serial register 2 connects multiple stages of registers 21-1 to 21-n and an output section 22 consisting of an output OG'(OG'), an output diode (OD), etc. It has a structure arranged in. In addition, the parallel register 3 has a large number of registers 31-1 to 31-n arranged in - columns in parallel in many stages (m stages), and the registers 31-1 to 31-n for each column are arranged in parallel.
, 3m-1 to 3m-n are connected to channel stoppers 3, respectively.
It has a structure separated by 2.

FIG. 3 is a structural diagram of the input serial register 1 in FIG. 1. This input serial register 1 adopts a CD, and each stage of registers 12-1 to 12-0 in FIG. 1 is composed of a storage gate 13 and a transfer gate 14. In each storage gate 13, each parallel register 31- in FIG.
It is estimated that 1 to 31-n are connected to each other. In FIG. 3, each storage gate 13 is separated by a channel stopper 15 shown by diagonal lines, and the direction of charge transfer is shown by an arrow.

The operation of the digital OOD field memory configured as above will be explained. First, an input signal is given to the input section 11 of the input serial register 1 in FIG.
After inputting to the registers 2-1 to 12-n for the line, the signals of the registers 12 to 1 to 12-n of each stage are simultaneously transferred to the registers 31-1 to 31-n of the first stage in the parallel register 3. do. The signals sent to the first-stage registers 31-1 to 31-n are sequentially output in parallel from the second-stage registers 32-1 to 32-n to the m-th registers 3m-1 to 3m'-n. is sent to serial register 2. The -line signal sent to the output serial register 2 is output from the output section 22 of the output serial register 2.

Here, the input serial register 1 inputs signals for - lines at high speed. The parallel register 3 operates to transfer one bit while inputting the signal to the input serial register 1 and send the signal to the output serial register 2. The output register 2 operates to read the signal sent from the parallel register 3 at high speed in the same manner as the input serial register 1.

In the above-mentioned digital COD field memory, details are not described regarding the pattern combination part (for example, part A in FIG. 2) between the input serial register 1 and the parallel register 3, but generally the part shown in FIG. a)～
A structure like (C) is adopted. Here, FIG. 4(a) is a top structural view of part A in FIG. 2, and FIG. 4(1)
) is a schematic BB-B sectional view of FIG. 4(a), and FIG. 4(
C) is a potential diagram corresponding to the cross section of FIG. 4(b).

As shown in FIG. 4(a), the input serial register l
The registers 12-1 to 12-5 in each stage have a structure in which a transfer gate 14 is stacked on a storage gate 13 (overlapping structure). A shift gate 40 for transferring signal charges in parallel from the input serial register 1 to the parallel register 3 is stacked on the lower end of the input serial register 1. Further, below the shift gate 40, the first stage registers 31-1 to 31-n in the parallel register 3 are stacked, and the second stage registers 32-n are stacked on top of the first stage registers 31-1 to 31-n. 1
~32-n, and second stage registers 32-1 to 32-
Third-stage registers 33-1 to 33-D, etc., are arranged on top of each other in order.

In FIG. 4(a), the area surrounded by the diagonal line with two-dot chain lines indicates the channel area divided by the channel stoppers 15 and 32, and the horizontal channel area 41-1 of this channel area is for input. It is formed in the N- area of the serial register 1 and transfers the input signal in the horizontal direction, and the vertical channel areas 41 to 2 of the channel areas are formed in the ON- area of the parallel register 3 to transfer the input signal in the vertical direction. It is intended to be transferred to The constricted vertical channel region 41-3 located at the junction between the input serial register 1 and the parallel register 3 is still P-
It is formed in the channel region and bridges the channel regions 41-1 and 41-2. In addition, L is the channel width of the channel 41-3, L2 is the channel length of the channel 41-3,
C indicates the constriction at the upper end of the channel 41-3, and the arrow indicates the direction of transfer of the human input signal.

Furthermore, as shown in FIG. 4(b), the connecting part between the manual serial register and the parallel register 3 is made of P-type Si.
an N- region 51 formed on the substrate (P-81) 50;
It consists of a P-dose region 52 doped into the N- region 51 to form a channel, a channel strike 15 consisting of the N- region and a P+ region formed on the substrate p-st, and 5102 formed on the P+ region. Field oxide film 53
, a gate oxide film 54 formed on the N- region and the P-dose region, and a storage gate 13 in the second stage register 2-2, which is made of polySt formed on the oxide film layer 54, respectively. , a shift gate 4o, and a first stage register 31-2. In addition, Fig. 4 (bJ
In the figure, L3 is the depth of the buried layer which is the N- region, and L4 is the thickness of the gate oxide film.

Then, as shown in FIG. 4(a), if a potential well is drawn by taking the potential X in the vertical direction (however, the potential becomes higher in the downward direction), when the shift gate 40 is off, it will look like a solid line. A depletion layer is formed and the input signal charge Q is accumulated in the shaded area, and then when the shift gate 40 is turned on, the potential X of the channel 41-3 increases as shown by the broken line and the signal charge Q is transferred to the left (in the direction of the arrow), transferred to the output serial register 2 via the channel 41-2 of the parallel register 3, and output.

(Problems to be Solved by the Invention) However, in the device having the above configuration, the potential , -a becomes low, a narrow channel effect occurs at the constricted portion C, and a phenomenon occurs in which the signal charge Q is not completely transferred and a portion of it ΔQ is left behind. In addition, the remaining signal charge Q, △Q, is due to variations in the manufacturing accuracy of the wafer process, so the amount left behind at each serial register stage is
2-1 to 12-n, and the remaining amount ΔQ differs for each serial register stage 12-1 to 12-n, and this appears in the output as fixed noise. Therefore, in the conventional device, Due to large transfer losses, it is difficult to transfer analog signals with high precision, and only digital signals can be transferred.

51st EI (a), ('b) is embedded channel k CC
! FIG. 3 is a diagram showing the dependence of potential on channel width and channel length in D (BOOD). That is, in FIG. 5 (al, (1)), the depth L3 of the buried layer is about 1 μm as shown in FIG.

BOC with gate oxide film thickness L4 of approximately 5002! The potential X when the measurement current (channel current) in D is 1 μA is plotted against the channel width Ll and the channel length L2. As is clear from FIG. 5, the smaller the channel width L□ and the channel length L2, that is, the smaller the pattern, the larger the narrow channel effect becomes, which becomes a particular problem during miniaturization.

As mentioned above, in the conventional device, since there is a constriction C in the pattern under the same gate, a narrow channel effect occurs and the signal charge Q is left behind, and the leftover amount △Q also increases in each serial register. Stages 12-1 to 12-n
There was a problem that it was not uniform.

This invention solves the problems that the prior art had,
The object of the present invention is to provide a charge transfer device that solves the problems of signal charges left behind due to narrow channel effects and variations in the amount left behind, and can handle analog quantities without leaving any signal charges behind.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a charge transfer device in which a pattern connection point from an input serial register to a parallel register is changed to The storage gate width of the storage section is at least the same width up to the connection point of the parallel register, or is pattern-coupled so that it widens toward the parallel register. Here, the connection point of the parallel register also includes a switch control electrode (shift register) that transfers charges from the input serial register to the parallel register in parallel.

(Function) According to the invention, since the charge transfer device is configured as described above, the narrow channel effect does not occur under the storage gate, and therefore the above-mentioned problem can be eliminated.

(Embodiment) FIGS. 1(a), (b), and (C) are explanatory diagrams of a COD field memory showing an embodiment of the present invention, and FIG. 1(a) is an illustration of an input serial register and a parallel register. A top structural view of the pattern bonding part (part A in FIG. 2), FIG. 1 (1)) is a schematic cross-sectional view taken along line D-D in FIG. 1 (a), and FIG. It is a potential diagram corresponding to the cross section of (1)). Note that the same elements as those in FIGS. 2 to 5 are given the same reference numerals.

The difference between this COD field memory and the one in FIG. 4 is that each stage of registers 12-1 to 12-n constituting the input serial register 1 is shown in FIG. 1(a).
The width of each storage gate 13 is made approximately the same width up to the connection point E of the parallel register 3. Here, the connection point E of the parallel register 3 refers to the connection point between the end of the storage gate 13 and the shift gate 40, and the input serial register 1 connects the parallel register 3 in parallel.
It also includes a shift gate 40 for a switch to transfer charge. In this embodiment, since the storage gate 13 has approximately the same width up to the connection point of the shift gate 40, the potential X under the storage gate 13 has the same height as shown in FIG. 1(C). Become. In addition, Figure 1 (C
), F is the fringing field of the shift gate 40.

Next, in order to clarify the structure of the COD field memory according to this embodiment, the manufacturing method will be explained in the sixth Eli3N4.
% and 102 sieves for masks. Next, Fig. 6 (b)
), the thick oxide called field oxide film was oxidized by photoetching to remove S''2 m and S'3N4 J in areas other than the active area, and a thin 5 inch diagonal oxide layer was attached to the active area. , C.O.
After ion-implanting phosphorous P to form the buried channel D and growing the N-region by OV'D (chemical vapor deposition), the first polysilicon is photo-etched into a predetermined shape. to form a gate electrode. And Figure 6 (
As shown in f), after removing an unnecessary thin oxide film and forming a second gate oxide film, barrier ion implantation is performed to determine the charge transfer direction of COD in one direction, and a P-dose region is formed. .

At this time, photoetching is performed to form a predetermined pattern for barrier ion implantation.

After boron ions are implanted, the width of the storage gate 13 formed by the third polysilicon film in the direction toward the parallel register 3 is uniformly spread within the range of 40 mm of the shift gate formed by the third polysilicon film. It is.

Thereafter, a conductive layer (that is, a diffusion layer) opposite to that of the P-type 81 substrate is created by ion-implanting arsenic, for example, into the drain part for signal input and the source part for signal output, etc., and an electronic circuit is formed. And as shown in Figure 6(h),
After growing an intermediate J called PSG by OVD, a hole is made in the bonding pad part to establish electrical continuity with the third polysilicon and the outer cage of the diffusion layer, and then a sink hole is made to stabilize the circuit operation. The device manufacturing process is completed by performing heat treatment.

Next, the operation of the cylinder making shown in FIG. 1 will be described in the case where the input serial register 1 is of a two-phase drive type.

13, the second polysilicon electrode! ”-) Lance 7 Age)
14 is selected. At this time, the potential under the storage gate 13 is selected to be higher than the potential under the transformer 7 agate 14, so the first stage register 1
The transfer gate 14 in 2-1 is placed on the front side, and the storage gate 13 is placed on the rear side, so that the same pulse voltage is applied. 2nd stage register 1
In 2-2, the transfer gate 14 and the storage gate 13 are similarly arranged in this order, and a pulse with a phase opposite to that of the first stage is applied. Since it is a two-phase drive system, the first stage electrode that applies the pulse and the second stage electrode that applies the opposite phase pulse are arranged alternately in the third stage, fourth stage, etc. to form an input serial register. 1. Although not shown, the transfer of signal charges in the input serial register l is carried out by rolling the signal charges under the electrode with the highest potential (i.e., the deepest of the potential well) due to two-phase clock pulses. In addition, the channel 41-1 that performs the transfer has one side connected to the upper channel stopper 1, as shown by the diagonal line of the horizontal two-dot chain line in FIG. 1(a).
5, and since the potential of the shift gate 40 on the lower side is lower than the potential of the input serial register 1, signal charges are blocked there, and this becomes the other end of the channel.

When the above clock pulse stops, i.e. jHl or I
When the potential of L level is constant, signal charges are accumulated under the storage gate 13. When the shift gate 40 is turned on in this state, as shown in FIG. 1(C),
The signal charge accumulated under the storage gate 13 is transferred to the first stage registers 31-1 to 31-n of the parallel register 3.
will be forwarded to. At this time, according to this embodiment, the storage gate 13 is connected to the connection point of the shift gate 40 (see FIG. 1(a)).
, Since the width is the same up to E) in (1)),
(XJ) where no narrow channel effect occurs.

In other words, since the transfer gate 14 formed of the second polysilicon shown in FIG. Channel width is narrow. However, unlike the conventional device shown in FIG. 4(a), where the channel width is narrow within the same gate, the channel width is narrowed below the shift gate 40, so even if a narrow channel effect occurs, it is very small. Therefore, by selecting the shift gate voltage, it becomes possible to sufficiently transfer the signal charge to the parallel register 3. Moreover, shift gate 4
The ringing field (F part in Figure (Q)) also works and cancels out the slight narrow channel effect mentioned above, so no signal charge is left behind, and therefore analog signal transfer can be performed with high precision. I can do it.

FIGS. 7(a) to (C) show other embodiments of the present invention.
These are explanatory diagrams of the 0D field memory, in which FIG. 7(a) is a top view structural diagram of the pattern connection portion of the input serial register 1 and parallel register 3, and FIG. 7('b) is a
7(C) is a potential diagram corresponding to the cross section of FIG. 7(b).The same elements as those in FIG. A symbol is attached.

This embodiment differs from the previous embodiment in that the storage gates 13 of each stage of the input serial register 1 are pattern-coupled so that the width thereof increases toward the shift gate 14. Therefore, as shown in Figure 7(C), the potential well below the storage gate 13 is shifted
40 (that is, the potential It can be sent to parallel register 3. That is, especially signal type, load-IJ
When Q is small, the region of the highest potential is narrower in this embodiment than in the above embodiment, and therefore the storage capacity in the transfer direction indicated by the vertical arrow in FIG. 7(a) is Since the electrode length of the gate electrode 13 is shortened, charge transfer to the parallel register 3 can be accelerated, which has the advantage of being suitable for higher speeds.

Note that in the above embodiment, the input serial register 1 is
Although the case of the phase drive force type has been described, it goes without saying that other drive systems such as three-phase, four-phase, etc. can be similarly applied.

(Effects of the Invention) As described above in detail, according to the present invention, the width of the gate electrode of the charge storage section in each stage of the input serial register is set to be the same width or to increase toward the connection point of the parallel register. Since the patterns are coupled to each other, the problems of signal charge left behind and variations in the amount left behind due to the narrow channel effect are eliminated, and therefore analog signals can be transferred with high precision.

[Brief explanation of drawings]

FIGS. 1(a) to (C) are CODs showing embodiments of this invention.
An explanatory diagram of the structure of a field memory. Figure 2 is a top view of a conventional digital COD field memory.
Structure diagram of the input serial register in the figure, Figure 4 (a)
~(C) are structural explanatory diagrams showing pattern combinations of input serial registers and parallel registers in conventional devices, FIGS. 5(a) and (b) are operational explanatory diagrams of FIG. 4, and FIG. 6(
a) to (a) are manufacturing process diagrams of the device shown in Fig. 1, and Fig. 7 (a)
-(1)> are structural explanatory diagrams of a COD field memory showing other embodiments of the present invention. 1... Serial register for input, 2... Serial register for output, 3... Parallel register, 12-1~
12-n...Register of each stage of the input serial register, 13...Storage gate, 14...Transfer gate), 21-1 to 21-n...Register of each stage of the output serial register Registers, 31-1 to 31-n, ~
3n-1 ~ Applicant's agent Yasushi Kakimoto (
A) χ fresh 4 otsu meng! (A) χ41 恢V Mengbeng b tsu＼鴫＼gin 1 n'2 Procedural amendment (method) March 6, 1985

Claims (1)

[Claims] A plurality of charge storage sections each having a gate electrode having an input/output terminal for an input signal are arranged in series, and an input signal is transferred along a signal transfer channel formed by these charge storage sections. a serial register for input, a parallel register arranged on the output end side of the plurality of gate electrodes and configured to transfer signal charges applied from the plurality of charge storage sections in parallel, and an output terminal of the plurality of gate electrodes. and a control electrode that is provided at a connecting portion with the parallel register and simultaneously transfers signal charges applied from the plurality of charge storage sections to the parallel register, the charge transfer device comprising: A charge transfer device characterized in that the plurality of gate electrodes are formed so that an effective width of the plurality of gate electrodes is equal to or larger than an input end width of the gate electrodes over a signal transfer channel width of the input serial register.