JPS61105116A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To obtain a stable output level against manufacturing tolerance by connecting a resistor and a diode in series between collectors of the 1st and 2nd transistors (TRs) so that the current path is formed only in a direction from the collector of the 2nd TR to the collector of the 1st TR. CONSTITUTION:When a resistor R2 has a small value or a hfe is large for example, a base potential of an output TR is high and the output high level is increased. In this case, a potential difference V between both the collectors of a differential amplifier is increased and a current I2 flowing through a D1 and an R4 connected between both the collectors increases to decrease the base potential and a prescribed output High level is obtained. When the R2 is large or the hfe is small conversely, the current I2 is small, the effect onto the base potential is not almost given and the output level is made constant. That is, the variance in the base potential of the output TR due to the variance in the manufacture appears as a current difference by the elements connected between both collectors, the output level is always kept almost constant.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor logic circuits, and particularly to an "interface to 10" logic circuit among ECLfi logic circuits.

[Prior art]

ECL type logic circuits generally include logic circuits with input and output levels collectively referred to as "10 interfaces" and logic circuits with input and output levels.
There is another logic circuit with input/output levels called ``100K Interface''. The two are distinguished by the difference K in power supply voltage and output characteristics. As shown in FIG. 3, the output characteristics of the ECL type logic circuit "interface to 10" have a margin of about 150 mV on the high/low side of the output.

Because it is extremely small at 200m"/200m", it is necessary to be very careful in circuit design.While the element performance itself has improved due to miniaturization due to advances in process technology, sufficient compensation has not been made for manufacturing variations. At present, this is a huge burden both in circuit design and manufacturing.The output level will be explained below using the diagram below.

Figure 4 is a circuit diagram of the conventionally used "lOK interface", which consists of a constant current circuit consisting of a transistor Q and a resistor R8, a differential amplifier consisting of Ql and Q, and an output transistor Qout. FIG. The emitter of the output transistor is RT50Ω,
■ A load of yas-2V is connected, and the output high level (vOH) or output low level (v
ot, ). voH is the output transistor QoutO
Forward voltage vfoHk output pace current. It is determined by the sum of the potential drop due to l (and resistor R2, and voL is QO
It is determined by the forward voltage vIoL of ut, the potential drop due to the output base current 'BQL, the constant current I determined by the transistor QB, the resistor R8, and the drop potential due to the resistor K.

V, )H= V7oH−)−IBoHx R1= −・
...” -・” (11vOL = vfoL10(I
eob + It)
2) The amount of change in the forward voltage vf due to changes in current density is small, and I, x R, is designed to remain almost constant despite manufacturing variations in the device, so variations in output level are caused by the resistance of the base current. It is represented by the variation in potential drop due to K.

Kokote V. H=-0,9v, Vot, =-1,r
V tort output current 'OH = 22 mi, IO
L = 6 mA, and the current amplification factor (hereinafter referred to as hl) is 50. Assuming Uma-Tori-3000, the potential drop due to this base current is 132 mV, respectively.
36 rytV. On the other hand, the amount of change in this potential drop due to variations in manufacturing conditions, especially variations in AI and resistance, is, for example, when hf, = 200, the potential drop is 33 mV and 9 mV, and compared to when hl, = 50, it is 99 mV. , 27mV level becomes high. Also, if the resistance variation is ±20%, it is 2671! ■.

The amount of change is 7mV. v. For L, margin 200
7 mV to 27 pain V against folding VK, no problem.
.

Hamage 7150mV on the vou side 26-99 for K
This is a very large value of 1yLv.

Further, the amount of variation bV7 of the forward voltage vf of the transistor due to jf fluctuation during manufacturing has a proportional relationship with Af (-5V7=
= xA, x: constant), and the special K Af is large ~ ・V. , Lf) There is almost no margin on the High side. This is shown in FIG.

As mentioned above, in the conventional example, it is extremely difficult to compensate for the manufacturing +i fluctuation by adjusting the output level, especially the H1gh side level.

[Problem that the invention seeks to solve]

An object of the present invention is to provide a circuit that compensates for manufacturing variations to obtain a stable output level.

[Means for solving problems]

In an ECL type logic circuit collectively referred to as "rioK interface", this logic circuit exhibits diode characteristics only in one direction from one end of the load resistor of the differential amplifier connected to the base of the output transistor to the end of the other load resistor. It is characterized by being connected by an element and a resistor.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows one embodiment of an ECL type logic circuit according to the present invention. Conventionally, the load resistance type 4 of the differential amplifier is not connected, but in the present invention, the diode D and the resistor R4 are connected.
is connected from the base side of the output transistor to the other end via. Current through this connection is only unidirectional;
In the reverse direction, the diode D1 is reverse biased, so there is no effect on the output Low level voL. It will only work on H level.

When the output is at High level, the potential difference d between both collectors of the differential amplifier is Δ:V=I, xR, -I. □× Toto. Normally, I, x R, is designed to be approximately constant value 5 despite manufacturing variations in the device. Since H×Tori is the base potential of the output transistor, the variation in the output transistor is the variation in the pace potential and appears as a four-dimensional variation. For example, when the resistance value is small or when hl is large, the pace potential of the output transistor becomes high and the output H1gh level becomes high. In this case d
increases, and the current RIt flowing through Dl and R1 connected between both collectors increases, lowering this pace potential and obtaining a predetermined output High level. On the other hand, if the current is large or Af is small, the current is small and the output level is constant with almost no effect on the pace potential. That is, variations in the pace potential of the output transistor due to manufacturing variations are detected as a 'IE potential difference between the two collectors of the differential amplifier, and this is seen as a current difference by the element connected between the two collectors. Therefore, the output level can always be kept almost constant.

When the output is at a low level, the diode D is reverse biased, so no current flows between the collectors of the differential amplifier and there is no effect on the level.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to maintain a stable output level despite manufacturing variations in elements.

[Brief explanation of the drawing]

41 is one embodiment of the present invention; ig2 is the output level according to the implementation array according to the present invention; FIG. 3 is the output level standard of the ECL type logic circuit and the conventional output level; FIG. 4 is the ECL type Sabaku. 1 is a conventional example of a circuit. QI, Qt, Q3, Qout ・・・・・・・・・・・・
...Transistor R,,R,,R3,R4,RT
・・・・・・・・・Resistance “IS, 凰Vcs ・−−−−−−−・・−・−−−−−−・−=
Pace signal......
・・・・・・・・・・・・・・・・・・・・・Diode Figure 1 1 degree Ta ('c') Figure 2 Yo

Claims (1)

[Claims] a transistor pair in which the emitter of the first transistor and the emitter of the second transistor are connected to form a current switching switch; and a third transistor whose base is connected to the collector of the second transistor and which operates as an output transistor. In the emitter-coupled logic circuit configured by the collector of the first transistor and the collector of the first transistor such that a current path is formed only in the direction from the collector of the second transistor to the collector of the first transistor. A semiconductor logic circuit characterized in that a resistor and a diode are connected in series between the collector of the transistor No. 2.