JPS61104495U - - Google Patents

Info

Publication number
JPS61104495U
JPS61104495U JP18965684U JP18965684U JPS61104495U JP S61104495 U JPS61104495 U JP S61104495U JP 18965684 U JP18965684 U JP 18965684U JP 18965684 U JP18965684 U JP 18965684U JP S61104495 U JPS61104495 U JP S61104495U
Authority
JP
Japan
Prior art keywords
clock signal
display
circuit
sequential scan
scan timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18965684U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18965684U priority Critical patent/JPS61104495U/ja
Publication of JPS61104495U publication Critical patent/JPS61104495U/ja
Pending legal-status Critical Current

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Landscapes

  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案の１実施例を示す回路図である。 １はデイスプレイ インターフエース、２と５
はドライブ用トランジスタアレイ、３は７セグメ
ントＬＥＤ、４はデコーダ、８は再トリガー可能
形ワンシヨツト回路である。 The drawing is a circuit diagram showing one embodiment of the present invention. 1 is the display interface, 2 and 5
3 is a drive transistor array, 3 is a 7-segment LED, 4 is a decoder, and 8 is a retriggerable one-shot circuit.

Claims (1)

【実用新案登録請求の範囲】 (1) 複数ないし多数桁表示器を少数のデコーダ
／ドライバにより時分割で一定周期ごとにくり返
し点灯させ、全表示器が同時に点灯しているよう
にみせかけるようにしたダイナミツク デイスプ
レイ回路において、表示器の順次走査タイミング
用クロツク信号の動作を常時監視する手段と、こ
れによりクロツク信号の停止を検出した場合には
表示器に前置されたこれらのドライブ素子の全て
の入力端をリセツトするようにした手段とを具有
していることを特徴とする、ダイナミツク デイ
スプレイ回路。 (2) クロツク信号をトリガー入力として再トリ
ガー可能形ワンシヨツト回路を使用した監視手段
と、これによりクロツク信号の停止を検出した場
合にデコーダを介して表示器のドライブ素子入力
端の全てがリセツトされるようにしたゲート回路
とを具有していることを特徴とする、実用新案登
録請求の範囲第１項に記載のダイナミツク デイ
スプレイ回路。[Claims for Utility Model Registration] (1) Multiple or multi-digit displays are lit repeatedly at regular intervals in a time-division manner using a small number of decoders/drivers to make it appear as if all the displays are lit at the same time. In the dynamic display circuit, there is a means for constantly monitoring the operation of the clock signal for the sequential scan timing of the display, and a means for constantly monitoring the operation of the clock signal for the sequential scan timing of the display, and a means for constantly monitoring the operation of the clock signal for the sequential scan timing of the display, and when it is detected that the clock signal has stopped, all of these drive elements installed in front of the display are 1. A dynamic display circuit comprising means for resetting an input terminal. (2) Monitoring means using a re-triggerable one-shot circuit using the clock signal as a trigger input, which resets all drive element input terminals of the display via a decoder when a stop of the clock signal is detected. The dynamic display circuit according to claim 1 of the utility model registration, characterized in that it comprises a gate circuit as described above.
JP18965684U 1984-12-14 1984-12-14 Pending JPS61104495U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18965684U JPS61104495U (en) 1984-12-14 1984-12-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18965684U JPS61104495U (en) 1984-12-14 1984-12-14

Publications (1)

Publication Number Publication Date
JPS61104495U true JPS61104495U (en) 1986-07-03

Family

ID=30747106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18965684U Pending JPS61104495U (en) 1984-12-14 1984-12-14

Country Status (1)

Country Link
JP (1) JPS61104495U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021784U (en) * 1988-06-14 1990-01-08

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021784U (en) * 1988-06-14 1990-01-08

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