JPS61103347A - Input disconnection detecting system - Google Patents

Abstract

PURPOSE:To decide surely input disconnection by applying the result of compari son between a reception equalization output signal and a threshold value and a clock having an intermediate phase of an identifying point of the reception equalization signal to an FF and allowing a calculation discriminating circuit to count an output of the FF. CONSTITUTION:The reception signal is subject to amplification 1, equalization 2 and fed to an identification circuit 3, a clock regenerating circuit CLK4 and a comparator circuit 5. The CLK4 generates a clock signal CK selecting a timing identified by the identification circuit 3, generates a clock ck having a phase different from that of the signal CK by 180 deg., and the clock ck is fed to a clock terminal C of the FF6. The comparator circuit 6 uses transistors (TRs)Q1, Q2 to compare the threshold value Vcc.R6/(R6+R7) and the input signal, and when the input signal is larger than the threshold value, logical H is outputted and fed to a data terminal D of the FF6. The output of the FF6 is fed to a count decision circuit 7, and when the count within a prescribed time exceeds a prescribed value, an alarm is outputted (8). Thus, the input disconnection is detected accurately.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention identifies S/N deterioration of a received equalized output signal in a receiving device for optical signals or electrical signals, and is capable of detecting signals that may cause false identification. The present invention relates to an input disconnection detection method that detects a drop in input level or the like as an input disconnection.

[Conventional technology]

In a receiving device in a data transmission system, the received signal is amplified by an amplifier, transmission distortion is corrected by an equalization circuit, and an identification circuit compares the received signal with a predetermined darkness value at the timing of a clock signal. It reproduces the signal. If the input signal to this receiver is cut off or drops below a specified level, the S/N of the output signal of the equalization circuit will deteriorate, causing erroneous identification in the identification circuit and preventing the original signal from being reproduced. Therefore, there is a problem that the equipment at the subsequent stage may malfunction.

For this purpose, a detection means is provided that outputs an alarm signal when an input interruption or level drop is detected.

For example, FIG. 3 is a block diagram of main parts of a conventional optical signal receiving device, in which 10 is a photoelectric conversion circuit (0/E), 11 is an amplifier (AMP), 12 is an equalization circuit (EQL), 13
14 is an identification circuit (DEC), 14 is a clock regeneration circuit (T(M)) that regenerates the clock signal, and 15 is a peak detection circuit (PDET) that detects the peak of the regenerated clock signal.
).

A digital optical signal received via an optical transmission line made of an optical fiber or the like is converted into an electrical signal by a photoelectric conversion circuit 1.0 and applied to an amplifier 11, and is then adjusted to a constant level by an amplifier 11 having an AGC function. amplified. This amplified output signal is applied to an equalization circuit 12 to correct transmission distortion. This equalized output signal is applied to an identification circuit 13 and a clock regeneration circuit 14, and a clock signal regenerated by a tongue circuit or the like in the clock regeneration circuit 14 is applied as an identification timing signal to the identification circuit 13, and the equalized output signal is is compared with a predetermined darkness value at this identification timing,
The original signals "1" and "0" are reproduced and output.

The peak detection circuit 15 also has a time constant circuit that holds the peak value of the clock signal reproduced by the clock reproduction circuit 14, and when the clock signal is not output for a predetermined period, the hold level decreases according to the constant of the time constant circuit. So, at that time, input ゛'11 yo, aa, -4
□Yokao, 6o7a.

[Problem that the invention seeks to solve]

When data is transmitted in a format that does not have a limit on the length of consecutive “0” or “1” of the received RZ optical signal, or even if the length is limited, a continuation that exceeds the limit length due to a 1-bit error may occur. If it becomes longer, the level of the reproduced clock signal will drop or the clock signal will not be reproduced, and as a result, the output level of the peak detection circuit 15 will decrease and an alarm signal will be output. That is, even if there is no input cutoff or input level drop, there is a drawback that an alarm signal is output when the mark rate is such that clock recovery is not possible.

The present invention provides an S/N ratio of an equalized output signal that causes erroneous identification.
The purpose of this invention is to make it possible to reduce mark rate dependence compared to the conventional example described above when identifying deterioration of the signal and detecting it as an input interruption.

[Means for solving problems]

The input disconnection detection method of the present invention uses a comparison circuit and a free
It is equipped with a flip-flop and a counting judgment circuit, which compares the received equalized output signal with a predetermined dark value in a comparison circuit, adds the comparison output signal to the data terminal of the flip-flop, and identifies the received equalized output signal. A clock signal with a phase approximately at the center between the points is applied to the clock terminal of the flip-flop, the output signal of the flip-flop is counted by a counting judgment circuit, and when the counted value is larger than a predetermined dark value, it is judged that the input is disconnected. It is.

[Effect]

If the phase is identified at approximately the center between the identification points of the received equalized output signal, the signal will be "0" in the normal state. In the event of an abnormality such as a drop in the input level, the S/N ratio of the equalized output signal deteriorates and the amount of code interference increases, so the possibility of the signal becoming "1" increases.

Therefore, if the comparison output signal with a predetermined dark value at a phase approximately at the center between the discrimination points is "1" for a predetermined number of times or more within a predetermined time, the S/N of the equalized output signal is is in a deteriorated state, and in that case an alarm signal is output as an input cutoff.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is an amplifier CAMP), 2 is an equalization circuit (EQL), 3 is an identification circuit (DEC), 4 is a clock recovery circuit (CLK),
5 is a comparison circuit, 6 is a flip-flop, 7 is a counting judgment circuit, and 8 is an output terminal for an alarm signal. The received signal is amplified by an amplifier 1 and applied to an equalization circuit 2, and the equalized output signal is sent to an identification circuit 3. It is added to the clock recovery circuit 4 and comparison circuit 5. In the optical signal transmission system, the received signal represents a signal converted by the above-mentioned photoelectric conversion circuit, and in the wireless transmission system or wired transmission system, it represents the output signal of the preamplifier.

The clock reproducing circuit 4 has a configuration for reproducing and outputting the clock signal CK for identification timing of the identification circuit 3, and a configuration for outputting a clock signal ck having a phase between the clock signals CK.

For example, a phase synchronization circuit (PLL) that performs phase synchronization with a clock signal CK for identification timing is provided, and a clock signal ck having a phase of 180° is output with respect to the clock signal CK for identification timing, and a flip-flop This configuration can be added to the clock terminal C of No. 6.

Further, the comparison circuit 5 includes, for example, a transistor Ql.

Q2, resistors R1 to R7, and capacitor C1, voltage vcc is divided by resistors R6 and R7 to form a reference voltage as a predetermined dark value, and the reference voltage is applied to transistor Q2.
In addition to the base of the transistor Q1, the equalized output signal is applied to the base of the transistor Q1, and when the equalized output signal is higher than the reference voltage, the collector potential of the transistor Q2 is high (
When the equalized output signal is lower than the reference voltage, the collector potential of transistor Q2 is low (“0”).
)Become.

The output signal of the comparison circuit 5 is applied to the data terminal of the flip-flop 6, and the comparison output signal is latched according to the timing of the clock signal ck...))
・Normally 6''! ・Geometric output signal ``Ikio'' 0 points between 1 points If the code amount interference is zero, it will be at zero level, so under normal input conditions , the output terminal Q of the flip-flop 6 is always "O". However, due to a drop in the input level, etc., the S/N of the equalized output signal deteriorates, and the code amount interference increases (as a result, the phase between the discrimination points The comparison output signal at is "1", and the output terminal Q of the flip-flop 6 is also "1".

The counting judgment circuit 7 counts "1"s at the output terminal Q of the flip-flop 6, and if the number exceeds a predetermined number within a predetermined time, it means that the S/N of the equalized output signal has deteriorated. It outputs an alarm signal from.

FIG. 2 is an explanatory diagram of the operation. Assuming that the equalized output signal waveform during normal conditions is shown by a solid line, and the equalized output signal waveform during abnormal conditions such as a drop in input level is shown by a dotted line, depending on the identification timing by the blackout signal CK, In the identification circuit 3, compared with the dark value, “
Since the clock signal ck is selected to have a phase between the discrimination points, the comparison output signal compared with the threshold value vth? in the comparator circuit 5 is the clock signal when normal. At the timing of ck, it becomes O''.

However, when the equalized output signal waveform reaches the state shown by the dotted line,
The code amount interference becomes large and becomes "1" even at the timing of the clock signal ck. That is, when the S/N of the equalized output signal deteriorates, the comparison output signal at the timing of the clock signal ck becomes 1''.

The flip-flop 6 latches the comparison output signal of the comparison circuit 5 at the timing of the clock signal ck.
In normal times, the output signal of the flip-flop 6 is "0", and in abnormal states such as a drop in the input level, it becomes "1". Therefore, if the "1" output signal of the flip-flop 6 is counted and the counted value within a predetermined time is greater than the dark value, it means that the S/N of the equalized output signal has deteriorated due to a drop in the input level, etc. In that case, an alarm signal is outputted from the output terminal 8 since erroneous identification is likely to occur.

S of the equalized output signal as described above before the input is completely cut off.
Since it is common for a deterioration of /N to occur, the above-described embodiment can detect a state in which erroneous identification occurs as an input disconnection. In addition, when the input is completely cut off,
Since the equalized output signal contains only noise components, timing extraction is no longer possible, and the clock signal ck disappears, so the counting determination circuit 7 cannot determine whether the input is interrupted. In this case, it is sufficient to use it together with the circuit that detects the peak of the reproduced clock signal shown in the conventional example described above. Complete input interruption is performed by detecting the peak of the clock signal, and the equalized output signal is It is also possible to use a configuration for detecting the S/N deterioration using the configuration according to the embodiment described above.

〔Effect of the invention〕

As described above, the present invention includes a comparison circuit 5 that compares an equalized output signal with a predetermined threshold value vth, a flip-flop 6, and a count determination circuit 7, and a comparison output signal of the comparison circuit 5 is converted into a flip-flop. In addition to the data terminal 6 of step 6, there is also a clock signal c whose phase is approximately at the center between the discrimination points of the equalized output signal.
k to the clock terminal C of the flip-flop 6, the output signal of the flip-flop 6 is counted by the counting judgment circuit 7, and when the counted value is larger than a predetermined dark value, the S/N of the equalized output signal is Since this is the case when the signal has deteriorated, an alarm signal indicating an input disconnection is outputted, and has the advantage of being less dependent on mark rate. Therefore, the present invention can be applied to a receiving apparatus using a wired transmission system, a wireless transmission system, or an optical signal transmission system, and can reliably detect a state that causes erroneous identification and determine that the input is disconnected.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of operation, and FIG. 3 is a block diagram of main parts of a conventional receiving apparatus. 1 is an amplifier (AMP), 2 is an equalization circuit (EQL), 3
is the identification circuit (DEC), and 4° is the clock recovery circuit (C
LK), 5 is a comparison circuit, 6 is a flip-flop, 7 is a counting judgment circuit, 8 is an alarm signal...):
The output terminal CK is a signal for identification timing, and ck is a clock signal for identifying S/N deterioration. First page

Claims (1)

[Claims] a comparison circuit that compares the received equalized output signal with a predetermined threshold;
The output signal of the comparison circuit is applied to the data terminal of the flip-flop, and the clock terminal of the flip-flop is provided with a phase signal approximately at the center between the discrimination points of the received equalized output signal. An input disconnection detection method characterized in that a clock signal is applied, the output signal of the flip-flop is counted in the counting judgment circuit, and an alarm signal is output when the counted value is larger than a predetermined threshold value.