JPS61100862A - Sequencing system of instruction - Google Patents

Abstract

PURPOSE:To enhance the parallelism between D0 loops made into vectors and other range and to increase the efficiency of execution by grasping its data dependency in wide range and making the optimum sequencing process. CONSTITUTION:Data analyzed in a source analyzing section 1 is given to an address allocating section 2, and there, memory area is allotted, and initial values are given to arrays and variables. A vector making section 3 converts D0 loops to vector instruction strings, and a sequencing processing section 4 grasps its data dependency in wide range, and makes the optimum sequencing of instruction to the data dependency by using a pipe line ID or synchronizing instruction. An intermediate text optimizing section 5 makes optimizing after making into vectors, and a register allotting section 6 performs processing such as allotting data to registers. An instruction generating section 7 converts an intermediate test to a machine language instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a compiler that creates object modules for vector computers, and in particular to a method for serializing instructions between a plurality of vectorized DoSils. It is.

[Prior art and problems]

In vector computers, increasing the speed of arithmetic units and the ability to supply data commensurate with the arithmetic units are important keys to improving execution efficiency. For this reason, recent vector computers are equipped with two-tree load/store pipelines that can operate in parallel to increase data supply capabilities. However, with multiple load/store pipelines operating in parallel, it has become necessary to synchronize (synonymous with serialization) memory access instructions. Such synchronization is difficult to achieve in hardware, and in systems including conventional vector computers, this is accomplished in software.

In vector computer hardware, the following methods are available for synchronizing memory access instructions.

(al Pipeline rD Specifies the pipeline in which vector memory access instructions operate. Synchronization can be achieved by running memory access instructions that require order guarantees in the same pipeline. .

(b) Synchronization instruction (PO3T/WA IT instruction) This is a method of guaranteeing the order relationship between memory access instructions using a synchronization instruction. Using this method, PO5
It is possible to synchronize the memory access instructions before the T instruction and the memory access instructions after the WAIT instruction.

In synchronization processing, it is necessary not only to guarantee the order of memory access instructions, but also to perform synchronization efficiently so that execution performance does not deteriorate. However, conventional compilers do not take into account data dependencies among a plurality of vectorized Do rules 1. Therefore, serialization processing is performed for each DO loop at the end of each DO loop, which is one of the causes of reduced execution efficiency in parallel processing calculations.

[Purpose of the invention]

The present invention is based on the above consideration, and comprises a plurality of D
The objective is to perform optimal instruction serialization processing between o-loops and improve execution performance.

[Means to achieve the purpose]

Therefore, in the instruction serialization method of the present invention, in a compiler that generates an object module executed on a vector computer, the intermediate text after vectorization is extensively data-dependent by referring to the subscripts appearing in the array. It is characterized by understanding the relationships and performing optimal instruction serialization processing on the data required for serialization.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a 5-part diagram outlining the compiler of the present invention.

This compiler is a P compiler that generates object modules to be executed on a system containing a vector machine. In FIG. 1, 1 is a source analysis section;
Reference numeral 2 indicates an address allocation section, 3 a vectorization section, 4 a serialization processing section, 5 an intermediate text optimization section, 6 a register allocation section, and 7 an instruction generation section. The source analysis unit 1 detects inconsistencies between arrays and variables defined in declaration statements and their handling in the procedure division of the source program, and checks whether undefined arrays and variables are defined or referenced. It is used to create blocks of source programs. The address allocation section 2 allocates memory areas for data and gives initial values to arrays and variables. The vectorizer 3 converts the DO loop into a vector instruction sequence. The serialization processing unit 4
It serializes instructions. The present invention relates to the serialization processing section 4. The intermediate text optimization unit 5 performs optimization after vectorization.

The register allocation section 6 performs processing such as allocating data to registers. The instruction generation unit 7 converts intermediate text into machine language instructions.

In summary, the present invention provides intermediate text after vectorization (
By applying vectorization technology (how subscripts that appear in an array behave), we can grasp a wide range of data dependencies and create data dependencies (data required for serialization).
This method performs optimal instruction serialization processing using pipeline IDs or synchronization instructions.

FIG. 2 is a diagram showing the flow of instruction serialization processing according to the present invention.

■ Take out a group of DO sills with a constant flow of control.

FIG. 3 shows an example of an O-loop group in which the flow of control is constant, and arrows A-B, CD, E-F, etc. indicate O-loop groups in which the flow of control is constant.

■ Understand the data dependencies within the DO loop group.

That is, the overlap is checked for subscripts of multiple dimensions. At this time, if there is a shift in the subscript information of the higher dimension, there is no overlap in the lower dimension. For example, suppose you have a program like the one below.

00 10 J=1. NDO101=1. N A, (1, J) = A (I, J-1) +S10
C0NTIN[IE This sentence is expanded as follows.

DO1Or=i, N 10 A(1,1)=A(1,0)+SDo 10
'l・1. N 10 A(1,2)=A(1,1)+S In this example, the inner DO small loops have different subscripts in the second dimension, so there is no overlap for A's memory access (non-serialization need). However, when considering the outer loop, there is an overlap between the store and the load of A, and it is necessary to perform serialization.

■ Check whether there is a dependency relationship between the Do small loop vector and the search. If Yes, perform the process ■, and then
In this case, process ■.

■ Perform serialization within multiple Do loops. , that is, serialization is performed based on the data dependence due to the outer rotation.

■ Perform serialization in Do loop units.

■ Check efficiency. That is, the density of pipeline IDs is checked. If the result is NG, process (■) is performed.

■ Perform serialization between DO sils. That is, serialization is performed based on data dependence relationships only in the innermost dimension (from top to bottom).

■ Check efficiency. If the result is NG, process (■) is performed.

■ Perform serialization within the DO loop. That is, serialization is performed based on the closed data dependence relationship within the D loop.

Next, the present invention will be explained with specific examples. Now, consider the o-loop group as shown below.

DO10J=2.100 DO10I・2,1.00 A(I, J)=A(I-1, J-1)+A (LJ-
1) 10 C0NTINUE In this example, there is no data dependency due to the rotation of the inner D○ loop. However, due to the rotation of the outer DO loop, ■−■
, ■−■ data dependence relationship occurs. In addition, ■ is A (
1, J), ■ is A (I-1, J-1), ■ is A (
1, J~1). In this case, a wide area (
If synchronization is performed (data dependence relationship of the outer Do loop), the same pipeline ID is required for memory accesses (1) and (2), resulting in a significant decrease in parallel processing efficiency. Therefore, it is better to synchronize locally (with the data dependencies of the inner Do loop). At this time, data dependencies in other ranges are synchronized by the PO3T/WAIT command.

An example where synchronization is optimal over a wide area will be described. Now, consider the O-loop group as shown below.

DO10J=1.100 Do10I=1,100 A(I,J)=B(1,J)+A(I,J-1)
10 C0NTINUE This example has the same structure as the previous example, but the data dependency due to the rotation of the outer DO loop is only ■-■, and it is synchronized in a wide range (outer Do small loop data dependency) Even if you do this, parallel processing efficiency is high. In addition, ■ is eight (1,
J), ■ indicates 8 (I, J-1). Therefore, it is optimal to perform synchronization over a wide area using pipeline IDs.

Another example where synchronization is optimal over a wide area will be described. Now, consider the O-loop group as shown below.

DO101・1,100 A(1)・C(1)+8(1-1) 10 C0NTINUE Do 20 I・1,100 B(1)・C(D book B(I+1) 20 C0NTINLIE In this example, the local If synchronization is performed within a range of 1 to 3, parallel processing efficiency will deteriorate because synchronization is achieved between DO sills using PO3T/WAIT instructions.However, if synchronization is performed based on data dependencies between DO sills, , only pipeline IDs are required for ■-■ and ■-■, and the parallel processing efficiency is high.Note that ■ is A(1), and ■
is B(I-1), ■ is B(1), ■ is B(1+1)
It shows.

Another example where synchronization is optimal within a local range will be described. Now, consider the o-loop group as shown below.

DO10r=1,100 A(1)=C(T) 10 C0NTINUE DO20J=1.50 B(J)=A(50) 20 C0NTINUE In this example, there is a vector and swash dependency between the DO loops, so Serialization is performed at the DO small loop level. The vector instruction sequence corresponding to the above DO loop group is as follows.

VL VRI, C (1:100) VST VRI A (1:100') VPT -T VL VR2, A (50) VST VR2, B (1:50) Note that VL is a vector load instruction, and VST is a vector load instruction. Store instruction, VPT is PO3T instruction, VWT is WAI
T instruction and VRX indicate vector registers, respectively.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, by comprehensively grasping data dependencies and performing optimum serialization processing, (squash instruction sequence) increases, and execution efficiency improves.

[Brief explanation of drawings]

Figure 1 is a diagram showing an overview of the compiler of the present invention, Figure 2 is a diagram showing the flow of instruction serialization processing of the present invention, and Figure 3 is a diagram showing an example of an O-loop group with a constant flow of control. It is. 1... Source analysis section, 2... Address allocation section, 3...
- Vectorization section, 4... Serialization processing section, 5... Intermediate text optimization section, 6... Register allocation section, 7...
・Instruction generation section.

Claims (1)

[Claims] A compiler that generates objects/modules that are executed on a vector computer uses the subscripts that appear in the array to grasp a wide range of data dependencies for the intermediate text after vectorization, and calculates the data required for serialization. An instruction serialization method characterized by performing optimal instruction serialization processing.