JPS6098623A - Method and apparatus for exposing semiconductor - Google Patents

Abstract

PURPOSE:To eliminate the need for a laser measuring machine, and to reduce cost by effectively illuminating an image forming pattern formed in a region adjacent to a circuit pattern on a mask by monochromatic light when a pattern on the mask is exposed onto a wafer. CONSTITUTION:Image forming patterns 120, 120' are formed to a bonding area while being adjoined to a circuit pattern 11 on a mask. When monochromatic light in wavelength lambda is projected vertically to the patterns 120, 120', reflected diffracted beams are condensed at the position of 1122 in a slitty shape. On the other hand, a scribing area 22 on a wafer is illuminated obliquely by beams (e), and scattered beams project through an imaging lens and an optical path 503 for the pattern 120, are reflected regularly by the pattern 120, and form an image at the position of 1122. Two crests are generated because an image from a chip is formed by scattered beams at a stepped section at the edge of an alignment pattern, thus obtaining an alignment signal. The wafer is moved finely on the basis of the signal, and the positions of the mask 1 and the wafer 2 can be conformed completely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method and apparatus for exposing and transferring a mask pattern onto the surface of a semiconductor.

[Background of the invention]

Conventionally, when exposing a pattern to a semiconductor, when exposing a mask and a conventional semiconductor pattern, the alignment between the mask and the wafer is j! There are two methods: one is to use an alignment optical system separate from the light imaging lens, and the other is to use an exposure imaging lens (TTL alignment method). The former measures the positions of several chips around the wafer 10 using an alignment optical system and a laser length measuring device, and assumes that other chips are aligned accurately. Assuming that the relative position between the optical axes of the system is accurately known, the chip exposure position on the wafer is calculated, the chip on the wafer is moved to this calculated position, and the chips are sequentially step-and-reheated. Expose and go.

Since this method only needs to measure the position of the chips at several locations, the time required for chip alignment is shorter than the time required for aligning the entire wafer, and while a high throughput can be obtained, it is possible to The accuracy of alignment with the mask becomes better, but this will become a major problem in the future as exposure patterns become increasingly finer and more precise alignment is required. On the other hand, there are several methods as the latter conventional method of performing an alignment image for each chip using an imaging lens for exposure. Figure 1 is an example. In the case of FIG. 1, exposure circuit pattern 1 on mask 1
1 and alignment patterns 12 and 12' are shifted in location on the mask surface (reticle surface) to prevent the alignment optical system and the exposure optical system from interfering with each other during alignment and exposure. Therefore, as shown in Figure 2, the mask and chip alignment is as shown in Figure 2 (tz).
, Ch) in the order of the chip alignment marks 22' (t
, - and 22) and mask alignment image 7 (and i
) is aligned twice, and the position of the wafer in the x and y directions is read using the tt laser length measuring device 6 (and 6'), and based on this data, the mask is adjusted as shown in Figure 2 (C). The circuit pattern image 11 is exposed onto the chip 21. Although this conventional TTL alignment method improves the relative alignment accuracy of the alignment optical system, it takes a long time to expose the entire wafer.

Furthermore, in any of the above methods, it is essential to use an expensive laser length measuring device, making the semiconductor exposure apparatus expensive.

[Purpose of the invention]

It is an object of the present invention to solve the above-mentioned conventional problems and to By aligning with high precision using an optical imaging lens and exposing immediately at the aligned position, the entire wafer can be exposed in a short period of time, and a laser length measuring device is not required, making it possible to reduce costs. An object of the present invention is to provide a semiconductor exposure method and a semiconductor exposure apparatus.

[Invention advisor]

In order to achieve the above object, in the present invention, when a pattern on a mask is exposed onto a wafer, an imageable pattern, which will be described in detail later, is provided in an area adjacent to a circuit pattern on the mask. To effectively illuminate a sexual pattern with monochromatic light. However, the monochromatic light in the present invention does not necessarily have to be physically pure monochromatic light, but rather light that can be considered monochromatic light in practical terms (hereinafter simply referred to as monochromatic light). The wavelength of the monochromatic light is generally advantageously different from the wavelength used for exposure.

It is illuminated with monochromatic light, and the light reflected or transmitted from the imageable pattern is diffracted to form a condensed image.

This focused image is used as an alignment pattern for mask alignment. On the other hand, since the alignment mark on the chip on the wafer is imaged by the exposure lens in the vicinity of the alignment pattern for mask alignment, which will be described later, accurate alignment must be performed from these two focused images and the alignment image of the chip. becomes possible.

The above content will be explained in more detail below. FIG. 6 shows the relationship between image formation at the j# source wavelength of the imaging lens 3 of the semiconductor exposure apparatus and image formation at the alignment wavelength. When the exposure wavelength light (assumed to be !1 line), that is, the dotted line light, is at position 2', point A of reticle 1 is clearly formed on the wafer. However, when the light of the alignment wavelength (temporarily e-ray) is illuminated obliquely for wafer alignment, when the wafer is at position 2', a wafer pattern is formed at position A' by the imaging lens 3. A and A' are shifted by ΔZ. Conventionally, to solve this problem, for example, the wafer position was changed from 2' to Δχ
It was necessary to align the pattern on the wafer by lowering it down and forming the pattern on the wafer near point A on the mask surface.

Δ2 and ΔZ are approximately ΔZ = N2, including the double height N of the lens.
There is a relationship of Δ2, Δ2 is about 200 μm, and ΔZ
becomes 20111 when N=10. Having to move the wafer up and down as much as 200 t1m each time it is exposed increases the time it takes to expose the entire surface of the wafer.

The present invention will be explained using FIG. 120 in the bonding area adjacent to the circuit pattern 11 on the mask, that is, in the scribe area or around the circuit pattern shown later.
．． An imaging pattern indicated by 12[1' is provided. This pattern consists of, for example, a hyperbolic group pattern shown in FIG. 6 or a pseudo-hyperbolic group pattern shown in FIG. These patterns are a single hyperbola or pseudo-hyperbola at a constant pitch in the X direction (direction connecting the two focal points of the hyperbola) y: knot 1 intervening stand (7) Finished = bp, the black part is Cr surface, the white part is Cr
It is a glass surface with no surface. When monochromatic light with a wavelength λ is perpendicularly incident on such a pattern, the reflected diffracted light is focused in a slit shape at an angle Ft of 1122, as shown in FIG.

On the other hand, in FIG. 4, an alignment pattern 22 (
t or 22') is obliquely illuminated with a - line and scattered 7'i: The light passes through the imaging lens and an image is formed at the position A' in Figure 3, resulting in the image formation in Figure 8. The light enters the optical pattern 120 through a curved optical path 503, and is imaged at a position 1122 without being specularly reflected or diffracted by the imaging pattern 120. That is, as shown in FIG. 8<b>, an imaging pattern is created such that 120 and 1122 are separated by ΔZ. In addition, Fig. 8 (C) is the 8th
It is a figure which looked at figure (h) from the direction in the page.

FIG. 9 shows an imaging pattern 12 formed near 1122.
Slit-shaped focused image of diffracted light from 0 (Fig. 9 (C)
) and a specularly reflected image (FIG. 9(b)) that is formed by obliquely illuminating the chip and passing through an imaging lens in an imaging pattern. The image from the chip is formed by scattered light at the edge step of the alignment pattern, resulting in two peaks, and the midpoint between these two peaks is the center of the pattern, as shown in Figure 9 @) If we calculate ΔX as shown in , this represents the pattern position shift dragon. Therefore, the mirror 53 shown in FIGS. 4 and 5,
An alignment signal can be obtained by focusing an image on the alignment detector shown in FIG. 4 using a magnifying lens 54 and detecting it. By slightly moving the wafer or mask based on this alignment signal, the mask and wafer can be perfectly aligned.

If exposure light (g-line) is emitted from the illumination system 4 immediately after this coincidence is confirmed, alignment and exposure can be performed without any delay, and the entire wafer can be exposed in a short time.

In order to achieve the above object based on the above-mentioned principle, the semiconductor exposure method according to the present invention is a method of exposing a circuit pattern provided on a mask onto the surface of a semiconductor as a workpiece. An image forming pattern is provided adjacent to the above circuit pattern, and the image of either the reflected diffraction light or the transmitted diffraction light obtained by illuminating the image forming pattern with monochromatic light is used as an alignment pattern. It is characterized by aligning the alignment mark on the workpiece with the image formed by the exposure lens.

fc5 A semiconductor exposure apparatus according to the present invention includes an exposure illumination light source that illuminates a circuit pattern provided on a mask;
Image the pattern on the surface of the semiconductor that is the workpiece.
In a semiconductor exposure apparatus equipped with an h-element lens, an image-forming alignment pattern is provided adjacent to the above-mentioned pattern, and means for illuminating the above-mentioned image-forming alignment pattern with monochromatic light is provided; alignment detection means is provided for detecting the relative positional relationship between a condensed image of either one of the reflected diffraction light beam and the transmitted diffraction light of the image-forming pattern illuminated by the image forming pattern and the image formed by the imaging lens. Additionally, the present invention is characterized in that means is provided for aligning the pattern on the mask with the surface of the semiconductor to be processed based on the information obtained by the alignment detecting means.

Next, examples of the present invention will be described.

FIG. 4 shows an embodiment of the present invention. mask (reticle)
1 is provided with a circuit pattern 11 as shown in FIG.
' is not provided.

This pattern consists of a hyperbolic group or a pseudo-hyperbolic group as shown in FIG. 6 or 7. The configuration of this hyperbola is the 8th
As shown in the figure (α), the protruding direction of the hyperbola is toward the circuit pattern side. The imaging patterns 120 and 120' are approximately 05 to 100, and are irradiated with a parallel beam from below from the l1t-Ne laser light source 51 (12
The illumination detection system of 0' is exactly the same as 120, so it is not shown in the figure. The Ire-Ne laser beam diffracted by the imaging pattern is focused in the form of a slit at the position shown at 1122 in FIG. On the other hand, a chip 21 to be exposed on the wafer 2 on the wafer stage 7 is slightly deviated from the correct wafer position and is positioned below the lens.

An alignment mark has already been formed in the scribe area of this chip, and if the relative positions of this mark and the imageable pattern of the mask match, then the pattern of the mask can be accurately overprinted on the chip. Therefore, the alignment pattern on the scribe area of the wafer is irradiated with He-Ne laser light diagonally from all directions, and the light scattered at the edges of the alignment pattern is passed through the imaging lens 3, and the image-forming pattern 120 on the mask is used to make a correct image. It is reflected and an image is formed on 1122. The pattern from the wafer formed on 1122 and the condensed image from the mask are magnified and imaged onto the detection surface (not shown) on the alignment detector by the mirror 53 and the magnifying imaging lens 54vC, and the two patterns are matched. Be careful. This detection involves a physical image pickup device, a combination of a scanning sensor and a photomultiplier, or the like. If a mismatch between the two patterns is detected, move the wafer stage or mask,
When a complete match occurs, VC exposure is immediately performed. Exposure light 41
Since it is completely separate from the alignment optical system and does not interfere with it, exposure ends immediately after alignment is completed.

FIG. 12 shows another embodiment of the invention. The same numbers as in FIG. 4 represent the same items. In FIG. 12, the imageable pattern in the area adjacent to the circuit pattern H of the mask 1 is placed in a vacant place within the imaging area inside the circuit pattern outline. The e-line illumination light 'm, 51'' from the mercury lamp passes through the half mirror 56, specularly reflects the imaging pattern consisting of the patterns shown in FIGS. 6 and 7, and passes through the imaging lens. The alignment pattern in the bonding area of the chip 22 is epi-illuminated.The reflected light returns along the same optical path 9 again, is specularly reflected again by the imaging pattern, and is imaged at the position 1122 (151il+).Mask position is a He-Ha laser light source or an Ar laser source, and includes an e-line light source 51
' The emitted monochromatic light 502 is made incident on the imaging pattern 120 via the mirror 55, and one of the diffracted lights from there is
Slit-like imaging at 122 can also be claimed. The pattern alignment detection and control from the mask and wafer is the same as in the previous embodiment.

FIG. 14 shows another embodiment of the present invention, and the same numbers as in FIG. 4 represent the same parts. The light emitted from the semiconductor laser 51'' irradiates the image forming pattern 120 on the mask from a slightly oblique direction. Since this light has a long wavelength, the -order diffraction angle is large, and -
The next time the diffraction source returns, and a slit-like image is formed at the position 1122. On the other hand, the light specularly reflected by the imageable pattern 120 can also be used for epi-illumination of alignment marks in the scribe area of the wafer. In addition to such epi-illumination, the alignment mark on the wafer is also obliquely illuminated from all sides by a semiconductor laser, and the scattered light generated at the step part of the alignment mark on the wafer or the reflected light from the epi-illumination is used to form an image, as in the previous embodiment. Specular reflection with sexual pattern, 11
22. The signal detection and alignment control of the mask and wafer alignment patterns thus obtained are the same as described above.

FIG. 16 shows a further different embodiment of the present invention.

The same numbers as in FIG. 4 represent the same items. The imaging pattern 121 provided adjacent to the circuit pattern portion 111C on the mask is composed of a one-dimensional Fresnel pattern shown in FIG. In this figure, the shaded area is a Cr surface, and the non-shaded area is a transparent glass surface without Cγ. In addition to the exposure light 41 of four exposure illumination systems, the mask is irradiated with monochromatic light 505 that illuminates the image forming pattern 121 on the mask from a slightly oblique direction.

- A slit-like image is formed at 1122 after moisture permeation through the 7-dimensional Lens pattern, and alignment is performed between the pattern and the alignment pattern from the wafer, as in the previous embodiment.

FIG. 18 shows a further different embodiment of the present invention, and the same number +4 represents the same thing as in FIG. 4. The alignment imaging pattern 122 on the mask has a structure as shown in FIG. 19(b)K. FIIJ macroscopically is a one-dimensional Fresnel pattern as shown in Figure 10, but microscopically it is Cτ
A grating is engraved on the part. Although FIG. 10 shows the C'r pattern on the symmetry axis of the one-dimensional Fresnel pattern, in this example, the pattern shown in FIG. 19 (h)
It becomes transparent. The alignment patterns 22 and 22' in the scribe area of the wafer soil are obliquely illuminated with highly directional light such as a Ha-He laser, and the scattered light passes through an imaging lens to form the imageable patterns 122 and 22' of the mask 1. 1
22', where it is diffracted by the grating 1202 shown in FIG. 19(c) and 1 shown in FIG. 19(α).
The image is formed at the position 122'. The other image forming pattern 122
is illuminated with monochromatic light 502 from below, and due to the effect of the -dimensional Fresnel pattern and grating, the 1st or 2nd order diffraction occurs.
The second-order diffracted light is condensed into a slit image at 1122' in FIG. 19. In this embodiment, unlike the above-mentioned embodiments, an alignment detection system is arranged above the mask. The method of detecting the alignment pattern from the mask and wafer is carried out in exactly the same manner as in the above embodiment.

In the above embodiments, the light incident on the image forming pattern is used both by reflecting the wafer pattern and the mask pattern (Figs. 4, 12, and 14), and by transmitting the light (Figs. 4, 12, and 14). 18), and as shown in FIG. 16, one is used for reflection and the other is used for transmission.

Although mask placement is precisely performed in a precisely machined mask chuck, sometimes the mask can tilt slightly, although this does not interfere with resolution. In this case, when using a transmissive type, it has almost no effect on the image formation position, but when using a reflective type, the image position shift ΔX with respect to the mask inclination Δθ becomes ΔX = Δθ・ΔZ, and ΔZ Since the angle is approximately 2Qmm, the allowable slope must be within 10 seconds in order to keep ΔX within 1μm. Therefore, if the source of the image of the superimposed pattern on the wafer is on the same side as the incident side on the mask,
It is desirable to illuminate the imageable pattern with monochromatic light.

In the above embodiment, the bonder (
It is desirable that the position corresponding to the alignment mark in the scanning area be illuminated during exposure. Therefore, although not shown in the drawings of the above embodiment, it is desirable to place a blade that limits the exposure area close to the top of the mask (
A, Figure 12.14.16). In addition, when the alignment detection system is located above the mask as shown in Fig. 18, an optical system is used in which a blade is provided inside the original illumination optical system and the blade is imaged on the mask using an imaging lens. good.

As detailed above, according to the semiconductor exposure method of the present invention, alignment can be performed with high precision using an imaging lens for exposure, and expensive equipment such as a laser length measuring device is not required. Equipment costs can be significantly reduced. Furthermore, exposure can be performed immediately at the aligned position, resulting in high speed and high efficiency.

Further, according to the exposure apparatus of the present invention, the above-described exposure method can be easily carried out and its effects can be fully exhibited.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are explanatory diagrams of the conventional alignment method,
FIG. 6 is an explanation of the imaging relationship between the exposure wavelength and different alignment lights, FIGS. 4 and 5 are explanatory diagrams of one embodiment of the method and apparatus of the present invention, and FIGS. 6 and 7 are the above-mentioned Plan view of imageable alignment pattern in Example, No. 8
The figure is an explanatory diagram of light collection and imaging by the image-forming alignment pattern, and FIG. 9 is an explanatory diagram of the alignment signal as well.
FIG. 10 is a plan view of the image-forming alignment pattern on the mask, FIG. 11 is an explanatory diagram of the condensing and imaging state of the image-forming alignment pattern, and FIGS. 12 and 13 are different implementations from the above. Examples of explanatory diagrams, FIGS. 14 and 15,
FIGS. 16 and 17, and FIGS. 18 and 19 are explanatory diagrams of different embodiments, respectively. Figure 19 Ch
) is a plan view of the imageable alignment pattern on the mask in the embodiment of FIG. 18. 1... Mask (reticle) 11... Circuit patterns 120, 120', 121.121', 122.1 on the mask
22'... Imageable alignment pattern on mask 2... Wafer 21... Chip 22.2 on wafer
2'... Scribe area 3... Imaging lens 4... Exposure illumination system 41...
Exposure illumination lights 51, 51', 51'... Light sources for illuminating the image-formable alignment pattern on the mask 521, 522.523.526... Oblique illumination light for wafer alignment 53.55... Mirror 54 ...image magnifying lens 56
... Half mirror 504 ... Detection light 5 ... Alignment detector 505 ... Imaging alignment pattern illumination light 7 ...
・Wafer stage l \ (; Agent patent attorney Takahashi -゛-fu' 3rd figure broom 4 figure 5 flash ra concave $ 8 figure q figure ΔZ brown / 2 jib 7th and 3rd closed page 74 $ 75 Kokugaku / Figure 6 No. 17 Written amendment to the country's procedures (voluntary) Indication of the case 1982 Patent Application No. 205817 57 Name of the invention Semiconductor exposure method and exposure device for each toy '1 No. 4 Qlf^ Patent Applicant?・1 (+I −5l'llll', l, (shi・1(1
☆、・Manufacturer's representative person's sleeve +I', o＞ Inside, ff line ``Drawings'' Figure 1 and page 1, page 1, line 5 to page 4, page 12 of the specification , amend the scope of claims column in separate dark blue text 9. 2. Delete "Ma" in the 4th negative line 20 of Specification 8, "When exposing a conventional semiconductor pattern." 3. In the fifth negative line of the specification, “method carried out using an alignment optical system” is changed to “method carried out using an alignment optical system (Of
fcLxtS alignment method)". 4. Page 6 of the specification, lines 17 and 18, “TTL
Alignment method: Alignment optical system" [TTL alignment method: 0ffaxis alignment method"
I am corrected. 5. On page 10, line 19 of the specification, "pressure irradiation image" is corrected to "specularly reflected image." 6 Replace “ΔX” on page 11, line 4 of the specification with “Δy” and “J
Press. l Correct "ΔX" on page 19, line 16 of the specification to "Δy". 8. Specification No. 22 negative 2nd line r 22.22'...
Scribe area Jor22, 22'... Chisogu alignment pattern'' is corrected. 9 Figures 3 and 9 of the drawings are corrected as shown in the attached sheet. Claim 1: In a method of exposing a circuit pattern provided on a mask onto the surface of a semiconductor as a workpiece, an imageable pattern is provided in contact with the circuit pattern Kli on the mask, and the imageable pattern is The feature is that the image of either the reflected diffraction light or the transmitted diffraction light obtained by moonlighting with monochromatic light is used as an alignment pattern to align the alignment mark on the workpiece with the image formed by the exposure lens. An exposure method for semiconductors. 2. Claim 1, characterized in that the image forming pattern is a one-dimensional Fresnel pattern.
The semiconductor exposure method described in Section 1. 3. The method according to claim 1, wherein the monochromatic light is illuminated from the same side as the side where the image of the overlapping pattern on the semiconductor to be processed is incident on the mask. U-source method for semiconductors. 4. The image of the alignment mark formed by the 11-element lens and the image of the imaging pattern formed by the monochromatic light are effectively formed on the same imaging plane. The method for manufacturing a semiconductor according to Scope 1. 5. The imaging pattern described above is either a hyperbolic group pattern in which a hyperbola is translated in parallel at a constant pitch in the horizontal axis direction, or a pseudo hyperbolic group pattern in which the above hyperbolic group pattern is sampled with unit pixels. The method for exposing a semiconductor according to claim 1, characterized in that one of the above methods is used. 6. In a semiconductor exposure apparatus equipped with an exposure illumination light source that illuminates a circuit pattern provided on a mask and an exposure lens that images the pattern on the surface of a semiconductor that is a workpiece, At least an imageable alignment pattern is provided, and a means for illuminating the imageable alignment pattern with monochromatic light is provided, and reflected and transmitted diffraction light of the imageable pattern illuminated with the monochromatic light is provided. Alignment detection means for detecting the relative positional relationship between one of the condensed images and the image formed by the imaging lens is provided, and a pattern on the mask is detected based on the information obtained by the alignment detection means. A semiconductor exposure apparatus characterized by being provided with means for positioning the surface of a semiconductor as a workpiece. Z. Claim 6, wherein the image-forming alignment pattern is a one-dimensional Fresnel pattern.
The semiconductor exposure apparatus described in 2. 86 The above-mentioned image-forming alignment pattern is one of a hyperbola group pattern in which a hyperbola is translated in parallel at a constant pitch in the horizontal axis direction thereof, and a pseudo-hyperbola group pattern in which the above-mentioned hyperbola Uf pattern is sampled with unit pixels. 7. A semiconductor exposure apparatus according to claim 6, characterized in that one of the above is used. 9 The illumination device using monochromatic light illuminates the entire imageable alignment pattern 1ffl from the same side as the side where the image of the overlapping pattern on the semiconductor to be processed is incident on the mask.
Claim 6 is characterized in that
1. The semiconductor h-light device described in 2. 0 Claims characterized in that the image of the alignment mark formed by the exposure lens and the image of the image forming pattern formed by the monochromatic light are effectively formed on the same image forming plane. 7. The semiconductor a-optical device according to item 6. Dezu diagram

Claims (1)

[Claims] 1. In a method of exposing a circuit pattern provided on a mask onto the surface of a semiconductor as a workpiece, an imageable pattern is provided adjacent to the circuit pattern on the mask, and the imageable pattern is The pattern is illuminated with monochromatic light, and an image of either the reflected diffraction light or the transmitted diffraction light obtained is used as an alignment pattern, and alignment is performed with the image of the alignment mark on the workpiece formed by the exposure lens. An i-element method for semiconductors. 2. Claim 1, wherein the image-forming alignment pattern is a one-dimensional Fresnel pattern.
The i-element method for semiconductors described in Section 1. 3. The illumination with the monochromatic light is performed from the same side as the side where the image of the overlapping pattern on the semiconductor to be processed is incident on the mask, as set forth in claim 1. semiconductor exposure method. 4. Claim 1, characterized in that the image of the alignment mark formed by the lightless lens and the image of the imaging pattern formed by the monochromatic light are effectively formed on the same imaging plane. The semiconductor exposure method described in Section 1. 5. The imaging pattern described above is either a hyperbolic group pattern in which a hyperbola is translated in parallel at a constant pitch in the horizontal axis direction, or a pseudo hyperbolic group pattern in which the above hyperbolic group pattern is sampled with unit pixels. 2. The semiconductor exposure method according to claim 1, wherein one of the semiconductors is exposed. 6. Illuminating the circuit pattern provided on the mask
! ! In a semiconductor 11-element device equipped with an illumination light source and an exposure lens that images the pattern on the surface of a semiconductor that is a workpiece, an imageable alignment pattern is provided adjacent to the pattern, and the image forming alignment pattern is provided adjacent to the pattern. means for illuminating the imageable alignment pattern with completely monochromatic light, and a condensed image of either the reflected diffraction light or the transmitted diffraction light of the imageable alignment pattern illuminated with the monochromatic light and the above-mentioned focused image. An alignment detection means for detecting the relative positional relationship with the image formed by the image lens is provided, and the pattern on the mask is aligned with the surface of the semiconductor to be processed based on the information obtained by the alignment detection means. A semiconductor exposure apparatus characterized by comprising means. Z. Claim 6, wherein the image-forming alignment pattern is a one-dimensional Fresnel pattern.
The semiconductor exposure apparatus described in 2. 8. The above-mentioned image-forming alignment turn, a hyperbola group pattern in which a hyperbola is translated in parallel at a constant pitch in the horizontal axis direction, and a pseudo-hyperbola group pattern in which the above-mentioned hyperbola group pattern is sampled with a unit pixel. 7. The semiconductor snoring device according to claim 6, wherein one of the two is one. 9. The illumination device using monochromatic light illuminates the image-forming alignment pattern from the same side as the side where the exposure illumination light that illuminates the circuit pattern is incident on the mask. The semiconductor exposure apparatus according to item 6. 10 Claims characterized in that the image of the alignment mark formed by the exposure lens and the image of the image forming pattern formed by the monochromatic light are effectively formed on the same image forming plane. The semiconductor exposure apparatus according to item 6.