JPS609306B2 - data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to communication between computer systems, and particularly to a data transfer device that controls data transfer between a transmission subchannel and a reception subchannel operating on a data transfer device.

BACKGROUND OF THE INVENTION Conventionally, an inter-channel coupling device (hereinafter referred to as CTCA) as shown in FIG. 1 has been used as a coupling means between computer systems. Main storage unit (hereinafter referred to as MSU) 1,C
PU2 and channel 3 constitute respective subsystems Z, and CTCA4 constitutes a communication path that connects the subsystems. The inter-subsystem communication method using CTCA has the following problems. '1l 1
Each data transfer requires several SIO commands and interrupts to the ZCPU, resulting in a large CPU overhead.

■ Since CTCA is connected to the channel "CTC
The A-channel data transfer method has no choice but to rely on the conventional relatively low-speed IOC-channel interface, and there is a limit to high-speed data transfer.

The invention that solves the first problem mentioned above was developed by the present applicant in 1933.
Buddha Hand Patent Application No. 146164 "Communication system between computer systems"
No. 97).

In the invention, once the transmission subchannel and the reception subchannel are put into operation, they start data transfer operation, and unless stopped by a stop command etc., they continue to operate, and the 3 transmission data for the transmission subchannel is stored in the main memory. The device is queued on the device, and even after the transfer of the queued data is completed, it remains in an operating state and waits for the next transmission data to be queued.

If transmission data queuing is performed continuously, data transfer to other systems is also performed continuously,
Therefore, the number of interrupts required by the activation command is kept to a minimum.
It is an object of the present invention to provide a data transfer device that solves the second problem and realizes a data transfer method that is high speed, highly reliable, and has fewer restrictions such as distance in communication between subsystems. be.

This purpose is to provide a data transfer device that is connected to each of two subsystems of a data processing system and that is interconnected by a communication path to control data transfer, and that the data transfer control is performed by sending and receiving commands. The command 'includes at least a data command indicating data transfer, is specified by a buffer number, is used in the order of the buffer number, and is a plurality of buffers for storing transmission data; a first counter indicating the buffer number of the oldest buffer in use, identified by a register number and used in the order of the register number to store commands to be sent;
a plurality of registers; a second counter indicating the register number of the oldest register currently in use; If the command is a data command, a means for reading data in a specific buffer according to the buffer number and length stored in the register, adding the data command, and sending it to the communication channel; A means for receiving a command, data and a sequence number added thereto, a means for transmitting a number next to the latest received sequence number onto a communication channel, a means for receiving the number, and when the number is received. increments the second counter until it becomes equal to the number, and in the process of yielding, increments the first counter by a number equal to the number of data commands stored in the register pointed to by the second counter. This is achieved by a data transfer device characterized in that the data transfer device divides data to be transferred between subsystems into blocks of a fixed length and transfers the data by dividing the data into blocks of a certain length. Appropriate error control is performed, and the reception of the flock is confirmed through communication between the transmitting and receiving devices.Flocks that were not received normally are automatically retransmitted, and on the receiving side, the blocks are combined and retransmitted. In a data transfer device that configures one piece of data, management of data and command buffers for transmission and retransmission can be performed efficiently by using decimal counts.

Next, the present invention will be explained by examples.

FIG. 2 is a diagram showing the configuration of the system, and an SCC (subsystem communication channel) 5 is the data transfer device of the present invention.

Each SCC5 is one subsystem CPU2, MSUI
and interface with other subsystems at the same time
It also has an interface with C5, and its purpose is to transfer data from the MSUI of one subsystem to the MSUI of the other subsystem.

Figure 3 shows that the transmission subchannel 6 of one SCC is connected to the other SC.
FIG. 3 is a conceptual diagram in which unidirectional data transfer is performed by logically coupling with the reception subchannel 7 of C through a communication path.

Data is fetched from the main memory by the transmission subchannel 6, passed to the receiving subchannel 7 of the other party, and stored in the main memory on the side of the receiving subchannel. The commands sent and received between both subchannels to control starting, stopping, and data transfer of both subchannels are described below as LT.
It is called P command. A subchannel is a logical mechanism that consistently controls a single input/output operation from start to end, and is mainly composed of control tables and the like necessary for a single input/output operation. Figure 4 shows two pairs of transmitting subchannels and receiving subchannels in opposite directions to enable bidirectional data transfer between subsystems, and a two-way transmission control circuit (hereinafter referred to as In T
This is called P control.

) 10, 1 is a conceptual diagram showing what is done by 1. The TP control 10 transmits the LTP command requested to be sent to the transmission subchannel 6 or the reception subchannel 8 to the other party's TP.
control 1 1, and the partner TP control 1 1 operates to pass the command to the receiving subchannel 7 or the transmitting subchannel, respectively. Communication between both TP controls is performed using commands, and these commands are hereinafter collectively referred to as TP commands.

Figure 5 shows the queue element on the main memory of subsystem 2 and its control program.

This is an illustration of the tsuku. The details are shown in the aforementioned patent application No. 146164, but a summary will be given below. The BCB 12 of the subsystem is used as a communication area between the transmission subchannel 6 and the CPU, and the BCB of the subsystem 2
B13 is used as a communication hub between the reception subchannel 7 and the CPU.

BAT14 and BAT15 are tables that hold information for addressing queue elements (hereinafter referred to as QE) 16, 17, 18, 19, etc.

BCB12 and BCB13 manage the location and queuing status of BAT14 and I5. In this case, the queue elements (QE) are transmitted and received data stored in the main memory, and are indicated by numerals 16 to 19. Transmit subchannel 6 is in operation state E in BCB1 2
Compare NQP and DEQP, and if they do not match, it is assumed that transmission data (QE) exists, and if reception subchannel 7 is receivable, transmit the QE data specified by the BAT entry pointed to by DEQP, and end. Then update DEQP. Transmission subchannel 6 repeats this operation,
While DEQP and ENQP match, it is checked at regular intervals whether QE exists. The receiving subchannel is E
When the entry in BAT15 specified in the NQP indicates that the buffer for the receive queue element is ready, it is ready to receive, the data from the transmit subchannel is written to that area, and the entire QE Update ENQP when data is written. The receiving subchannel 7 reports to the transmitting subchannel 6 that the reception of the QE is completed, and at the same time reports whether the next QE can be received.

If it is reported that reception is not possible, a report that reception is possible is made when reception becomes possible. In FIG. 5, THP of BCB12 indicates the start address of BAT14, and TL indicates the length of BAT14. B.C.B.
The same applies to the case of 13. On the sending side, BCB1
ENQP 2 points to an entry in BAT14 indicating the address of the QE to which the CPU should write transmission data next, and when writing transmission data, the CPU updates ENQP to point to the next entry. BCB13 on the receiving side
DEQP points to the entry in BAT15 that indicates the address of the QE to which received data to be processed by the CPU is written.After processing this QE, the CPU writes DEQP
Update. The LTP commands used for communication between the transmit and receive subchannels are state control commands (S
TO and STI), data command (SD), reception completion command (RC), and reception ready command (RS) are defined. ST○, SD as shown in Figure 6
The command originates from the transmit subchannel, ST1, R
The C,RS command originates from the receive subchannel.
The state control commands STO and STI are used as control commands for starting and stopping subchannels, and whether the STO and STI commands are start, stop, positive response, or negative response is indicated by a flag in the command code section. The STO and STI commands have the same function except for different directions. Flag bits are also assigned to the command code portions of the SD and RC commands, and the meanings indicated by each flag are shown in parentheses after the command name in the following explanation. The control of subchannel activation, data transfer, and termination performed using these commands will be explained.
Figure 7 shows the process of transitioning to the operating state (W state) by a state control command when both the transmitting subchannel and the receiving subchannel are in the usable state Z state (A state). When the sending subchannel is given a SEND command as a start command from the CPU, the sending subchannel Z issues an ST○ (start) command and waits for a response from the receiving subchannel.

When the receiving subchannel receives an STO (startup) command in the A state, it returns an ST1 (negative response) command.
In the case of a negative response, the SNB field of the STI command is valid and the SNB information indicates that the receiving subchannel is
The status is reported to the transmit subchannel. Further, the reception subchannel generates an attention interrupt cause and enters an interrupt pending state (1 state). This requests an interrupt to the receiving side PU and sends a RECE request to the receiving subchannel.
This is to request that an IVE directive be issued. C.P.
When the interrupt is accepted by U, the receiving subchannel returns to the A state. On the other hand, the transmission subchannel that has received the ST1 (negative response) command ends with condition code CC=1 indicating the execution result of the start command, and the state remains in the A state. The CPU sees that CC=1 and knows that startup has not been completed. The receiving side CPU that received the attention interrupt prepares a QE buffer for reception, issues a start command to the reception subchannel, and issues a RECEIVE command. The receive subchannel issues an STI (initiate) command.

When the transmission subchannel receives an ST1 (activation) command in state A, it generates an attention interrupt cause, enters the interrupt pending state, and simultaneously returns an ST○ (acknowledgement) command as a response.

When the receiving subchannel receives the ST○ (acknowledgement) command, it terminates the command with CC=○ and changes the state to the W state.

The CPU regards CC=0 as success in startup. A SEND command is issued again as a start command to the transmitting side CP peak transmission subchannel that received the attention interruption. The transmitting subchannel issues the ST○ (activation) command again and waits for a response. When a receiving subchannel in the W state receives an ST○ (activation) command, it returns an ST1 (acknowledgement) command. No interrupt is performed at this time. The transmitting subchannel that has received the ST1 (acknowledgement) command ends the command with CC=○ and changes its state to W state. The above is the startup sequence communicated between the sending subchannel and the receiving subchannel. Both subchannels send a startup command from the CPU to the other party of the designated startup command, and when this command is received, the receiving subchannel The channel returns an acknowledgement only when in the W state, the transmitting subchannel returns an acknowledgement in the A state, and both subchannels enter the W state only when they receive an acknowledgement, thereby changing the W state of both subchannels. It can be seen that synchronization can be obtained. Only in the W state, both subchannels transmit and receive data as described below. Next, the transmitting subchannel and receiving subchannel are in the operating state (W
This section describes the operation when the device is in the state). When the transmit subchannel becomes active, it checks whether there is data (queue element) to be transmitted.

This is the BCB EN associated with the transmit subchannel.
QP and DEQP are compared, and if they do not match, it is assumed that transmission data exists (see Figure 5). As shown in FIG. 8, one queue element is divided into blocks of a fixed length, transmitted over a communication path, and combined on the receiving side main memory.

The SD command consists of a command part and a data part as shown in FIG. 6, and each block is transferred from the transmission subchannel to the reception subchannel as the data part of the SD command. Figure 9 shows the sequential transfer of three QEs,
The EI is divided into four blocks, and the four SD commands are sequentially transmitted.

The SD command has a 3-bit flag, which is set to SD (
F, L, 1). In this), the F bit=1 indicates the first block, and the L bit=1 indicates the last block. Therefore, when both the F bit and the L bit are "0", this indicates that the block in the data portion of this SD command is an intermediate block. 1 bit = 1 indicates that an interrupt should be generated to the CPU on the reception subchannel when a command is received.

This interrupt is used for the purpose of notifying the received data to be immediately processed by the CPU. The receiving subchannel sequentially stores the received data in the queue element indicated by the address of BAT15 pointed to by ENQP in FIG.
D (1, 1, 0), etc.), the block of the data portion is stored in the main memory, and then ENQP is updated.

Next, it is checked whether the contents of the BAT15 entry pointed to by the updated ENQP are valid or not, and it is determined whether the next data to be sent can be received. If it can be received, RC(0
) command to the transmit subchannel (QE2 in Figure 9).
and after receiving QE3), and if reception is not possible, sends an RC(1) command (after receiving QEI in the example of FIG. 9). When the transmission subchannel receives the RC(0) command, if there is data to be transmitted next, it transmits the next data. If RC(1
) command is received, the transmission is delayed until the next RS command is received. The reception subchannel is RC(1
) After sending the command, periodically check the BCB13 etc. in Figure 5, wait for the CPU to prepare the next receive queue element buffer, and when it becomes possible to receive, send the RS command. . The transmission subchannel is RC(0
) or RC(1) command is received, D of BCB12
Update EQP. With the data transfer method described above,
The transmit subchannel and the receive subchannel can continuously transfer queue elements in the active state.
Next, the stopping operation will be explained with reference to FIG.

FIG. 10 shows a stop sequence when an event requiring CPU intervention is detected for some reason in a transmission subchannel in an operating state and an interrupt is generated.
When the transmitting subchannel detects the cause of an interrupt, it transmits an ST0 (stop) command to the receiving subchannel, and sets its own state to an interrupt pending state.

On the other hand, when the receiving subchannel receives this command, it enters an interrupt pending state. The status of the cause of the interrupt, etc. is indicated by the SNB field of the STO command. Each subchannel is own C
When an interrupt is accepted by the PU, it becomes usable.

If an interrupt cause occurs on the receiving subchannel side, an STI command is issued from the receiving subchannel and a similar stop sequence is performed. FIG. 11 is a block diagram inside the SCC in the embodiment of the present invention.

DBE20 and DB021' are 32-bit registers, and are used as a buffer during data transfer between the main storage device and local 0 storage (B) 24, or as a work register for address calculation, etc. The ALU 22 is a logic circuit having functions of addition/subtraction and selection of the DBE 20 and DB021, and the WR 23 is a buffer register for temporarily holding input data of the LS 24.

LS24 is a local memory for holding a buffer for transmitting and receiving data and various control information used by the transmitting/receiving subchannel. O LSA25 leads B24/
This is an address register for writing.

The transmission subchannel 6/reception subchannel 8 holds control information regarding activation, termination, and data transfer, and controls the entire sequence. The HSI control 26 manages the interface between the CPU and main memory and the SCC, executes CPU instructions, handles interrupts to the CPU, and controls the main memory and the LS24.
data transfer between the CPUs, buffer control on the main memory, communication with the CPU program using control blocks, etc.
The TP control 27 sends LTP commands requested to the sending/receiving subchannels 6 and 8 to the other system TP control, and transmits/receiving LTP commands received from the other system TP control to the sending/receiving subchannel 6.
, 8.

The flock transmission control 28 generates a CRC check code for the TP command, adds block delimiter bits, and transmits the TP command.
It has the function of sending commands to the other party's SCC. The block reception control 29 recognizes the block delimiter bit, receives the TP command sent from the partner SCC, and performs error detection due to the CRC check code.

FIG. 12 shows the state of the transmission buffer and reception buffer allocated to the inside, and the state of the management counter.

In the embodiment, the buffers for both transmission and reception are composed of four blocks of equal length. The transmission buffer 3 is managed by the transmission subchannel 6, and the write counter WTN3
A 1-byte data block is loaded from the main memory into the block area indicated by 1.

Every time one block is completed, the WTN 31 counts up by 11.

This indicates that the data in the block area indicated by the read counter RDN32 is to be sent to the partner subchannel next.

This counter is incremented by 1 after the transmission subchannel 6 makes a transmission request to the TP control 27 and is accepted. The data confirmation counter ACN33 is incremented by 11 when the block in the transmission buffer 30 is transmitted to the other party's communication channel and its reception is confirmed. Each counter returns to 0 after the counter value 7. The reason why each counter counts up to 7 even though there are 4 block areas is as follows. Each counter consists of 3 bits, the lower 2 bits indicate the area of the block, and the higher 1 bit is used as control information in counter comparison. For example, WTN3 1 is ACN
The lower 2 bits of WTN31 and ACN33 are set to the same count value as 33 or earlier, but after WTN31 instructs block 3, the lower 2 bits of WTN31 and ACN33 are If they match, and the upper 1 bit also matches, W
Load the data into the block pointed to by TN31, and
3 1 may be updated, but "If the upper 1 bit does not match, all blocks in the transmitting buffer 30 are in use, so loading blocks and updating the WTN 31 cannot be performed. The receiving buffer 35 is The block sent from the other transmission subchannel is written into the block area indicated by the write counter WTN36, and the count is increased by 11 at that time.The block indicated by the read counter RDN37 is then transferred to the main memory. When stored in main memory, it is counted up by 11. When each counter reaches 7, it returns to 0. How to use the upper 1 bit of WTN36 and RDN37 , as above, WT
N36 is controlled so as not to exceed RDN37. FIG. 13 shows TP commands for communicating between the TP control 27 and the TP control of the partner SCC.

Bits 0-8 of the first line of the TP command form the command code. There are five types of TP commands: SABM, UA, old R, RNR, and 1.

These commands are appended with a CRC check code as the final word, and the command code and data portion are checked for transmission errors. Bit B is a block delimiter bit and is used to identify the first and last words of the TP command, as described below. FIG. 14 shows an example of the command code of the TP command shown in FIG. 13. RR, RNR 1 command N(R
) is the reception sequence number, which is the sequence number of the LTP command that can be received next ~ N(S) of 1 command is the transmission sequence number, which indicates the sequence number of the LTP command that is being sent. RR, RNR
Bits 4 and 8 of the command are used for retransmission checking. These functions will be described later. Other bits are used to identify the type of each command. The SABM command is a command to start communication between TP controls, and the UA
The command is a response command to the SABM command.

After sending the SABM command, if a UA command is received, TP control performs communication using the 1, RR, and RNR commands. 1 command is used to transmit an LTP command, and the LTP command shown in FIG. 6 is placed below the first word bit 9 of the 1 command and is transmitted and received.

RR and RNR commands are used for reception reports, busy reports, and retransmission control. FIG. 15 shows the command register and control counter located on the mountain 24 and used by the TP control 27.

Command registers 40 are prepared for four commands, and each register has command, ID, and length fields.
The command field contains bits 9 to 3 of the LTP command.
1 is set, and the ID and length fields are valid only when the command field is a $D command. RQCN4 1, VS as a control counter for the command register 40
CN42 and CACN43 are available. These counters consist of 3 bits, the lower 2 bits are used to instruct one of the command registers 40, and the upper 1 bit is used in the same way as the counter for controlling the transmission buffer 30 in FIG. and is used as a control for comparison. RQCN14 points to the command register to be written next, VSCN42 points to the command register to be sent next, and CACN43 points to the command register to which reception is to be confirmed next.

In the initial state, it is set to zero except for the above control counters.
Another counter VRCN44 is the next LTP to be received.
Indicates the command reception sequence number.

Z Next, the transfer operation of the LTP command will be explained. The transmission subchannel 6 and the reception subchannel 8 request the TP control 27 when transmitting an LTP command. TP control compares CACN43 and RQCN41, and if the lower 2 bits of both are not equal or all 3Z bits are equal, the transfer request is accepted, an LTP command is set in the command register indicated by RQCN41, and RQCN41 is set.
N4 Count up 1 by 11. At the same time, if LT
If the P command is SD, RDN3 is used as the address on the transmission buffer of the data block sent with the SD command.
Set the value of 2 to m and the effective data length to the length field. When RQCN41 and VSCN42 are not equal, it is determined that there is a command to be sent, and TP control 2
7 takes out the LTP command from the register indicated by VSCN 42 and checks whether it is an SD command.

If it is not an SD command, the first word of one command is formed in the format shown in FIG. 13 e-1. V as N(S) of 1 command
The value of VRCN44 is used as the value of SCN43 and N(R).

TP control 27 passes the first word to block transmission control 28;
A block transmission control 28 adds a check code CRC and a block delimiter bit, and transmits it to the block reception control 29 of the other party's SCC.

If it is an SD command, 1 in the format of Figure 13 e-2
Form the first word of the command and ask the block send control 28, passing at the same time the ID and length fields read from the command register. Details of the block transmission control 28 are shown in FIG. The flock transmission control 28 always sets the B bit 54, which is a block delimiter bit, to "1" and sends it to the other party S.
Sending to CC. SD passed by TP control 27
The command is set in register SA50. SA50
The contents of SB51 and B54 are transferred to register SB51, and at the same time, 8 bits 54 are set to "0", and the contents of SB51 and B54 are sent out. At the same time, the block transmission control 28 reads one word of data from the block designated by the block ID of the transmission buffer on the LS 24 and sets SA50'. Next, S
The contents of A50 are moved to SB51 and sent.

During this time, the next data word from 24 is set to SA501. In this way, the number of data words of the designated block length is read out from the LS 24 and sent out. During this time B bit 5
4 is initially set to "0"), "0" is sent out.
In parallel with the above operations, the contents set in SB51 are input to the check code generation circuit SCG53, and are operated on together with the contents of register SC52, and the result is set in SC52. The SC 52 is put into an initial state when a transmission request is received from the TP control 27. With the above operation, the last data is set in SB51 and sent out, and at the same time it is input to SCG53 to perform the final check code generation operation, and the SC
When the result is set in SC52, the contents of SC52 are sent as a check code.At the same time, the B bit 54 is set to '4.
1" and is sent to indicate that it is the last transfer word. In the case of sending a command other than the SD command, the SB
After sending the command from SC51, SC52 is sent as the second line.
The content of is sent and the transfer ends. Next, I will talk about the receiving operation.

FIG. 17 shows details of the block reception control 29. The block reception control 29 always sends the received word to the register RB61.
It sets it to B64 and monitors until the B bit turns off. The first word with B bit 64 turned off is stored in register R.
A601 is retained. At the same time, RC62 is reset. The contents of RB61 are held in RA6, and are also input to check code generator RCG63, and the result is held in register RC62. Receive the next word to RB61,
If the B bit has returned to “1” at this time, the RC62
The contents of RB61 are compared with the contents of RB61 by a comparison circuit 65, and if they match, the register RA6 is made valid and passed to the TP control 27. If they do not match, the contents of RA 60 are discarded and the reception operation ends. When the second word is received, if the B bit is still “0”, the command of the first word is 1 command, the LTP command field is an SD command, and therefore the second word and subsequent words are considered to be the data part. .

After the second word, the contents of RB61 are transferred to mountain 24 and written to the block area indicated by WTN36 of the reception buffer.
At the same time, the RCG 63 performs a check calculation. When the first word with the B bit 64 set to "1" is received, that word is not transferred to the B bit 64 but is compared with the RC 62 in the comparator circuit 65. If they match, the contents of register RA60 are controlled by TP control 27.
and B bit 64 is set to “0” to receive the next block.
”.The TP control 27 decodes bits 0 to 8 of the command passed from the block reception control 29, and if it is one command, it decodes bits 1 to 3 of N( S) and counter VRCN44
Compare. If they match, the VRCN 44 is counted up by 11. If there is a mismatch, the VRCN 44 is not updated. Next, N(R) in bits 5 to 7 of the command and VACN43 are compared, and if they do not match, the CAC
It is assumed that the command indicated by N has been received, and VACN43
Reads the command register 40 indicated by S.
If it is a D command, the counter AC of the transmission buffer 30
By incrementing N33 by 11, the block pointed to by ACN33 can be used for new transmission data.

regardless of the type of command read. CACN43
11 and empties the register pointed to by CACN43. Normally, through the above processing, the received N(R) and C
The ACNs 43 become equal, but if they still do not match, repeat the above steps until they match. However, CACN43 is VSCN4
It must not be updated beyond a value of 2. 3. If ACN43 and VSCN42 are equal from the beginning or as a result of the above processing, and N(R) and CACN43 still do not match, synchronization of the transmission and reception confirmation operation with the other party's SCC may be caused by some kind of failure. Since this is an impossible state, this is notified to the CPU and appropriate recovery processing must be performed, but a description of the recovery processing will be omitted.

Transmission sequence number N(S) and V of one received command
If the result of the comparison by the RCN 44 is that they do not match, the received command is ignored and no further processing is performed and the command is discarded. If they match, then the LTP command is determined, and the LTP command is passed to the reception subchannel 8 if it is an STO and SD command, and to the transmission subchannel 6 if it is an ST1, RC, or RS command. If it is an SD command, the counter WTN 36 of the reception buffer 35 is incremented by 1. The functions of each of the above LTP commands are as described above, but in the case of the SD command, the reception subchannel 8 transfers the data of the block pointed to by the counter RDN 37 of the reception buffer 35 on the LS 24 to the queue element area of the main storage device. , and then increment RDN37 to 11. When the TP control 27 receives the RR and RNR commands, it only checks the receiving sequence number of the same aircraft using bits 5 and 6 of N(R).

When the TP control 27 receives a command, it then reports the reception to the other party's SCC.

This report should be sent to the command register 40.
If there is a command (if RQCN41 and VSCN42 do not match) and an RNR command has not been received from the other SCC as described later, execute one command to send the LTP command that is the register pointed to by VSCN42. If there is no LTP command to be sent (if RQCN41 and VSCN42 are equal), "RR
Or RNR command day Koyoru. In this case, if there is no free space in the reception buffer 35 (WTN 36 and RDN 37
(If the lower 2 bits of are equal and the upper 1 bit is different)
The RNR command is used in cases other than the above, and the RR command is used in cases other than the above. The S and R bits of the RR and RNR commands are set to "0". In case of using any of the above commands,
N(R) of bits 5 to 6 of that command to VRCN44
Setting the value to this value and sending it is considered a reception report.
When the TP control 27 transmits the RNR command as described above, it notifies the block reception control 29, and in the subsequent reception operation, the block reception control 29 does not receive the command if it is determined to be an SD command. Throw away.

The TP control 27 monitors the count of the reception buffer 35,
When the RDN 37 is updated, an RR command is sent to notify the other party's SCC, and the SD command reception prohibition of the block reception control 29 is released. The TP control 27 of the other party's SCC is R.
After receiving the NR command, stop sending one command and start the RR command.
Resumes upon reception of command. The DIP control 27 performs the following processing in order to automatically retransmit when one command is not normally received by the other party's SCC. TP control 2
Reference numeral 7 has a timer, and each time one command is transmitted, the timer is reset to start timing, and the timing is stopped when the counters VSCN42 and CACN43 of the command register become equal in the reception sequence number checking process described above. VSCN4 within a certain period of time set by the timer.
If 2 and CACN43 do not match,
It is assumed that the reception confirmation cannot be normally obtained, and a retransmission check operation is started. First, the TP control 27 is RR or R.
Send the NR command with the S bit set to "1" and the R bit set to "0". The use of the RR command and the RNR command depends on the state of the reception buffer 35, as described above. When the TP control 27 of the partner SCC receives this command, it returns an RR or RNR command with both the S bit and the R bit set to "1" to indicate that it is a response to the retransmission check. N(R) of this command is the V of the other SCC.
This is the value of RCN44, and indicates the next sequence number of one command that has been normally received by the other party's SCC. T.P.
When the controller 27 receives the response RR or RNR command, it executes the reception sequence number check process using the N(R) in the same manner as described above. As a result, CACN43 and N
(R) are equal, CACN43 and VSCN4
If 2 are not equal, this indicates that the already transmitted LTP commands from the register pointed to by CACN 43 to the register immediately before the register pointed to by VSCN 42 have not been received. Therefore, in this case N
The value of (R) is set in VSCN 42 and retransmission is started from the register indicated by the new value of VSCN 42.
This control is as explained in the transmission of one command above. As is clear from the above, according to the present invention,
By managing data and command transmission buffers with a small number of control counters, data transfer in units of flocks, reception confirmation, and retransmission processing are automatically performed, reducing the processing overhead of the CPU that was previously used for this purpose. Since it is possible to realize high-speed and highly reliable data transfer between subsystems by significantly reducing the amount of noise, the processing efficiency of the data processing system can be significantly improved.

[Brief explanation of the drawing]

Fig. 1 is a system configuration diagram that performs subsystem coupling using conventional CTCA, Fig. 2 is a system configuration diagram of the present invention, Fig. 3 is a conceptual diagram of connection of transmitting and receiving subchannels, and Fig. 4 performs bidirectional communication. Connection conceptual diagram, Figure 5 is a diagram showing the queue element on the main memory and its control block, Figure 6 is a diagram showing the LTP command, Figure 7 is an explanatory diagram of the startup sequence, and Figure 8 is the block of the queue element. Figure 9 is a diagram explaining the division, Figure 9 is a diagram explaining the data transfer sequence,
Fig. 0 is an explanatory diagram of the stop sequence, Fig. 11 is a block diagram of the SCC configuration, Fig. 12 is a diagram showing transmitting and receiving buffers and control counters, Fig. 13 is an illustration of the TP command, and Fig. 14 is a diagram of the TP command. Command code example diagram, 1st
Figure 5 is a diagram showing the command register and control counter;
FIG. 16 is a diagram showing an example of the configuration of block transmission control, and FIG.
The figure is a diagram showing a configuration example of block reception control. In the figure, 1 is the main storage device, 2 is the CPU, 3 is the SCC which is a data transfer device, 6 and 7 are transmission subchannels, 8 and 9 are reception subchannels, 27 is TP control, 2
8 is bu. 29 is block reception control, 30 is a transmission buffer, 31, 32, 33 are transmission buffer control counters, 35 is a reception buffer, 36, 37 are reception buffer control counters, 4 command registers, 41, 42,
43 indicates a control counter of the command register. Figure 1 Figure z Figure Father 3 Figure Eagle 4 Figure Father S Figure Tortoise 8 Figure Multi 5 Crab You 7 Figure Ax q Figure ゑ'04 key'Figure light off the figure'That figure '5 Figure Ax '3 Figure Ding P ] Cloak moxibustion '4 figure? 1 diagram of code

Claims (1)

[Claims] 1. In a data transfer device connected to each of two subsystems of a data processing system and mutually connected by a communication path to control data transfer, the data transfer control is performed by sending and receiving commands. The command includes at least a data command indicating that data is to be transferred, is specified by a buffer number, is used in the order of the buffer number, and is a plurality of buffers for storing transmission data, among the buffers. a first counter indicating the buffer number of the oldest buffer currently in use; a plurality of registers, identified by register numbers, used in the order of the register numbers, and storing commands to be sent; a second counter indicating the register number of the oldest register in use, appending that register number as a transmission sequence number to the command stored in said register; and if said command is a data command, said register number; means for reading the data of a specific buffer according to the buffer number and length stored in the data command, adding it to a data command, and transmitting it to the communication channel; means for receiving the command, data, and the sequence number added thereto on the communication channel; , means for sending a number next to the latest received sequence number to the communication channel, and means for receiving the number, and when receiving the number, steps the second counter until it becomes equal to the number. In the process of incrementing, the first counter is incremented by a number equal to the number of data commands stored in the register pointed to by the second counter.
A data transfer device characterized by incrementing a counter. There are 2^m buffers, where 2 m is an integer, and the buffers are used repeatedly in the order of the buffer numbers, and have a first counter that indicates the first buffer that is not in use, and the third counter and the first buffer 1 counter consists of m+1 bits, and the increment of both counters is 2^m^+^1
The third counter is incremented from -1 to 0, and the third counter is not incremented when the values of both counters differ only in the value of their most significant 1 bit. The data device according to paragraph 1. 3. There are 2^n registers, where n is an integer, and the registers are used repeatedly in the order of register numbers, and have a fourth counter that indicates the first register that is not in use. The counter 2 is composed of n+1 bits, and the increment of both counters is 2^n^+^1
The fourth counter is incremented from -1 to 0, and the fourth counter is not incremented when the values of both counters differ only in the value of the most significant 1 bit.
A data transfer device according to claim 1 or 2.