JPS6087591A - Multiplex signal receiver - Google Patents

Abstract

PURPOSE:To attain the information of a fault to a recipient in an understandable way by using a capacitor for the detection of fluctuation of average luminance level at each field so as to raise alarm in the reception of character broadcast superimposed during the vertical blanking period of a TV signal. CONSTITUTION:A multiplex signal such as character broadcast or the like transmitted while being superimposed during the vertical blanking period of the TV signal is received and its video detection output enters a buffer amplifier 16, its output is given to two capacitors 24, 34 via switches 20, 30 and a charge proportional to the average luminance level (APL) at each field is stored respectively in the capacitors. If the APL during the storage is fluctuated largely, the relation of ON/OFF of transistors 27, 37 is inverted, its change is detected by a detection circuit 39, the reverse change is detected by a detection circuit 67, a character ''input failure'' is formed from an alarm raising circuit 43 by one output of both the detection circuits and the possibility of a fault of a character signal is displayed on a CRT based on the APL fluctuation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus for receiving multiplex signals such as teletext broadcasts transmitted superimposed on the i direct retrace period of a television digital signal.

Conventional configuration and its problems FIG. 1 shows an example of a television multiplex signal receiving apparatus.

The figure shows a conventional teletext receiver. The problem with this device is that the TV signal (video signal) has an average S level (APL).
Errors in the reception of text signals occur when there is a large change in the text signal, but the receiver does not know whether the cause of the error lies in the text broadcasting receiver or in a change in the position of the message being sent.

In the part of the conventional example in FIG. 1, 1 is a tuner, 2
is a VIP circuit, 3 is a detection circuit, 4 is a chroma/video processing circuit, 6 is a synchronization separation circuit, 6 is a horizontal AFC-oscillation circuit, 7 is a color subcarrier regeneration circuit, 8 is a slice circuit, and 9 is a konkomi A clock generation circuit, 10 a write/read control circuit, 11 a read clock generation circuit, 12 a main memory,
13 is a circuit that switches and mixes 40 outputs and 12 outputs, 1
4 is a cathode ray tube.

In Jurai's circuit, when the APL of the video signal suddenly changes significantly or when the circuit operation of the receiver becomes defective, the operation of the slice circuit becomes abnormal and reception errors occur, causing white noise on the screen. , missing characters, missing lines, 2 incorrect colors, etc. It was unclear whether this phenomenon was due to a problem with the receiver itself or an abnormality in the transmitted signal.

Purpose of the Invention In view of such conventional inconveniences, the present invention aims to identify the cause of the inconvenience when the above-mentioned inconvenience occurs.
It is an object of the present invention to provide a multi-N signal receiving device capable of detecting and displaying a constant 'L7i'AP'L fluctuation due to an abnormality of 100 or more.

Structure of the Invention FIG. 2 shows -A/11! of the present invention! In the figure, 1 is a tuner, 2 is a VIN circuit, 3 is a detection circuit, 4 is a chroma and video processing circuit, 6 is a synchronization separation circuit, Horizontal AFC/oscillation circuit, 7 is color-carrier wave (fsc
)+4 In the raw circuit, I, 1 to 7 are similar to the circuit of a color television receiver. 8 is 2 after shaping the detection output.
9 is a clock generation circuit for sampling character signals; 1o is for writing to main memory 12;

11 is the read clock generation port of the main memory 12, IS, 12 is the main memory, and 13 is a circuit that mixes or switches the output of the main memory 12IllP readout and the output of the wave circuit 4, and outputs it. 14 is a color cathode ray tube. 16 is an APL variation/production circuit which is a feature of this device.

As shown in Figure 3, the method for teletext broadcasting is to superimpose a 296-bit binary coded teletext signal at the 20th d of the vertical blanking period (VBL) as shown in Figure 3. The committee has submitted a report and it has been put into practical use. As shown in Figure 4, there are six types of packets for this binary code, and among these, a page control packet (PAP) is sent with a code indicating the number of examiners. Determine the type of teletext screen and extract the screen of the specified program. The above-mentioned configurations of 751< minutes 1 to 14 are known as normal teletext receivers (pattern system).

In FIG. 2, 16 is a circuit that detects and displays fluctuations in the APL of the video signal. When converting the large-character signal received by the slice circuit 8 into a binary code, the slice level is set based on the black level or pedestal level, but if the APL of the video signal changes significantly, the black level or pedestal level changes. changes. Therefore, if the slice level is fixed, or if the time constant is large even if the slice level is changed using automatic tracking, the relationship between the character signal and the slice level may become inappropriate. , the output of the slice circuit 8 becomes irregular (the waveform on the sending side cannot be reproduced!).

Such conditions often occur in current television broadcasting when signal sources are switched during news broadcasts, and errors often occur even when the output signal of the slice circuit 8 is processed at such times.

Therefore, when the APL changes significantly, there is a screen that detects it and displays a message indicating that there is a possibility that an error may occur in the character signal being received, or when it is temporarily not possible to receive the character signal, it is possible to detect the cause. It is preferable in the UK to indicate that the problem is based on APL fluctuations, as this allows the receiver to be easily informed that the problem is not a receiver failure.

Next, an embodiment of the present invention having such an APL fluctuation detection and display function will be described in detail with reference to FIGS. In Figure 6, parts with the same functions as those in Figure 2 are marked with the same U symbol, and parts 20 to 68 are A.
This shows a specific configuration of the i'L fluctuation detection circuit 15.

First, the video detection output of the received signal is transmitted to the buffer 7 amplifier 16.

16 may be an AC-coupled emitter follower circuit.

The output of the buffer 7 amplifier 16 is switched by FMT20.
30 to the first set of two capacitors 24.degree. 34. Since the portions 20 to 28'' and the portions 30 to 38 have the same function, only the portions 20 to 28 will be described here. A gate pulse shown at φ46 in FIG. 7 is applied to the switching FKT 20, and when it is at a low level, it becomes -vbb, so the switching FET 20 is cut off during the period when the gate pulse φ46 is at a low level. Details will be described later.

Switching Fh: When T20 and T30 are alternately turned on for each field, charges proportional to the APL of each field are alternately stored in the capacitor 24.34. This capacity 11
If 24 and 34 are alternately charged and discharged every frame, 1
At the end of the field, the AFL of the field that has just ended and the field before it are stored in 24 and 34, respectively. Therefore, when the AFL between them fluctuates greatly and the output r of the capacitance 24.30 of both exceeds a certain value, the on/off relationship of the transistors 27 and 37 becomes reversed, and the change becomes a change structure. It is detected by circuit 39.

The AFL fluctuation detection circuit 67 has the same configuration as the parts 20 to 39, and the polarity is reversed only by manual operation.

The operation will be described in detail below with reference to FIGS. 4 to 8. The output of the detection circuit 3 is shown in FIG. 6 ψ1. The output of the synchronous separation circuit 6 is ψ2. Horizontal AFC/oscillator circuit 6
The output of is cut off at φ3 and can be used as a horizontal blanking pulse. The output of the blanking pulse generation circuit 17 is φ6.
ψ16, and is formed from the output of the sync separation circuit 6 and the output of the vertical pulse generation circuit 19. ψ6 indicates the first field signal, and ψ16 indicates the next field signal.

The vertical pulse generating circuit 19 divides ψ2 to form vertical pulses ψ4 and $201 (second pulse φ2°).The 0 frame pulse generating circuit 18 divides ψ4 to form a frame pulse ψ1□. 46 is a NANI) gate whose output is ψ4. becomes.

47 is a base leak resistance, 48 is a switching transistor, 23 is its collector load, and the switching FJ! :T20 is blocked.

On the other hand, since the output of the inverter a44 is added to the NAND gate 46, the output is the same as that shown in FIG. The resistor 6o has the same role as 47, and the resistor 33 is a load resistance for the transistor 49, and its output is cut off except during the high level period of φ46 in FIG.

Next, the ANL) gate 61 will be explained.
Since the human power of the ID gate 61 is φ2o and ψ1□, its output is ψ6. So, switching FtT20
At T24, a little before turning on from °r25, ψ61 is applied to the base of the transistor 22, and the transistor 22 becomes conductive for 1H period, discharging the charge in the capacitor 24. 53 is a resistor inserted to protect the gate 61 of the TTL circuit since the base of the transistor 67 is pulled by -vbbL/c. Transistor 57 is a switching transistor, and resistor 66 is a transistor 670 base leak resistance.

Now, the above explanation is 20-28, 45, 47.

48, '61.53.55.57, this is the part that passes through /J in the second field, 30-38, 46, 49, 60, 62°54.66.
58 is the first field and operates in the same way.Resistor 29 is the common emitter resistance of the differential circuit, and transistors 27 and 37 constitute the differential circuit. 26
, 28 , 29 , 35 , 36 .

I have selected 38. The change detection circuit 39 is a circuit that detects a change by determining whether the potential is at a low level or a high level during a high level period of ψ4, for example. The change detection circuit 39 can detect a change in the I/i state of any of the transistors 27, 37, that is, a part of the change in Ai'L. The rest are detected at 67. 41 is an OR gate, and the output of 42tri41 is ψ
This is a NAND gate that gates the change detection circuit 39.67 to eliminate malfunctions of the change detection circuit 39.67.If the output of the rJAND gate 42 becomes a low level, the warning generation circuit 4
In step 3, the words "input error" are formed and displayed on the CRT 14, or by flashing the light emitting diode of the indicator, etc., to indicate that there is a possibility of an error in the reception of the character signal based on the i'L fluctuation. . - Now, the operation □ of parts 20 to 38 will be explained with reference to FIG. In Fig. 8, T14'T24...T12~''131 T22~T23°...T3 slightly before T324
22 to 101 of ``323'', that is, the voltage of ``v24'' 34 (father is T124'' 134) during the period when ψ4 is at a high level, but in FIG. 8, ``T14. T24
°°.

...It is written according to the time of T324. Also, v2
4゜v34 is the base% of the transistor 27.37, as shown in Figure 6] v24I'iT2.
It changes from ~T31, but does not change from ``31~°r44.Similarly, from V 341d T,, 6 to T21
L'K L 'I' 21 It does not change until Kara T34. However, if we consider that the time to be compared is only the period when ψ4 is at a high level, both v24 and v34 are constant, so
In FIG. 8, the change of "24+v34" is shown in frame units.

If we decide to detect a change when the AFL changes by 3/4 or more between the high level H and the low level L, then in FIG.

15 B5. 116I 1su5 195T206'
"295 changes correspond to this." 14°T24...
...“If the transistor 22 or the transistor 32 is conductive at T324, then v24°V3
4 is slightly lower than the low level L as shown in FIG.

Now, since the state of the collector of TR27 before T14 is unknown, the state of the collector before T14 is unknown.
24. ......T341 T44...Tn
In 0T24, where it is not known whether low level L or high level H, v24 is low level L and v34 is high level H, transistor 27 is cut off and the collector is a high level tonal. From then on until 'r 94, v24≧V34+-j(
vH-■, ), so the transistor 27 is cut off. In r94, v24 is v34 (VH
-VL) becomes high level and transistor 2 becomes conductive, and v2□ becomes low level.At 0°r264, the change in adjacent fields is small, but the change in field one field away is large. Considering the general operation of character signal processing circuits in which v2□ changes over time, it is often better to detect changes in each frame rather than in each field, so this is intentionally removed. You don't have to.

'296 change does not appear in v2□, but this is because p
, since it is detected by v, 2□ of the PL change detection circuit 67,
■ If we take the logical sum of 27, V, and the falling of 2□ to create vX, then after 1 field, T2
35~T265 part tr, r27, ('-Q after t, ) downward pulse is 1! I get caught.

Now, ■, 24. v134. ■, 2□As shown in Figure 6, the output of the Buffel amplifier 16 is transferred to the inverter 4.
Invert with o, s(, 1"j!: TI 20, 130
Adding to. (The fluctuation detection circuit 67 includes 20 to 39.
It has exactly the same configuration as the circuit, and here, although not shown, 1
20 becomes 2o, 121 becomes 21, ... 139 becomes 39, and so on! L corresponds. However, circuit constant 1iFi difference fx le lrs, this t:J:, T1241 T134
as v24. This is to perform f:I on v34. ) Transistor 127 is T24tef;Ll! 1 piece °
r34"C14m, and the transistor 127 becomes conductive at 0゛L"3゜4, which is blocked up to T304. As stated above, the circuit from 20 to 39.67 is
-r + V, 27 b”I'Ib rel.

Generally, since the change in the collector voltage of the transistor 27 in FIG. 5 is not at the rTL level, it is converted to the "I"I' L level by the circuit consisting of 69 to 61 in FIG. 9. 9th
In the figure, the collector of transistor 27 is connected from 6V to 0.
When the voltage drops by 7V or more, the transistor 60 becomes conductive. If the resistor 69 is selected to be small, the collector of the transistor 6o rises above the high level H of °rTL. This is added to the NANO gate 63 via the TTL of Basonga. Except when φ4 is at high level, NAND gate controller 3
output is always at a high level. When ψ4 is at a high level and the output of the buffer 762 is at a high level, that is, when v24 is at a low level, the output of the NAND gate 63 changes from high level to low level. The integrating circuit consisting of a resistor 64 and a capacitor 66 is used to remove noise with a small pulse width. The pulse width of the monostable multi 66 is chosen narrowly and its output is directed upward. In FIG. 8 Vx, the width is ignored.

The same applies to the transistor 127, and the OR gate 41 forms the logical sum of the outputs of the monostable multipliers 66 and 166. 01 (The output of the gate 41 is a pulse in the opposite direction to vx in FIG. 8, and the output of the rJAND gate 42 is vx.

Effects of the Invention Thus, according to the present invention, if the A of the television screen is
Even if an error occurs in character signal extraction 9 or judgment processing due to a sudden change in PL, it is possible to clearly inform the receiver that the error is caused by the sending side, making it convenient to use. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional multi-7JI signal receiving device, FIG. 2 is a block diagram of a multiplex signal receiving device according to an embodiment of the present invention, and FIG. Figure 4 is a waveform diagram showing the manner in which the character signal is superimposed, Figure 4 is a waveform diagram showing each taper of the character signal, Figure 6 is a detailed diagram of the device, and a high-level diagram explaining Mll. Figure 6. FIGS. 7 and 8 are a waveform diagram 1 of each part, and FIGS. 9 t and 8 are partial circuit diagrams. 3...Detection circuit, 6...Cyclic column circuit, 6...Horizontal AFC circuit, 16...
APL... Fluctuation, production circuit, 17...
Blanking pulse forming circuit, 18... Frame pulse forming circuit, 19... Vertical pulse generating circuit, 20.30 Old... Transistor switch, 24
, 34...Capacity. Name of agent: Patent attorney Toshi Nakao (1 person)

Claims (1)

[Claims] In addition to providing a route for extracting and processing the binary A3 signal that is superimposed and sent during the vertical retrace line of television No. 18, the television video signal is manually input alternately for each field. The difference between the average luminance level of the two capacitors of the first set, which crosses the average luminance level by approximately one frame at a time, is constant 11μ. a first circuit that generates an output when the above value is reached, and a second circuit that inverts the video No. 16 and alternately manually inputs it for each field, and alternately stores the average luminance level for approximately one frame at a time. a second circuit that generates an output when the difference between the two capacitors of the set and the average luminance level stored in these capacitors exceeds a certain value;
1. A multiplex four-digit receiving device comprising a circuit for forming a logical sum of the outputs of the circuits, and a circuit for generating a warning based on the logical sum output.